With Particular Conductive Connection (e.g., Crossover) Patents (Class 174/261)
  • Patent number: 9012789
    Abstract: An electronic component assembly and a method for making an electronic component assembly. A non-limiting example electronic component assembly may, for example, comprise a lower component comprising a plurality of upward extending pins, and an upper component comprising a plurality of respective terminals, each which comprising a respective reflowable conductive structure that extends downward to a respective one of the plurality of upward extending pins.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: April 21, 2015
    Inventors: Akito Yoshida, Mahmoud Dreiza, Curtis Michael Zwenger
  • Patent number: 9012785
    Abstract: A flexible multilayer substrate includes a multilayer body including a plurality of laminated resin layers. The multilayer body includes an innermost surface, which is a surface on an inner side when the substrate is bent, and an outermost surface, which is a surface on an outer side when the substrate is bent. Each of the plurality of resin layers includes a skin layer on one surface. Lamination of the multilayer body includes a skin layer joint plane at one location at a central portion in the thickness direction, and the skin layer and other surface come in contact with each other at another location along the central portion in the thickness direction. A skin layer joint plane is arranged on a side closer to the innermost surface than a central plane in the thickness direction of the multilayer body.
    Type: Grant
    Filed: October 7, 2013
    Date of Patent: April 21, 2015
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Yoshihito Otsubo
  • Publication number: 20150103494
    Abstract: Printed circuit boards are provided. The printed circuit board includes an insulation layer, an interconnection portion and a metal layer. The insulation layer has a flat plate shape and includes a top surface and a bottom surface. The interconnection portion is disposed on at least one of the top and bottom surfaces of the insulation layer. The interconnection portion includes a plurality of interconnection patterns. The metal layer covers the plurality of interconnection patterns of the interconnection portion. Related semiconductor packages are also provided.
    Type: Application
    Filed: October 14, 2014
    Publication date: April 16, 2015
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hee-jeong Kim, Eun-Chul AHN, Yong-Kwan LEE
  • Publication number: 20150101855
    Abstract: A flat cable assembly comprises: a flat cable; a PCB electrically connected to the flat cable; and a retainer formed on the joint of the flat cable and the PCB. The flat cable defines a metallic shielding layer having extension portions formed at two sides of the flat cable, the PCB defines grounding conductive pads electrically connected to the extension portion.
    Type: Application
    Filed: October 9, 2014
    Publication date: April 16, 2015
    Inventors: Jerry WU, Jun CHEN, Fan-Bo MENG
  • Publication number: 20150102835
    Abstract: A substrate plate is provided for at least one MEMS device to be mounted thereon. The MEMS device has a certain footprint on the substrate plate, and the substrate plate has a pattern of electrically conductive leads to be connected to electric components of the MEMS device. The pattern forms contact pads within the footprint of the MEMS device and includes at least one lead structure that extends on the substrate plate outside of the footprint of the MEMS device and connects a number of the contact pads to an extra contact pad. The lead structure is a shunt bar that interconnects a plurality of contact pads of the MEMS device and is arranged to be removed by means of a dicing cut separating the substrate plate into a plurality of chip-sized units. At least a major part of the extra contact pad is formed within the footprint of one of the MEMS devices.
    Type: Application
    Filed: October 10, 2014
    Publication date: April 16, 2015
    Applicant: OCE-TECHNOLOGIES B.V.
    Inventors: Maikel A.J. HUYGENS, René J. VAN DER MEER, Reinier PANNEKOEK, Alex N. WESTLAND
  • Publication number: 20150103500
    Abstract: Provided is an electronic component including a pad region including a plurality of pads extending along corresponding extension lines and arranged in a first direction, and a signal wire configured to receive a driving signal from the pad region, wherein the plurality of pads include a plurality of first pads arranged continuously and a plurality of second pads arranged continuously, and extension lines of the plurality of first pads substantially converge into a first point and extension lines of the plurality of second pads substantially converge into a second point different from the first point.
    Type: Application
    Filed: December 18, 2014
    Publication date: April 16, 2015
    Inventors: Han-Sung BAE, Wonkyu KWAK, Cheolgeun AN
  • Patent number: 9004937
    Abstract: A through-the-hole (TTH)/surface mount (SMT) insulation piercing connector includes one or two spaced electrical contacts. Each contact has a flat plate portion and integrally-formed legs. An L-shaped hook portion on the flat plate portion has a piercing tip pointed in a direction away from the legs. The piercing tip is spaced from the flat plate portion, the flat plate portion being configured and dimensioned to bend in the direction towards the piercing tip when pressed to urge an insulated wire onto said piercing tip to cause it to penetrate the wire insulation and make electrical contact with the internal conductive wires or strands within the wire. The legs are insertable into mounting holes in a substrate for direct TTH mounting in a PCB or to be secured to a header provided with mounting holes by TTH soldering and surface mounting by a pick-and-place machine acting on the header.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: April 14, 2015
    Assignee: Zierick Manufacturing Corporation
    Inventor: Raffaele Tarulli
  • Patent number: 9006586
    Abstract: One embodiment provides a wiring substrate including: a core substrate having an insulative base member, the insulative base member having a first surface and a second surface, a plurality of linear conductors penetrating through the insulative base member from the first surface to the second surface; an inorganic material layer joined to at least one of the first surface and the second surface of the insulative base member; and a penetration line penetrating through the inorganic material layer, wherein one end of the penetration line is electrically connected to a corresponding part of the linear conductors, without intervention of a bump.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: April 14, 2015
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Michio Horiuchi, Yasue Tokutake, Yuichi Matsuda, Tomoo Yamasaki
  • Publication number: 20150096797
    Abstract: Disclosed herein are a package board and a method of manufacturing the same. The package board includes: an insulating layer; and a ground layer formed in the insulating layer, wherein one side of the ground layer is formed so that a plurality of pattern parts having a plurality of diameters are spaced apart from each other and the other side thereof is continuously formed.
    Type: Application
    Filed: April 8, 2014
    Publication date: April 9, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventor: Heung Ku Kim
  • Patent number: 8999537
    Abstract: A battery pack configured to prevent excess solder material from flowing down onto a protective circuit module (PCM) is disclosed. According to some aspects, the battery pack includes at least one battery cell, a protective circuit module (PCM) electrically connected to the battery cell, and a conductive tab configured to electrically connect the battery cell to the PCM. A tapered through hole is formed in the PCM so that the conductive tab is inserted into and fixed to the through hole.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: April 7, 2015
    Assignee: Samsung SDI Co., Ltd.
    Inventor: Eunyoung Kim
  • Patent number: 9000306
    Abstract: An electronic apparatus (100) has an electronic device (151), a power supply plane (121) and a power supply plane (122) disposed with a gap (123) therebetween, a connection member (152) that electrically connects the power supply plane (122) and the electronic device (151), a ground plane (141) facing the power supply plane (121) or the power supply plane (122), a connection member (153) that electrically connects the ground plane (141) and the electronic device (151), a plurality of conductor elements (131) that is repeatedly arrayed, and open stubs (111) formed at a location overlapping the gap (123) included in an area surrounded by the conductor elements (131). In addition, at least some of the open stubs (111) face the power supply plane (122) which is not in contact with the open stubs (111).
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: April 7, 2015
    Assignee: NEC Corporation
    Inventors: Hiroshi Toyao, Manabu Kusumoto, Naoki Kobayashi, Noriaki Ando
  • Patent number: 9000307
    Abstract: The disclosed structure (10) is provided with: at least three conductors (111, 131, 151) which face one-another; a through-via (101) which passes through each of the conductors (111, 131, 151); openings (112, 152) which are provided so as to surround the circumference of the through-via (101); and conductor elements (121, 141) which are located in different layers to those in which the conductors (111, 131, 151) are located, and which are connected to the through-via (101). Facing opening 112 is conductor element 121, which is larger than said opening (112), and facing opening 152 is conductor element 141, which is larger than said opening (152).
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: April 7, 2015
    Assignee: NEC Corporation
    Inventors: Hiroshi Toyao, Naoki Kobayashi, Noriaki Ando
  • Patent number: 9001521
    Abstract: An assembly including: a first substrate having a first surface and housing a first electrical-interconnection element and a second electrical-interconnection element in a position corresponding to the first surface; a second substrate having a second surface, housing a third electrical-interconnection element and a fourth electrical-interconnection element in a position corresponding to the second surface, and provided with a dielectric layer extending on top of the third interconnection element; and a first bump and a second bump made of conductive material, extending between the first electrical-interconnection element and the third electrical-interconnection element and, respectively, between the second electrical-interconnection element and the fourth electrical-interconnection element, at least partially aligned to the respective electrical-interconnection elements, the first bump being ohmically coupled to the first interconnection element and capacitively coupled to the third interconnection element,
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: April 7, 2015
    Assignee: STMicroelectronics S.r.l.
    Inventors: Roberto Canegallo, Mauro Scandiuzzo
  • Patent number: 8997341
    Abstract: It is an object of the invention to provide a method for producing a substrate for mounting a semiconductor chip, that can reduce bridging and allows excellent wire bondability and solder connection reliability to be obtained, even when forming fine-pitch wirings.
    Type: Grant
    Filed: September 6, 2010
    Date of Patent: April 7, 2015
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Yoshinori Ejiri, Kiyoshi Hasegawa, Takehisa Sakurai, Yoshiaki Tsubomatsu
  • Publication number: 20150092377
    Abstract: Embodiments of methods for forming microelectronic device packages include forming a trench on a surface of a package body between exposed ends of first and second device-to-edge conductors, and forming a package surface conductor in the trench to electrically couple the first and second device-to-edge conductors. In one embodiment, the package surface conductor is formed by first forming a conductive material layer over the package surface, where the conductive material layer substantially fills the trench, and subsequently removing portions of the conductive material layer from the package surface adjacent to the trench. In another embodiment, the package surface conductor is formed by dispensing one or more conductive materials in the trench between the first and second exposed ends (e.g., using a technique such as spraying, inkjet printing, aerosol jet printing, stencil printing, or needle dispense). Excess conductive material may then be removed from the package surface adjacent to the trench.
    Type: Application
    Filed: September 30, 2013
    Publication date: April 2, 2015
    Inventors: JASON R. WRIGHT, Michael B. Vincent, Weng F. Yap
  • Publication number: 20150092371
    Abstract: According to various embodiments, a contact pad structure may be provided, the contact pad structure may include: a dielectric layer structure; at least one contact pad being in physical contact with the dielectric layer structure; the at least one contact pad including a metal structure and a liner structure, wherein the liner structure is disposed between the metal structure of the at least one contact pad and the dielectric layer structure, and wherein a surface of the at least one contact pad is at least partially free from the liner structure, and a contact structure including an electrically conductive material; the contact structure completely covering at least the surface being at least partially free from the liner structure of the at least one contact pad, wherein the liner structure and the contact structure form a diffusion barrier for a material of the metal structure of the at least one contact pad.
    Type: Application
    Filed: September 27, 2013
    Publication date: April 2, 2015
    Applicant: Infineon Technologies AG
    Inventor: Dirk Meinhold
  • Publication number: 20150092378
    Abstract: A circuit board upon which to mount an integrated circuit chip may include a first interconnect zone on the surface of the circuit board having first contacts with a first pitch, and a second interconnect zone, surrounding the first zone, having second contacts or traces with a second pitch that is smaller than the first pitch. The first contacts may have a design rule (DR) for direct chip attachment (DCA) to an integrated circuit chip. The first contacts may be formed by bonding a sacrificial substrate having the first contacts to a surface of the board; or by laser scribing trenches where the conductor will be plated to create the first contacts. Such a board allows DCA of smaller footprint processor chips for devices, such as tablet computers, cell phones, smart phones, and value phone devices.
    Type: Application
    Filed: September 28, 2013
    Publication date: April 2, 2015
    Inventors: Mihir K. ROY, Mathew J. MANUSHAROW
  • Publication number: 20150090481
    Abstract: A manufacturing method of a package carrier includes the following steps. Firstly, two base metal layers are bonded together. Then, two supporting layers are laminated onto the base metal layers respectively. Next, two release metal films are disposed on the supporting layers respectively, wherein each of the release metal films includes a first metal film and a second metal film separable from each other. Next, two patterned metal layers are formed on the release metal films respectively, wherein each of the patterned metal layers is suitable for carrying and electrically connected to a chip. Then, the base metal layers are separated from each other to form two package carriers independent from each other. A package carrier formed by the manufacturing method described above is also provided.
    Type: Application
    Filed: November 22, 2013
    Publication date: April 2, 2015
    Applicant: Subtron Technology Co., Ltd.
    Inventor: Shih-Hao Sun
  • Patent number: 8993896
    Abstract: A lead electrode and a preparation method thereof are provided. The lead electrode includes an inner terminal, a lead, and an outer terminal, which are sequentially connected. The lead includes: an insulating substrate; an adhesive material coated on the insulating substrate, the adhesive material defining a trenched mesh; and a conductive material filled in the trenched mesh, wherein an angle formed by a grid line of the trenched mesh and a demolding direction is from 0° to 90°. Since the angle formed by the grid line and the demolding direction is very small, little adhesive material will be attached to the mold, such that the residues of the adhesive material are prevented.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: March 31, 2015
    Assignee: Nanchang O-Film Tech Co., Ltd.
    Inventors: Fei Zhou, Yulong Gao, Miaoqian Cao, Hongwei Kang
  • Publication number: 20150083479
    Abstract: A method of fabricating a capacitance touch panel module includes forming a plurality of first conductive patterns on a substrate comprising a touching area and a peripheral area along a first orientation, a plurality of second conductive patterns along a second orientation, and a plurality of connecting portions in the touching area; forming a plurality of insulated protrusions, in which each insulated protrusion covering one connecting portion, and forming an insulated frame on the peripheral area; and forming a bridging member on each insulated protrusion.
    Type: Application
    Filed: December 4, 2014
    Publication date: March 26, 2015
    Inventors: KAI MENG, LIEN-HSIN LEE
  • Publication number: 20150083478
    Abstract: The electric part to be soldered to a metal pad mounted on a printed circuit board, includes a first surface facing the metal pad, a second surface extending from the first surface in a direction away from the metal pad, and a third surface outwardly extending from the second surface, the second surface and the third surface defining a space in which solder is stored.
    Type: Application
    Filed: September 12, 2014
    Publication date: March 26, 2015
    Inventors: Takayoshi ENDO, Kenya ANDO
  • Publication number: 20150084090
    Abstract: External connection conductors are arranged on a back surface of a base material, and wiring conductors are arranged on a front surface. An insulating layer is provided on surfaces of the wiring conductors. Component mounting conductors are provided on a surface of the insulating layer. The component mounting conductor and the wiring conductor are electrically coupled to each other, and the component mounting conductor and the wiring conductor are electrically coupled to each other. The wiring conductor and the external connection conductor are electrically coupled by a conductor film on an inner wall surface of a hole provided between forming areas of the component mounting conductors. The wiring conductor and the external connection conductor are electrically coupled by a conductor film on an inner wall surface of a hole provided between the forming areas of the component mounting conductors.
    Type: Application
    Filed: December 1, 2014
    Publication date: March 26, 2015
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Masakazu FUKUMITSU, Yoshiharu YOSHII
  • Patent number: 8987608
    Abstract: A circuit structure includes an inner circuit layer, a first and a second dielectric layers, a first and a second conductive material layers, and a second and a third conductive layers. The first dielectric layer covers a first conductive layer of the inner circuit layer and has a first surface and first circuit grooves. The first conductive material layer is disposed inside the first circuit grooves. The second conductive layer is disposed on the first surface and includes a signal trace and at least two reference traces. The second dielectric layer covers the first surface and the second conductive layer and has a second surface and second circuit grooves. Widths of the first and the second circuit grooves are smaller than that of the reference traces. The second conductive material layer is disposed inside the second circuit grooves. The third conductive layer is disposed on the second surface.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: March 24, 2015
    Assignee: Unimicron Technology Corp.
    Inventors: Shang-Feng Huang, Cheng-Po Yu, Jen-Chi Cheng
  • Publication number: 20150075849
    Abstract: A semiconductor device includes a lead frame having a flag and leads surrounding the flag. The flag includes a first die attach area and an interposer area. An insulated layer with at least one conductive trace is formed on the interposer area.
    Type: Application
    Filed: September 17, 2013
    Publication date: March 19, 2015
    Inventors: Jia Lin Yap, Yin Kheng Au
  • Publication number: 20150075856
    Abstract: A cable backplane system includes a backplane having a plurality of openings extending between a front and a rear of the backplane. The backplane has mounting locations proximate the openings. Mounting blocks are coupled to the front of the backplane at corresponding mounting locations. The mounting blocks are secured to the backplane by fasteners. A cable rack is coupled to the rear of the backplane and has a tray with a frame surrounding a raceway and spacers coupled to the tray. The spacers hold corresponding cable connectors and are secured to corresponding mounting blocks to position the spacers and cable connector assemblies relative to the backplane. The cable connectors are received in corresponding openings in the backplane and are held in position relative to the backplane by the spacers and mounting blocks.
    Type: Application
    Filed: September 13, 2013
    Publication date: March 19, 2015
    Applicant: Tyco Electronics Corporation
    Inventors: Christopher David Ritter, Robert Paul Nichols, Brian Patrick Costello, Joshua Tyler Sechrist, Nathan Glenn Lehman
  • Patent number: 8982576
    Abstract: Provided is a printed wiring board including a power source, a plurality of LSIs, and a planar power supply wiring for supplying power from the power source to the LSIs. A plurality of partial wiring patterns each forming a current path from the power source to the LSIs are provided by forming gaps in the power supply wiring.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: March 17, 2015
    Assignee: NEC Corporation
    Inventor: Kazuhiro Kashiwakura
  • Patent number: 8981236
    Abstract: A printed circuit board includes a line intensive distribution area, a line sparse distribution area, a solder mask layer, and a signal layer. A first signal line is laid on the signal layer. The first signal line crosses the line intensive distribution area and the line sparse distribution area. The first signal line is narrower in the line intensive distribution area than in the line sparse distribution area. The solder mask layer is thicker in the line intensive distribution area than in the line sparse distribution area.
    Type: Grant
    Filed: December 29, 2012
    Date of Patent: March 17, 2015
    Assignees: Hong Fu Jin Precision Industry (WuHan) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventor: Feng Zhang
  • Publication number: 20150070854
    Abstract: The invention relates to an arrangement for increasing the insulation coordination between at least two electric potentials on a printed circuit board (2), said arrangement comprising the printed circuit board (2) and an insulation barrier (3), wherein the printed circuit board (2) has an opening (7) between the electric potentials, and the insulation barrier (3) is disposed on the printed circuit board (2) so as to be displaceble through the opening (7) and is designed such that the isolating distance between the two electric potentials can be enlarged by displacing the insulation barrier (3) relative to the printed circuit board (2). The arrangement makes it possible obtain a high packing density on the printed circuit board (2).
    Type: Application
    Filed: March 22, 2013
    Publication date: March 12, 2015
    Inventors: Frank Best, Marco Seelig
  • Patent number: 8975531
    Abstract: Various embodiments include interconnect structures and methods of forming such structures. The interconnect structures can include a composite copper wire which includes at least two distinct copper sections. The uppermost copper section can have a thickness of approximately 1 micrometer or less, which inhibits surface roughening in that uppermost section, and helps to enhance cap adhesion with overlying layers.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: March 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Felix Anderson, Zhong-Xiang He, Anthony K. Stamper
  • Patent number: 8973261
    Abstract: A manufacturing method of an object having a conductive line includes the following steps. A hardening layer and a conductive line layer are formed in an in-mold roller (IMR) material in sequence. The conductive line layer is formed on a non-conductive substrate by an IMR process. A carrier sheet is then separated to expose the hardening layer. A connecting piece is formed on the hardening layer. The connecting piece runs through the hardening layer by a connection process, and the connecting piece is electrically connected to the conductive line layer. Therefore, an object structure having the conductive line is formed.
    Type: Grant
    Filed: September 25, 2011
    Date of Patent: March 10, 2015
    Assignee: Getac Technology Corporation
    Inventor: Cheng-Hung Chiang
  • Patent number: 8975528
    Abstract: Even in an electronic device where electrodes are coupled electrically using a solder, sections to which electrodes of an electronic component are coupled are switched by a method other than changing circuits of the electronic component or changing circuits of a wiring substrate. The electronic device includes: a wiring substrate having two or more first electrodes over one surface thereof; and an electronic component having, over one surface thereof, two or more second electrodes arranged corresponding to the two or more first electrodes, respectively. At least one of the first electrodes is a specific electrode divided into two or more divided portions, and the divided portions are coupled to different wirings, respectively. Further, at least one of the divided portions is coupled to a corresponding second electrode through a solder.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: March 10, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Shuuichi Kariyazaki
  • Publication number: 20150060123
    Abstract: A method of assembling a flip chip on a leadframe package. A locking dual leadframe (LDLF) includes a top metal frame portion including protruding features and a die pad and a bottom metal frame portion having apertures positioned lateral to the die pad. The protruding features and apertures are similarly sized and alignable. A flipped integrated circuit (IC) die having a bottomside and a topside including circuitry connected to bond pads having solder balls on the bond pads is mounted with its topside onto the top metal frame portion. The top metal frame portion is aligned to the bottom metal frame portion so that the protruding features are aligned to the apertures. The bottomside of the IC die is pressed with respect to a top surface of the bottom frame portion, wherein the protruding features penetrate into the apertures.
    Type: Application
    Filed: September 4, 2013
    Publication date: March 5, 2015
    Applicant: Texas Instruments Incorporated
    Inventors: LEE HAN MENG @ EUGENE LEE, SUEANN LIM WEI FEN, ANIS FAUZI BIN ABDUL AZIZ
  • Publication number: 20150060127
    Abstract: A combined printed wiring board includes a multilayer printed wiring board, and a wiring film fixed to a surface of the multilayer printed wiring board and including a first wiring structure formed to connect multiple semiconductor elements and a second wiring structure formed to connect the multilayer printed wiring board and each of the semiconductor elements.
    Type: Application
    Filed: August 29, 2014
    Publication date: March 5, 2015
    Applicant: IBIDEN CO., LTD.
    Inventors: Makoto Terui, Takashi Kariya, Yoshinori Shizuno, Masatoshi Kunieda
  • Publication number: 20150061096
    Abstract: A semiconductor package includes a block having a first side, a second side opposite the first side and a recessed region extending from the second side toward the first side so that the block has a thinner part in the recessed region and a thicker part outside the recessed region. The semiconductor package further includes a first semiconductor die and a second semiconductor die each having opposing first and second sides. The first semiconductor die is disposed in the recessed region of the block and attached to the thinner part of the block at the first side of the first semiconductor die. The second semiconductor die is attached to the second side of the first semiconductor die at a first side of the second semiconductor die.
    Type: Application
    Filed: August 29, 2013
    Publication date: March 5, 2015
    Inventor: Kok Chai Goh
  • Publication number: 20150060124
    Abstract: A combined printed wiring board includes a multilayer printed wiring board having an outermost insulation layer, and a wiring film fixed to a portion of the outermost insulation layer of the multilayer printed wiring board. The wiring film includes dense-pitch pads formed on a semiconductor-mounting surface of the wiring film, the multilayer printed wiring board has sparse-pitch pads formed on a semiconductor-mounting surface of the multilayer printed wiring board, the dense-pitch pads are formed to facilitate electrical connection between a first semiconductor element and a second semiconductor element, and the sparse-pitch pads are formed to facilitate electrical connection between the multilayer printed wiring board and the first semiconductor element and/or the second semiconductor element.
    Type: Application
    Filed: August 29, 2014
    Publication date: March 5, 2015
    Applicant: IBIDEN CO., LTD.
    Inventors: Makoto TERUI, Takashi KARIYA, Yoshinori SHIZUNO, Masatoshi KUNIEDA
  • Publication number: 20150060125
    Abstract: A touch panel includes a substrate, a plurality of first axis electrodes, a plurality of second axis electrodes and a first insulation layer. Each first axis electrode includes a plurality of first sub-electrodes and a plurality of first connection parts disposed between two adjacent first sub-electrodes. The first sub-electrodes and the first connection parts are monolithically formed. Each second axis electrode includes a plurality of second sub-electrodes and a plurality of second connection parts disposed between two adjacent second sub-electrodes. The second sub-electrodes and the second connection parts are monolithically formed. The first sub-electrodes and the second sub-electrodes are disposed on an identical surface. The first insulation layer is disposed on and completely covers the first axis electrodes. The first insulation layer is partially disposed between the first connection part and the second connection part.
    Type: Application
    Filed: September 4, 2014
    Publication date: March 5, 2015
    Inventors: David E. Stevenson, Siang-Lin Huang, Chia-Chi Chen, Kuo-Chang Su
  • Publication number: 20150064849
    Abstract: A lead frame strip includes connected unit lead frames each having a die paddle, a tie bar directly connecting the die paddle to a periphery of the unit lead frame, leads directly connected to the periphery of the unit lead frame and projecting toward the die paddle, and an opening in the periphery adjacent the tie bar. The openings in the periphery of the unit lead frames are spanned with an electrically insulating material that connects the tie bar of each unit lead frame to the periphery of the unit lead frame. The direct connections between the tie bars and the periphery of the unit lead frames are severed prior to subsequent processing, so that the tie bars remain connected to the periphery of the unit lead frames by the electrically insulating material and the die paddles are electrically disconnected from the periphery of the unit lead frames.
    Type: Application
    Filed: August 30, 2013
    Publication date: March 5, 2015
    Inventors: Nee Wan Khoo, Lay Yeap Lim
  • Publication number: 20150062849
    Abstract: A wiring board includes a unit section including product portions, and a frame section formed along the periphery of the unit section. The frame section has a dummy pattern which includes conductive portions and connection lines such that the connection lines are formed in spaces between the conductive portions and linking the conductive portions.
    Type: Application
    Filed: August 28, 2014
    Publication date: March 5, 2015
    Applicant: IBIDEN CO., LTD.
    Inventors: Takema ADACHI, Satoshi Kondo
  • Patent number: 8969736
    Abstract: A cover insulating layer is formed on a base insulating layer. One of write wiring traces includes first to third lines, and the other write wiring trace includes fourth to sixth lines. The one and other write wiring traces constitute a signal line pair, the second and fifth lines are arranged on an upper surface of the cover insulating layer, and the third and sixth lines are arranged on an upper surface of the base insulating layer. At least parts of the second and fifth lines are respectively opposed to the sixth and third lines with the cover insulating layer sandwiched therebetween. The second and third lines are electrically connected to the first line, and the fifth and sixth lines are electrically connected to the fourth line. The fourth line is electrically connected to at least one of the fifth and sixth lines through a jumper wiring on a lower surface of the base insulating layer.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: March 3, 2015
    Assignee: Nitto Denko Corporation
    Inventor: Daisuke Yamauchi
  • Patent number: 8969735
    Abstract: A flexible metal interconnect structure for transmitting signals between IC devices in flexible electronic devices is formed between two compliant flexible material layers that are laminated together form a multi-layer flexible substrate. The interconnect structure is formed by two rows of spaced-apart conductive pads (metal islands) attached to the inside (facing) surfaces of the flexible material layers. Compliant micro-contact elements such as micro-springs provide sliding metal pressure contacts that maintain electrical connections between the islands during stretching of the composite sheet. Specifically, at least two micro-contact elements are attached to each metal island in one of the rows, with one element in sliding pressure contact with an associated first metal island in the opposing row and the second element in sliding pressure contact with an associated second metal island. The islands and sliding contacts can be patterned into high density traces that accommodate large strains.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: March 3, 2015
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Eugene M. Chow, Dirk DeBruyker
  • Patent number: 8969732
    Abstract: A printed wiring board includes a core insulation layer having via conductors through the core layer, a first structure including an interlayer insulation layer on first surface of the core layer and having via conductors through the interlayer layer in the first structure, and a second structure including an interlayer insulation layer on second surface of the core layer and having via conductors through the interlayer layer in the second structure. The interlayer layers have dielectric constants set to be 4.0 or lower for signal transmission at frequency of 1 GHz, the core layer has thermal expansion coefficient at or below Tg set lower than thermal expansion coefficients of the interlayer layers at or below Tg, the coefficient of the core layer at or below Tg is set to be 75 ppm/° C. or lower, and the conductors in the interlayer layers are stacked on the conductors in the core layer.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: March 3, 2015
    Assignee: IBIDEN Co., Ltd.
    Inventors: Tetsuo Amano, Toshio Nishiwaki
  • Patent number: 8969730
    Abstract: Printed circuits may be electrically and mechanically connected to each other using connections such as solder connections. A first printed circuit such as a rigid printed circuit board may have solder pads and other metal traces. A second printed circuit such as a flexible printed circuit may have openings. Solder connections may be formed in the openings to attach metal traces in the flexible printed circuit to the solder pads on the rigid printed circuit board. A ring of adhesive may surround the solder connections. The flexible printed circuit may be attached to the rigid printed circuit board using the ring of adhesive. An insulating tape may cover the solder connections. A conductive shielding layer with a conductive layer and a layer of conductive adhesive may overlap the solder joints. The conductive adhesive may connect the shielding layer to the metal traces on the rigid printed circuit board.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: March 3, 2015
    Assignee: Apple Inc.
    Inventors: Anthony S. Montevirgen, Emery A. Sanford, Stephen Brian Lynch
  • Publication number: 20150053474
    Abstract: An object of the present invention is to propose a functional element built-in substrate which enables an electrode terminal of a functional element to be well connected to the back surface on the side opposite to the electrode terminal of the functional element, and which can be miniaturized.
    Type: Application
    Filed: November 4, 2014
    Publication date: February 26, 2015
    Applicant: NEC CORPORATION
    Inventors: Yoshiki NAKASHIMA, Shintaro YAMAMICHI, Katsumi KIKUCHI, Kentaro MORI, Hideya MURAI
  • Publication number: 20150054145
    Abstract: An integrated circuit package having a die attach paddle, a power die mounted on the die attach paddle and a controller die mounted on the die attach paddle. The die attach paddle has at least one recessed portion at least partially underlying the controller die.
    Type: Application
    Filed: August 23, 2013
    Publication date: February 26, 2015
    Applicant: Texas Instruments Incorporated
    Inventors: You Chye How, Maria Christina Bernardo Violante
  • Patent number: 8963014
    Abstract: The present invention relates to a touch panel, comprising: a screen part comprising a first conductive pattern portion, and a router part comprising a second conductive pattern portion, in which the first conductive pattern portion and the second conductive pattern portion have the same line height, and there is no connecting portion in a region in which the first conductive pattern portion and the second conductive pattern portion are connected to each other, and a display apparatus comprising the same.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: February 24, 2015
    Assignee: LG Chem, Ltd.
    Inventors: Ji Young Hwang, In-Seok Hwang, Seung Heon Lee, Yong Goo Son, Beom Mo Koo
  • Patent number: 8964409
    Abstract: An electronic module with EMI protection is disclosed. The electronic module comprises a component (1) with contact terminals (2) and conducting lines (4) in a first wiring layer (3). There is also a dielectric (5) between the component (1) and the first wiring layer (3) such that the component (1) is embedded in the dielectric (5). Contact elements (6) provide electrical connection between at least some of the contact terminals (2) and at least some of the conducting lines (4). The electronic module also comprises a second wiring layer (7) inside the dielectric (5). The second wiring layer (7) comprises a conducting pattern (8) that is at least partly located between the component (1) and the first wiring layer (3) and provides EMI protection between the component (1) and the conducting lines (4).
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: February 24, 2015
    Assignee: GE Embedded Electronics Oy
    Inventor: Risto Tuominen
  • Patent number: 8959760
    Abstract: A method for manufacturing a printed wiring board, including providing a support board having a metal foil secured to the support board, forming a resin insulation layer on the metal foil, forming openings in the resin insulation layer, forming a conductive circuit on the resin insulation layer, forming in the openings via conductors to electrically connect the conductive circuit and the metal foil, separating the support board and the metal foil, and forming from the metal foil external terminals to electrically connect to another substrate or electronic component.
    Type: Grant
    Filed: August 15, 2011
    Date of Patent: February 24, 2015
    Assignee: Ibiden Co., Ltd.
    Inventors: Ayao Niki, Kazuhisa Kitajima
  • Publication number: 20150049444
    Abstract: A conductor pad and a flexible circuit including a conductor pad are provided. The conductor pad includes a first contact region, a second contact region, and a body portion configured to establish a conductive path between the first contact region and the second contact region. The body portion includes a perimeter edge having at least a first convex segment and a second convex with a first non-convex segment disposed between the first convex segment and the second convex segment. A method of constructing a flexible circuit to facilitate roll-to-roll manufacturing of the flexible circuit is also provided.
    Type: Application
    Filed: May 31, 2014
    Publication date: February 19, 2015
    Applicant: OSRAM SYLVANIA INC.
    Inventors: Sridharan Venk, Earl Alfred Picard, JR., Qi Dai, Richard Garner
  • Publication number: 20150047891
    Abstract: A method includes forming a hard mask over a base material, and forming an I-shaped first opening in the hard mask. The first opening includes two parallel portions and a connecting portion interconnecting the two parallel portions. Spacers are formed on sidewalls of the first opening. The spacers fill an entirety of the connecting portion, wherein a center portion of each of the two parallel portions is unfilled by the spacers. The hard mask is etched to remove a portion of the hard mask and to form a second opening, wherein the second opening is between the two parallel portions of the first opening. The second opening is spaced apart from the two parallel portions of the first opening by the spacers. The first opening and the second opening are then extended down into the base material.
    Type: Application
    Filed: August 16, 2013
    Publication date: February 19, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Ying Lee, Jyu-Horng Shieh
  • Patent number: 8957320
    Abstract: A printed wiring board includes a substrate having an accommodation section having multiple opening portions, multiple electronic components accommodated in the opening portions, respectively, a filler resin provided in the opening portions in the substrate such that the electronic components are secured in the opening portions in the substrate, a resin insulation layer formed over the substrate and the electronic components, a conductive layer formed on the resin insulation layer, and via conductors formed in the resin insulation layer and connecting the conductive layer and the electronic components. The opening portions are connected to each other.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: February 17, 2015
    Assignee: Ibiden Co., Ltd.
    Inventors: Toshiki Furutani, Yukinobu Mikado, Shunsuke Sakai, Yusuke Tanaka