Metal Is Elemental Copper, An Alloy, Or Compound Thereof Patents (Class 216/105)
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Patent number: 5904863Abstract: A process for etching the sides of a trace remove the feet which extend laterally out from the sides and over a circuit board substrate adjacent the trace.Type: GrantFiled: April 30, 1997Date of Patent: May 18, 1999Assignee: Coates ASI, Inc.Inventors: Michael M. Hatfield, Marshall I. Gurian
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Patent number: 5900186Abstract: A composition for reducing a copper oxide layer to metallic copper so as to facilitate bonding a resin to the metallic copper is disclosed. The composition is an aqueous reducing solution containing a cyclic borane compound. Examples of such cyclic borane compounds include those having nitrogen or sulfur as a ring-forming member, such as morpholine borane, piperidine borane, pyridine borane, piperazine borane, 2,6-Iutidine borane, 4-methylmorpholine borane, and 1,4-oxathiane borane, and also N,N-diethylaniline borane.Type: GrantFiled: February 25, 1998Date of Patent: May 4, 1999Assignee: Morton International, Inc.Inventors: John Fakler, Michael Rush, Scott Campbell
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Patent number: 5893983Abstract: A technique for polishing an exposed surface of metal on a substrate to remove defects from mechanical working of metals, such as burrs and pigtails resulting from drilling, and defects from plating, such as nodules and depressions, is provided. The substrate has an exposed metal surface such as copper thereon which is to be treated to remove defects. A planarizing or polishing head, preferably a rotating roller, is provided which is continuously rotating with respect to the substrate, with the head in contact with the metal surface on the substrate. A chemical etchant, essentially free of abrasive material, is continuously supplied to the interface between the metal surface and the head. The treating and polishing continues until the defects have been removed or reduced to an acceptable value. In some instances where significant height reduction is required, thus requiring significant metal removal, several passes of the substrate may be required or a device with multiple heads may be used.Type: GrantFiled: November 19, 1996Date of Patent: April 13, 1999Assignee: International Business Machines CorporationInventors: John Joseph Konrad, Voya Rista Markovich, George Frederick Reel, Jose Antonio Rios, Timothy Leroy Wells, Michael Wozniak
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Patent number: 5863838Abstract: A method of manufacturing a semiconductor device includes providing (51) a substrate (19), providing (52) a colloid (17) having particles held in suspension, providing (53) a reagent (18), disposing (54) the substrate (19) in a processing tool (10), combining (55) the colloid (17) and the reagent (18) to form a slurry (28), decomposing (56) the reagent (18) into a surfactant and an oxidizer, using (57) the slurry (28) to process the substrate (19) in the processing tool (10), and removing (58) the substrate (19) from the processing tool (10).Type: GrantFiled: July 22, 1996Date of Patent: January 26, 1999Assignee: Motorola, Inc.Inventors: Janos Farkas, Melissa Freeman
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Patent number: 5840629Abstract: There is described a slurry for use in chemical mechanical polishing of copper layers in integrated circuit fabrication. The slurry includes a chromate oxidant, such as sodium chromate tetrahydrate (Na.sub.2 CrO.sub.4.4H.sub.2 O). The chromate oxidant provides a slightly basic slurry solution that enhances removal characteristics for copper layers. In one embodiment, the slurry has a pH between about 6 and about 9.Type: GrantFiled: December 14, 1995Date of Patent: November 24, 1998Assignee: Sematech, Inc.Inventor: Ronald A. Carpio
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Patent number: 5792375Abstract: Two copper containing surfaces are bonded together by microetching at least one of the surfaces, followed by abutting the two surfaces together, and then laminating them at a temperature of at least about 300.degree. C. and below the decomposition temperature of the copper-containing surfaces, and at a pressure of at least about 1500 psi.Type: GrantFiled: February 28, 1997Date of Patent: August 11, 1998Assignee: International Business Machines CorporationInventor: Donald Seton Farquhar
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Patent number: 5770095Abstract: The present invention provides a polishing method including the steps of forming a film made of material containing a metal as a main component over a substrate having depressed portions on a surface thereof so as to fill the depressed portions with the film, and polishing the film by a chemical mechanical polishing method using a polishing agent containing a chemical agent responsible for forming a protection film on a surface of the film by reacting with the material containing a metal as a main component, thereby forming a conductive film in the depressed portions.Type: GrantFiled: July 11, 1995Date of Patent: June 23, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Yasutaka Sasaki, Nobuo Hayasaka, Hisashi Kaneko, Hideaki Hirabayashi, Masatoshi Higuchi
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Patent number: 5766499Abstract: A method of making a circuitized substrate wherein a dielectric layer is provided having a first layer of metallic material thereon. A first metallic member is formed on the dielectric's metallic layer, following which a pair of openings are precisely provided within a second dielectric material located on the dielectric. These openings in turn define a selected area on the first metallic member and, significantly, a precisely oriented pattern of the first metallic layer at a spaced distance from the metallic member. This metallic pattern serves as a mask to permit formation of an opening through the dielectric, which opening in turn may be engaged by tooling or the like such as may be used to position an electronic component, e.g., semiconductor device, on the underlying substrate.Type: GrantFiled: April 26, 1996Date of Patent: June 16, 1998Assignee: International Business Machines CorporationInventors: Kim Joseph Blackwell, Daniel Peter Labzentis, Jonathan David Reid
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Patent number: 5766492Abstract: A method of metal-plating electrode portions of a printed-wiring board includes copper-plating the overall surface of the printed-wiring board on which an electric circuit has been formed, forming a metal plating resist coating on the copper plated wiring board except for on the electrode portions, and subjecting the electrode portions, which are not covered with the resist coating, to an electrolytic metal plating process, at least once, and then removing the remaining resist coating. The resist coating formation and the electrolytic metal plating process may optionally be repeated a predetermined number of times. An etching resist coating is then formed on the circuit portion including the electrode portions, and the copper-plated portion is then removed except from the circuit portion by etching and then stripping the etching resist coating.Type: GrantFiled: May 28, 1996Date of Patent: June 16, 1998Assignees: Nippon Paint Co., Ltd., International Business Machines CorporationInventors: Toshiya Sadahisa, Johji Nakamoto, Kanji Nishijima, Yoshinobu Kurosaki
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Patent number: 5759427Abstract: A technique for chemically planarizing an exposed surface of metal on a substrate to a pre-determined thickness is provided. The substrate has an exposed metal surface such as copper circuitry on a dielectric substrate which is to be planarized. Typically, this will be circuitization extending above a photoresist layer. A planarizing head is rotated against the substrate, with the planarizing head in contact with the metal surface on the substrate. A chemical etchant, essentially free of abrasive material, is continuously supplied to the interface between the metal surface and the planarizing head. The planarizing continues until a predetermined thickness of the metal has been reached. In circuit board manufacturing, this will form a surface co-planar with the photoresist. In some instances where significant height reduction is required, thus requiring significant metal removal, several passes of the substrate may be required or a device with multiple heads may be used.Type: GrantFiled: August 28, 1996Date of Patent: June 2, 1998Assignee: International Business Machines CorporationInventors: Edward Cibulsky, Gerald Andrew Kiballa, Voya Rista Markovich, Gary Leigh Newman, John Francis Prikazsky, Michael Wozniak
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Patent number: 5733468Abstract: A pattern plating method for fabricating printed circuit boards begins by bonding a thin layer of copper (e.g., copper foil) to the surface of the board. A photoresist layer is laminated over the copper layer, and then selectively exposed and developed to define a desired pattern of traces. A thick, second layer of copper is deposited on the traces by electrolytic deposition, and the photoresist is then removed. The board is etched with a solution containing cupric chloride (or an ammoniacal etchant) to remove those portions of the first copper layer that are not covered by the second copper layer. The present invention also allows through-holes to be drilled at selected locations after the first layer of copper foil has been bonded to the board. A thin layer of copper is then deposited by electroless deposition to create a conductive surface in the through-holes necessary for the subsequent step of electrolytic deposition in the process above.Type: GrantFiled: August 27, 1996Date of Patent: March 31, 1998Inventor: John W. Conway, Jr.
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Patent number: 5705219Abstract: A method for coating surfaces of a non-conductor with finely particulate solid particles by substrate-induced coagulation, including the steps of: contacting the non-conductor with a first solution containing a first polar solvent and at least one coagulation initiator comprising high molecular weight material; and, subsequently contacting the non-conductor with a dispersion which contains a second polar solvent and: a) finely particulate solid particles, b) at least one surfactant for preventing the sedimentation of the solid particles, and c) a salt, essentially free of tin ions, for selectively destabilizing the dispersion.Type: GrantFiled: March 14, 1996Date of Patent: January 6, 1998Assignee: Atotech Deutschland GmbHInventors: Jurgen-Otto Besenhard, Olaf Claussen, Hans-Peter Gausmann, Heinrich Meyer, Hartmut Mahlkow
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Patent number: 5700389Abstract: An etching solution for copper or copper alloys comprising, (a) sulfuric acid, (b) a persulfate, (c) at least one compound selected from imidazole, imidazole derivatives, pyridine derivatives, triazine, and triazine derivatives, and (d) water. The etching solution exhibits a high etching speed and does not oxidize the copper surfaces after etching.Type: GrantFiled: August 2, 1995Date of Patent: December 23, 1997Assignee: MEC Co., Ltd.Inventor: Toshiko Nakagawa
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Patent number: 5693364Abstract: The present invention relates to a process for the manufacture of printed circuit boards. The method contemplates a novel processing sequence for this manufacturing process which method is particularly versatile in reducing the number of steps and variety of chemicals currently necessary to produce the circuit boards.Type: GrantFiled: October 30, 1996Date of Patent: December 2, 1997Assignee: Mac Dermid, IncorporatedInventor: Peter Kukanskis
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Patent number: 5693239Abstract: An aqueous slurry is provided for polishing or planarizing a work piece which contains a metal, the solids portion of said slurry being comprised of 1 to 50 percent by weight of submicron alpha-alumina, the remainder of the solids being of a substantially less abrasive composition chosen from the group consisting of aluminum hydroxides, gamma-alumina, delta-alumina, amorphous alumina, and amorphous silica. Also provided is a method for polishing the surface of a work piece which contains a metal wherein said aqueous slurry is used as the polishing composition during chemical-mechanical polishing.Type: GrantFiled: October 10, 1995Date of Patent: December 2, 1997Assignee: Rodel, Inc.Inventors: Jiun-Fang Wang, Anantha Sethuraman, Huey-Ming Wang, Lee Melbourne Cook
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Patent number: 5653891Abstract: A method of producing a semiconductor device with a convex heat sink that disposes a semiconductor element within a space formed by leads of a lead frame. Bonding pads of the semiconductor element are connected to the leads through wires. The convex heat sink is made from a high heat-conductive material and formed so as to have an outer periphery of a size sufficiently large to overlap the leads. The semiconductor element is disposed at a center portion of the heat sink. An insulator is disposed on the leads. The insulator bonds and fixes the semiconductor element to the heat sink. Resin seals the semiconductor device except for a part of the leads and a top surface of a projecting portion of the heat sink. The insulator has a shape like a tape so as to cover part of the leads and extend along a bottom surface near a circumferential edge of the convex heat sink. The side surface of the projecting portion of the heat sink is scraped out into a curved surface.Type: GrantFiled: May 9, 1995Date of Patent: August 5, 1997Assignee: Seiko Epson CorporationInventors: Tetsuya Otsuki, Norikata Hama
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Patent number: 5635084Abstract: A method for treating the surface of aluminum alloys hang a relatively high copper content is provided which includes the steps of removing substantially all of the copper from the surface, contacting the surface with a first solution containing cerium, electrically charging the surface while contacting the surface in an aqueous molybdate solution, and contacting the surface with a second solution containing cerium. The copper is substantially removed from the surface in the first step either by (i) contacting the surface with an acidic chromate solution or by (ii) contacting the surface with an acidic nitrate solution while subjecting the surface to an electric potential. The corrosion-resistant surface resulting from the invention is excellent, consistent and uniform throughout the surface. Surfaces treated by the invention may often be certified for use in salt-water services.Type: GrantFiled: May 22, 1995Date of Patent: June 3, 1997Assignee: University of Southern CaliforniaInventors: Florian B. Mansfeld, You Wang, Simon H. Lin
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Patent number: 5630950Abstract: A process and aqueous bath for bright dipping of a copper containing substrate. The bath includes: an acid, hydrogen peroxide and a bath soluble, peroxide stable constituent effective for creation and stabilization of a dissolution inhibiting film over the brightened substrate.Type: GrantFiled: October 11, 1994Date of Patent: May 20, 1997Assignee: Enthone-OMI, Inc.Inventor: Anthony R. Cangelosi
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Patent number: 5601658Abstract: A method for treating bronze or brass fixtures containing lead with a cupric acetate solution is described. The treatment results in decreased amounts of lead in subsequent use. A preferred embodiment uses about 0.01 M cupric acetate at pH4.Type: GrantFiled: June 30, 1995Date of Patent: February 11, 1997Assignee: Purdue Research FoundationInventors: Benito J. Marinas, Connie Bogard, Yi Jiang, Hsin-Ting Lan
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Patent number: 5591302Abstract: A process for dry etching a copper containing film formed on a substrate is performed by using an etching gas while heating at a temperature below 200.degree. C. The etching gas is selectable from the group consisting of a mixed gas of a N containing gas, an O containing gas, a N and O containing gas, or a mixed gas of a N containing gas, an O containing gas and a F containing gas, or a mixed gas of a N and O containing gas and a F containing gas. By this etching gas, Cu(NO.sub.3).sub.2 is formed to be sublimed.Type: GrantFiled: July 25, 1995Date of Patent: January 7, 1997Assignee: Sony CorporationInventors: Keiji Shinohara, Junichi Sato, Yukihiro Kamide, Toshiharu Yanagida
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Patent number: 5591480Abstract: One method for fabricating solderable pads (406) onto a substrate (220) for direct chip attachment uses a multilayer metallization coating (500). The coating has a bottom layer (202) of indium-tin oxide, with an intermediate layer (204) of copper and a top layer (206) of indium-tin oxide. A masking layer (208) is deposited on the active display area (402) of the substrate, leaving the bonding pads uncovered. The revealed bonding pads are then plasma etched, using the polyimide as an etch resist, and the top layer of ITO is selectively removed to reveal the underlying copper layer. The exposed copper layer (204) is then plated with a solderable metal to the desired thickness to form bonding pads that may be used with direct chip attachment schemes.Type: GrantFiled: August 21, 1995Date of Patent: January 7, 1997Assignee: Motorola, Inc.Inventors: Douglas H. Weisman, Thomas J. Swirbel, John K. Arledge
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Patent number: 5560838Abstract: Cupric chloride etchant waste is converted into non-hazardous material consisting of copper oxide and salt water. The cupric chloride etchant is preheated and a stream of the etchant is combined with a stream of preheated caustic solution. A neutralization reaction occurs in the mixed stream which is directed to a mixing tank. The reaction completes in the mixing tank without addition of heat, producing fine copper oxide which is filtered out from the salt water. The entire apparatus for carrying out the process can be integrated into a single portable unit.Type: GrantFiled: December 5, 1994Date of Patent: October 1, 1996Assignee: Training `N` Technology, Inc.Inventors: Victoria R. Allies, Mark F. Lloyd, James M. McCarron
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Patent number: 5556553Abstract: A process for control of recycle of ammoniacal copper etchant which uses metallic aluminum to remove copper without substantially adding undesirable byproducts, by controlling the temperature and mixture rate of the removal process. The very rapid reaction can be controlled by using a diluent of copper-free etchant, heating to process temperature, then adding spent, copper containing etchant at a controlled rate while actively cooling the system to control the temperature. The copper concentration can be monitored by colorimetry while maintaining the pH above pH 8. The separated metallic copper and aluminum hydroxide sludge are easily filtered from the etchant. The purified etchant is now suitable for chemical adjustment and reuse.Type: GrantFiled: May 23, 1995Date of Patent: September 17, 1996Assignee: Applied Electroless Concepts, Inc.Inventors: Gerald A. Krulik, Nenad V. Mandich, Rajwant Singh
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Patent number: 5544773Abstract: Provided is a method for making a multilayer printed circuit board having blind holes which comprises heat laminating a copper foil and an inner layer panel previously provided with circuit patterns on one or both sides thereof by processing a copper-clad laminate, a resin layer soluble in an aqueous alkali solution and having a flowability upon heating being present between said copper foil and said inner layer panel, forming via holes in the surface copper foil by etching and then dissolving the resin layer under said via holes with an aqueous alkali solution and removing the resin layer, thereby to form blind holes in which the copper foil on the inner layer panel is exposed. Further provided is a copper foil used for making multilayer printed circuit boards, which is provided with a resin layer soluble in an aqueous alkali solution and having flowability upon heating on its roughened surface.Type: GrantFiled: June 2, 1994Date of Patent: August 13, 1996Inventors: Youichi Haruta, Tomio Kambayashi, Hitoshi Kato, Hiromu Taguchi
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Patent number: 5531018Abstract: An insulating layer with at least one via is provided over a metal plate. A sacrificial layer is applied over a portion of the insulating layer so that the sacrificial layer extends into the via. A metal bridge having at least one opening is provided over a portion of the sacrificial layer and a portion of the insulating layer so that the metal bridge extends over the via and the opening is situated adjacent a portion of the sacrificial layer. A reinforcing seal layer with a well is provided over the metal bridge so that the well is situated adjacent to at least a portion of the opening. The sacrificial layer is then removed.Type: GrantFiled: December 20, 1993Date of Patent: July 2, 1996Assignee: General Electric CompanyInventors: Richard J. Saia, Mario Ghezzo, Bharat S. K. Bagepalli, Kevin M. Durocher
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Patent number: 5527766Abstract: Novel structures and methods utilize layered copper oxide release materials to separate oxide films from growth substrates. Generally, the method comprises the steps of: first, forming a layered copper oxide sacrificial release material on a growth substrate, in the preferred embodiment being the high temperature superconductor YBCO grown on a compatible substrate such as LaAlO3, second, forming an oxide film on the layered copper oxide release material, in the preferred embodiment, a ferroelectric, an optical material or a oxide film compatible with further high temperature superconductor growth, such as SrTiO3 or CeO2, and third, etching the layered copper oxide release material so as to separate the oxide film from the growth substrate. Optionally, additional layers may be grown on the oxide film prior to etching.Type: GrantFiled: December 13, 1993Date of Patent: June 18, 1996Assignee: Superconductor Technologies, Inc.Inventor: Michael M. Eddy
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Patent number: 5503286Abstract: A process for an improved solder terminal is disclosed. The improved solder terminal is made of a bottom metallic adhesion layer, a CrCu intermediate layer on top of the adhesion layer, a solder bonding layer above the CrCu layer and a solder top layer. The adhesion layer is either TiW or TiN. A process for fabricating an improved terminal metal consists of depositing an adhesive metallic layer, a layer of CrCu over the adhesive layer and a layer of solder bonding material, over which a solder layer is formed in selective regions and the underlying layers are etched using solder regions as a mask.Type: GrantFiled: June 28, 1994Date of Patent: April 2, 1996Assignee: International Business Machines CorporationInventors: Henry A. Nye, III, Jeffrey F. Roeder, Ho-Ming Tong, Paul A. Totta
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Patent number: 5492235Abstract: A method for removing Ball Limiting Metallurgy (BLM) layers from the surface of a wafer in the presence of Pb/Sn solder bumps. In one embodiment, the BLM comprises two layers: titanium and copper. After Pb/Sn solder bumps have been formed over the electrical contact pads of the wafer, the BLM copper layer is etched with a H.sub.2 SO.sub.4 +H.sub.2 O.sub.2 +H.sub.2 O solution. While removing the copper layer, the H.sub.2 SO.sub.4 +H.sub.2 O.sub.2 +H.sub.2 O etchant also reacts with the Pb/Sn solder bumps to form a thin PbO protective layer over the surface of the bumps. When the copper layer has been etched away, the titanium layer is etched with a CH.sub.3 COOH+NH.sub.4 F+H.sub.2 O solution. The PbO layer formed over the surface of the Pb/Sn solder bumps remain insoluble when exposed to the CH.sub.3 COOH+NH.sub.4 F+H.sub.2 O etchant, thereby preventing the solder bumps from being etched in the presence of the CH.sub.3 COOH+NH.sub.4 F+H.sub.2 O etchant.Type: GrantFiled: December 1, 1994Date of Patent: February 20, 1996Assignee: Intel CorporationInventors: Douglas E. Crafts, Venkatesan Murali, Caroline S. Lee
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Patent number: 5474798Abstract: The present invention relates to a process for the manufacture of printed circuit boards. The method contemplates the use of electroless nickel as the primary medium for interconnection, for building circuitry to the desired thickness and as an etch resist. The method is particularly versatile in reducing the number of steps and variety of chemicals currently necessary to produce these circuit boards.Type: GrantFiled: August 26, 1994Date of Patent: December 12, 1995Assignee: MacDermid, IncorporatedInventors: Gary B. Larson, Donna Kologe, Cynthia Retallick, Jon Bengston
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Patent number: 5468409Abstract: Multicurved copper films having fine-line elements suitable for radome applications can be improved by cutting the elements with reproducible precision to close tolerance (typically line widths of 3-10.+-.0.25 mil) using an etchant comprising a concentrated saline solution of CuCl.sub.2.Type: GrantFiled: November 3, 1993Date of Patent: November 21, 1995Assignee: The Boeing CompanyInventor: Dennis L. Dull
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Patent number: 5468345Abstract: A method of making printed circuit boards in a continuous process. The method uses copper base metal sputtered onto a substrate. This base metal is much thinner than the base metal normally used in printed circuit processes and ultimately allows a greater number of conductors per unit of length to be made on the boards.Type: GrantFiled: May 4, 1994Date of Patent: November 21, 1995Inventors: Ronald K. Kirby, James W. Watson
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Patent number: 5433819Abstract: A method of making circuit boards is disclosed that is suitable for use in a high-volume automated processing plant. The method can be used to produce either single-sided or double-sided circuit boards with access windows allowing electrical access and connection between traces from both sides. In the process, access holes are punched in a coverfilm. A copper sheet having a tin plating on one side is laminated to the coverfilm, with the tin side facing the coverfilm. A pattern representing a circuit is screened on the resulting laminate with a UV-curable resist, developed in a UV dryer, and then the unprotected copper is etched away. The remaining tin is then removed with solder stripping agent, and the resulting circuit is protected with a coverfilm. The process can be applied to large rolls of materials in an automated process, with large numbers of circuits applied to the laminated board. The circuits can then be punched out of the web with a hydraulic press in large numbers.Type: GrantFiled: May 26, 1993Date of Patent: July 18, 1995Assignee: Pressac, Inc.Inventor: Mark T. McMeen
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Patent number: 5431776Abstract: Copper etchant solution additives for use with an aqueous alkaline ammoniacal cupric chloride etching bath include several compounds, each of which is shown to stabilize the copper(I) state. The compounds discovered by the present invention include iodide ions such as potassium iodide, ammonium iodide, sodium iodide, calcium iodide and magnesium iodide. Other copper(I) stabilizers discovered by the present invention include certain water soluble salts containing sulfur such as a thiocyanate ion (e.g. ammonium thiocyanate, potassium thiocyanate, sodium thiocyanate, magnesium thiocyanate, and calcium thiocyanate) and a thiosulfate ion (e.g. ammonium thiosulfate, potassium thiosulfate, sodium thiosulfate, magnesium thiosulfate, and calcium thiosulfate). Etching rates for alkaline ammoniacal cupric chloride with different concentrations of potassium iodide, ammonium thiocyanate, and sodium thiosulfate were studied.Type: GrantFiled: September 8, 1993Date of Patent: July 11, 1995Assignee: Phibro-Tech, Inc.Inventors: Hugh W. Richardson, Charles F. Jordan