Forming Or Treating Resistive Material Patents (Class 216/16)
  • Patent number: 11324125
    Abstract: A diversified assembly printed circuit board includes a first printed circuit board provided with a multiple first conductive metals protruding from a surface of the first printed circuit board, and a multiple second printed circuit boards each provided with a multiple second conductive metals protruding from a surface of the each of the second printed circuit boards. At a connection position, solidified conductive metal paste is arranged between each of the first conductive metals and a corresponding second conductive metal to electrically connect each of the first conductive metals and the corresponding second conductive metal. A laminated adhesive sheet is arranged between each of the second printed circuit boards and the first printed circuit board to physically connect the second printed circuit boards and the first printed circuit board.
    Type: Grant
    Filed: November 29, 2020
    Date of Patent: May 3, 2022
    Assignee: SHENNAN CIRCUITS CO., LTD.
    Inventors: Ke Leng, Hailong Liu, Jinfeng Liu, Fengwu Wu, Li Chen, Lihua Zhang
  • Patent number: 11287740
    Abstract: A photoresist composition includes a photoresist material including metal oxide nanoparticles and a ligand, and an acid having an acid dissociation constant, pKa, of ?15<pKa<4, or a base having a pKa of 40>pKa>9.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: March 29, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: An-Ren Zi, Chin-Hsiang Lin, Ching-Yu Chang
  • Patent number: 11169103
    Abstract: A thermal gas sensor for measuring the thermal diffusivity and/or the thermal conductivity of a gas or gas mixture includes a substrate. In the surface of the substrate a trench is formed, as well as at least two conductor structures arranged at a distance from one another on the surface of the substrate. The conductor structures respectively each contain at least two contact sections and a web section connected to the contact sections, the web sections of the conductor structures crossing over the trench at a distance from one another. At least one slot is formed between at least two contact sections of different conductor structures in at least one region of the surface of the substrate.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: November 9, 2021
    Assignee: Diehl Metering GmbH
    Inventors: Ulf Hammerschmidt, Andreas Benkert, Christoph Sosna, Karl Herrmann
  • Patent number: 11084727
    Abstract: An ultra dense and ultra low power microhotplates using silica aerogel and method of making the same, comprising creating a sol-gel by impregnation of ethanol with functional colloidal alcogel particles is described. The technique further comprises forming tiny aerogel particles on the wafer and networking the particles together just by exposure to air during spin coating. The novelty of this technique is not limited to the processing of thin film and thick film silica aerogel.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: August 10, 2021
    Assignee: University of Louisiana at Lafayette
    Inventors: Mohammad Reza Madani, Seyedmohammad Seyedjalaliaghdam
  • Patent number: 10917967
    Abstract: A printed wiring board includes an insulator having a first surface, and a second surface opposite to the first surface, a through-hole penetrating from the first surface to the second surface, and a metal plated layer formed on the first and second surfaces of the insulator, and on an inner peripheral surface of the through-hole, wherein an inside diameter of the through-hole gradually decreases from the first surface toward the second surface of the insulator. An average diameter of the through-hole is 20 ?m or greater and 35 ?m or less at the first surface, and is 3 ?m or greater and 15 ?m or less at the second surface, and an average thickness of the metal plated layer formed on the first and second surfaces is 8 ?m or greater and 12 ?m or less.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: February 9, 2021
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Kenji Takahashi, Eiko Imazaki, Koji Nitta, Shoichiro Sakai, Kousuke Miura, Masahiro Matsumoto, Hirohisa Saito
  • Patent number: 10821729
    Abstract: In an embodiment, a fluid flow structure includes a micro device embedded in a molding, a fluid feed hole formed through the micro device, and a transfer molded fluid channel in the molding that fluidically couples the fluid feed hole with the channel.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: November 3, 2020
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Chien-Hua Chen, Michael W. Cumbie
  • Patent number: 10770537
    Abstract: Resistor elements and methods of forming the resistor elements generally include increasing resistivity by diffusing nitrogen ions from an underlying dielectric layer into a metal resistor layer defining the resistor elements. One or more embodiments include a first resistor element and at least one additional resistor element disposed on a first dielectric material and at least one additional dielectric material, respectively, of a dielectric layer. The first dielectric material is different from the at least one additional dielectric material, and the first resistor element has a different resistivity than the at least one additional resistor element.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: September 8, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Chih-Chao Yang
  • Patent number: 10347404
    Abstract: A resistor element includes a base substrate having first and second surfaces opposing each other and first and second end surfaces opposing each other and connecting the first and second surfaces. A first resistor layer is on the first surface of the base substrate. First and second terminals are respectively on the first and second end surfaces. A second resistor layer is on the first resistor layer, is connected to the first and second terminals, and includes a copper-manganese-tin (Cu—Mn—Sn)-based composition.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: July 9, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Kwang Hyun Park, Jang Seok Yun, Kyung Seon Baek
  • Patent number: 10322584
    Abstract: A method for manufacturing a liquid ejection head including the steps of preparing a substrate including, on a surface of the substrate, a layer having a plurality of openings in which opening portions of supply portions are located and which are arrayed in an array direction and another opening which is different from the plurality of openings and is located beyond the array end portion in the array direction, and attaching a dry film for forming flow passages to the substrate and the layer.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: June 18, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventors: Jun Yamamuro, Kenji Fujii, Kazuhiro Asai, Keiji Matsumoto, Koji Sasaki, Kunihito Uohashi, Seiichiro Yaginuma, Masahisa Watanabe, Ryotaro Murakami, Tomohiko Nakano, Keiji Edamatsu, Haruka Nakada
  • Patent number: 10277775
    Abstract: A method for compensating tone value fluctuation in inkjet printing includes generating multi-bit halftone images of pixels on a computer during prepress screening for color separations with multiple tone values out of print image data, forwarding multi-bit halftone images to a control unit of an inkjet printing machine, and printing the multi-bit halftone on the machine, wherein encoded binary values of multi-bit halftone images correspond to ink drop sizes to be generated by the machine. The computer introduces additional binary values of multi-bit halftone images not corresponding to ink drop sizes in pixel positions of multi-bit halftone images where occurring tone value fluctuations are to be compensated for by modified ink drop sizes, causing additional binary values to be ignored by the machine in a regular print mode, and assigning additional binary values to modified ink drop sizes in a correction print mode.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: April 30, 2019
    Assignee: Heidelberger Druckmaschinen AG
    Inventors: Dirk Kirchhoff, Bernd Stritzel, Michael Kaiser
  • Patent number: 10201069
    Abstract: A high frequency power supply device and power supplying method are disclosed, which can rapidly and accurately control power used for generation of plasmas. The device includes a first high frequency power supply, providing power at frequency f1, and a second high frequency power supply providing power at frequency f2 (f1>f2). The first power supply includes: a first high frequency oscillator, which excites the high frequency power at the first frequency and has a variable frequency; a first power amplification block, which amplifies the power of the high frequency oscillator; a heterodyne detection block, which performs heterodyne detection of a reflected wave; and a first control block, which receives a signal after detection of the heterodyne detection block and a traveling wave signal, and controls an oscillating frequency of the first high frequency oscillating block and an output of the first power amplification block.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: February 5, 2019
    Assignees: PEARL KOGYO CO., LTD., ADVANCED MICRO-FABRICATION EQUIPMENT INC, SHANGHAI
    Inventors: Eiich Hayano, Takeshi Nakamura, Yasunori Maekawa, Hiroshi Iizuka, Jinyuan Chen
  • Patent number: 9859286
    Abstract: A method of fabricating an SRAM semiconductor device includes forming first and second FinFETs on an upper surface of a bulk substrate. The first FinFET includes a first source/drain region containing first dopants, and the second FinFET includes a second source/drain region containing second dopants. The method further includes selectively controlling a temperature of the second FinFET with respect to a temperature of the first FinFET during an anneal process to activate the first and second dopants such that the second source/drain region is formed having a different electrical resistance with respect to the first source/drain region.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: January 2, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Dechao Guo, Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 9831301
    Abstract: Resistor elements and methods of forming the resistor elements generally include increasing resistivity by diffusing nitrogen ions from an underlying dielectric layer into a metal resistor layer defining the resistor elements. One or more embodiments include a first resistor element and at least one additional resistor element disposed on a first dielectric material and at least one additional dielectric material, respectively, of a dielectric layer. The first dielectric material is different from the at least one additional dielectric material, and the first resistor element has a different resistivity than the at least one additional resistor element.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: November 28, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Chih-Chao Yang
  • Patent number: 9824799
    Abstract: A measuring resistor for high-current measurements is provided, which has a defined resistance value. The measuring resistor has a resistive layer having a sheet resistivity. The resistance value of the measuring resistor is defined by the resistive layer and is less than the sheet resistivity of the resistive layer.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: November 21, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Severin Kampl, Uwe Kirchner
  • Patent number: 9799490
    Abstract: A cold trap is provided to reduce contamination gases that react with the beam during operations that use a process gas. The cold trap is set to a temperature that condenses the contamination gas but does not condense the process gas. Cold traps may be used in the sample chamber and in the gas line.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: October 24, 2017
    Assignee: FEI Company
    Inventors: Aiden Martin, Geoff McCredie, Milos Toth
  • Patent number: 9793127
    Abstract: One or more plasma etching techniques are provided. Selective plasma etching is achieved by introducing a gas into a chamber containing a photoresist over a substrate, establishing a bias at a frequency to convert the gas to a plasma at the frequency, and using the plasma to etch the photoresist. The frequency controls an electron density of the plasma and by maintaining a low electron density causes free radicals of the plasma to chemically etch the photoresist, rather than physically etching using ion bombardment. A mechanism is thus provided for chemically etching a photoresist under what are typically physical etching conditions.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: October 17, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu Chao Lin, Chao-Cheng Chen
  • Patent number: 9776407
    Abstract: In an embodiment, a fluid ejection device includes a substrate with a fluid slot formed therein, a chamber layer formed on the substrate defining fluid chambers on both sides of the fluid slot, a thin-film layer between the substrate and chamber layer that defines an ink feedhole (IFH) between the fluid slot and the chamber layer, and a chamber layer extension that forms a bridge across the IFH between two chambers.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: October 3, 2017
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Rio Rivas, Anthony M. Fuller, Ed Friesen
  • Patent number: 9748023
    Abstract: Disclosed is a method for manufacturing a substrate gap supporter. The method includes: a first step of forming metal foils on both sides of an insulating plate; a second step of etching the metal foils to expose the insulating plate so that a plurality of stripes are arranged on both sides of the insulating plate in parallel at constant intervals, wherein the stripes expose the insulating plate at constant widths; and a third step of cutting in direction in parallel with the stripes and in direction in vertical with the stripes along one edges of the stripes to complete the gap supporter.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: August 29, 2017
    Assignee: GNE TECH CO., LTD.
    Inventor: Jae Ku Kim
  • Patent number: 9502254
    Abstract: New photoresists are provided that comprise preferably as distinct components: a resin, a photoactive component and a phenolic component Preferred photoresists of the invention are can be useful for ion implant lithography protocols.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: November 22, 2016
    Assignee: Rohm and Haas Electronic Materials LLC
    Inventor: Gerhard Pohlers
  • Patent number: 9462830
    Abstract: An electronic cigarette includes a storage tank filled with extractant and an atomization device. The electronic cigarette further comprises a device for heating tobacco, which includes a heating mechanism and a heated chamber for loading cigarette or tobacco. The heating mechanism comprises a heating element and a heater circuit for controlling the heating element to be heated to a set temperature range. An inlet of the heated chamber is connected to an outlet of the atomization device, and its outlet is connected with an opening for a suction nozzle. When the electronic cigarette is working, the extractant is atomized by the atomization device and then guided into the heated chamber. The heat produced by the heating element is applied to the cigarette or tobacco in the heated chamber to generate nicotine. The nicotine and atomized extractant are mixed together and then sucked out through the opening for the suction nozzle.
    Type: Grant
    Filed: July 12, 2011
    Date of Patent: October 11, 2016
    Assignee: HUIZHOU KIMREE TECHNOLOGY CO., LTD.
    Inventor: Qiuming Liu
  • Patent number: 9368329
    Abstract: A synchronized pulsing arrangement for providing at least two synchronized pulsing RF signals to a plasma processing chamber of a plasma processing system is provided. The arrangement includes a first RF generator for providing a first RF signal. The first RF signal is provided to the plasma processing chamber to energize a plasma therein, the first RF signal representing a pulsing RF signal. The arrangement also includes a second RF generator for providing a second RF signal to the plasma processing chamber. The second RF generator has a sensor subsystem for detecting values of at least one parameter associated with the plasma processing chamber that reflects whether the first RF signal is pulsed high or pulsed low and a pulse controlling subsystem for pulsing the second RF signal responsive to the detecting the values of at least one parameter.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: June 14, 2016
    Assignee: Lam Research Corporation
    Inventors: John C. Valcore, Jr., Bradford J. Lyndaker, Harmeet Singh
  • Patent number: 9335218
    Abstract: A digital bolometer architecture provides dynamic control of a simultaneous integration time for all pixels, with a temporal response that is more uniform than conventional bolometers and lacks frame cross-talk from decay tails, and which supports sub-frame measurement for on readout computational imaging. This is accomplished by replacing resistive pixel temperature sensing with continuous optical interferometric measurement and subsequent signal accumulation. Balanced reference sensors allow rejection of temperature differences across the thermal sink. The thermal time constant of the pixels is substantially reduced and the lost SNR is recovered by integration of the measured signals, using a programmable integration time.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: May 10, 2016
    Assignee: Raytheon Company
    Inventor: Darin S. Williams
  • Patent number: 9230914
    Abstract: Approaches for fabricating copper wires in integrated circuits are provided. A method of manufacturing a semiconductor structure includes forming a wire opening in a mask. The method also includes electroplating a conductive material in the wire opening. The method additionally includes forming a cap layer on the conductive material. The method further includes removing the mask. The method still further includes forming spacers on sides of the conductive material. The method additionally includes forming a dielectric film on surfaces of the cap layer and the sidewall spacers.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: January 5, 2016
    Assignee: International Business Machines Corporation
    Inventors: Fen Chen, Jeffrey P. Gambino, Zhong-Xiang He, Trevor A. Thompson, Eric J. White
  • Patent number: 9031684
    Abstract: A method and system for integrated circuit fabrication is disclosed. In an example, the method includes determining a first process parameter of a wafer and a second process parameter of the wafer, the first process parameter and the second process parameter corresponding to different wafer characteristics; determining a variation of a device parameter of the wafer based on the first process parameter and the second process parameter; constructing a model for the device parameter as a function of the first process parameter and the second process parameter based on the determined variation of the device parameter of the wafer; and performing a fabrication process based on the model.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: May 12, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Nai-Han Cheng, Chin-Hsiang Lin, Chi-Ming Yang, Chun-Lin Chang, Chih-Hong Hwang
  • Publication number: 20150102006
    Abstract: Isolation of magnetic layers in the magnetoresistive stack is achieved by passivation of sidewalls of the magnetic layers or deposition of a thin film of non-magnetic dielectric material on the sidewalls prior to subsequent etching steps. Etching the magnetic layers using a non-reactive gas further prevents degradation of the sidewalls.
    Type: Application
    Filed: June 4, 2014
    Publication date: April 16, 2015
    Inventors: Chaitanya Mudivarthi, Sarin A. Deshpande, Sanjeev Aggarwal
  • Publication number: 20150084002
    Abstract: An apparatus, system, and/or method are described to enable optically transparent reconfigurable integrated electrical components, such as antennas and RF circuits to be integrated into an optically transparent host platform, such as glass. In one embodiment, an Ag NW film may be configured as a transparent conductor for antennas and/or as interconnects for passive circuit components, such as capacitors or resistors. Ag NW may also be used as transmission lines and/or interconnect overlays for devices. A graphene film may also be configured as active channel material for making active RF devices, such as amplifiers and switches.
    Type: Application
    Filed: December 4, 2014
    Publication date: March 26, 2015
    Applicant: HRL LABORATORIES LLC
    Inventors: Hyok J. SONG, James H. Schaffner, Jeong-Sun Moon, Kyung-Ah Son
  • Publication number: 20150085448
    Abstract: Provided are a conductive structure including a) a base, b) a conductive pattern provided on at least one side of the base, and c) a darkening layer provided on the upper surface and lower surface of the conductive pattern, provided on at least a part of the side of the conductive pattern, and provided in an area corresponding to the conductive pattern area, and a touch panel including the same and a manufacturing method thereof.
    Type: Application
    Filed: December 4, 2014
    Publication date: March 26, 2015
    Inventors: Ji Young HWANG, Min Choon PARK, Yong Goo SON, Beom Mo KOO
  • Publication number: 20150079666
    Abstract: A system and method of manufacture for the system, comprising a set of heater-sensor dies, each heater-sensor die comprising an assembly including a first insulating layer, a heating region comprising an adhesion material layer coupled to the first insulating layer and a noble material layer, and a second insulating layer coupled to the heating region and to the first insulating layer through a pattern of voids in the heating region, wherein the pattern of voids in heating region defines a coarse pattern associated with a heating element of the heating region and a fine pattern, integrated into the coarse pattern and associated with a sensing element of the heating region; an electronics substrate configured to couple heating elements and sensing elements of the set of heater-sensor dies to a controller; and a set of elastic elements configured to bias each of the set of heater-sensor dies against a detection chamber.
    Type: Application
    Filed: September 16, 2014
    Publication date: March 19, 2015
    Inventors: Sundaresh Brahmasandra, Thomas Haddock, Patrick Duffy, Jeffrey Williams
  • Publication number: 20150077216
    Abstract: A high voltage resistor includes a ceramic substrate having a surface and defining a groove, and a resistive film deposited in the groove such that the resistive film is recessed relative to the surface of the ceramic substrate.
    Type: Application
    Filed: January 4, 2012
    Publication date: March 19, 2015
    Applicant: Schlumberger Technology Corporation
    Inventor: Guillaume Frerejean
  • Publication number: 20150071326
    Abstract: Provided are a temperature sensor that is hard to increase resistance in the electrode structure with respect to a Ti—Al—N thermistor material layer even under a high-temperature environment, and has a high reliability with a high heat resistance as well as a method for producing the same. The temperature sensor includes an insulation substrate; a thin film thermistor portion formed on the insulation substrate; and a pair of pattern electrodes formed on the insulation substrate with a pair of opposed electrode portions being arranged so as to be opposed to each other on the thin film thermistor portion, wherein the thin film thermistor portion is made of a Ti—Al—N thermistor material, and the pair of pattern electrodes has a Ti—N bonding layer formed on the thin film thermistor portion and an electrode layer made of a noble metal formed on the bonding layer.
    Type: Application
    Filed: March 22, 2013
    Publication date: March 12, 2015
    Inventors: Noriaki Nagatomo, Hitoshi Inaba, Hiroshi Tanaka
  • Patent number: 8961853
    Abstract: Disclosed are methods of lithography using a tip array having a plurality of pens attached to a backing layer, where the tips can comprise a metal, metalloid, and/or semi-conducting material, and the backing layer can comprise an elastomeric polymer. The tip array can be used to perform a lithography process in which the tips are coated with an ink (e.g., a patterning composition) that is deposited onto a substrate upon contact of the tip with the substrate surface. The tips can be easily leveled onto a substrate and the leveling can be monitored optically by a change in light reflection of the backing layer and/or near the vicinity of the tips upon contact of the tip to the substrate surface.
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: February 24, 2015
    Assignee: Northwestern University
    Inventors: Chad A. Mirkin, Wooyoung Shim, Adam B. Braunschweig, Xing Liao, Jinan Chai, Jong Kuk Lim, Gengfeng Zheng, Zijian Zheng
  • Patent number: 8939645
    Abstract: A micro drive assembly may comprise a substrate, a micro shaft oriented in-plane with the substrate and at least one micro bearing to support rotation of the micro shaft. The micro shaft and micro bearing may be in or less than the micrometer domain.
    Type: Grant
    Filed: October 8, 2012
    Date of Patent: January 27, 2015
    Assignee: MicroZeus, LLC
    Inventor: Harold L. Stalford
  • Publication number: 20140375931
    Abstract: A display device may include a substrate, a first roof layer formed of a material, a second roof layer formed of the material and spaced from the substrate, and a subpixel electrode disposed between the substrate and the first roof layer. The display device may further include a common electrode member disposed between the subpixel electrode and the first roof layer. The common electrode member may overlap the first roof layer in a first direction without extending beyond the first roof layer in a second direction. The first direction may be perpendicular to a surface of the substrate. The second direction may be parallel to the surface of the substrate. The display device may further include a liquid crystal set disposed between the subpixel electrode and the common electrode member.
    Type: Application
    Filed: January 10, 2014
    Publication date: December 25, 2014
    Applicant: Samsung Display Co., Ltd.
    Inventors: Won Tae KIM, You Young Jin, Kyung Tae CHAE, Don Chan CHO, Seok-Joon HONG
  • Publication number: 20140340791
    Abstract: A current-perpendicular-to-the plane magnetoresistive sensor has top and bottom electrodes narrower than the sensor trackwidth. The electrodes are formed of one of Cu, Au, Ag and AgSn, which have an ion milling etch rate much higher than the etch rates for the sensor's ferromagnetic materials. Ion milling is performed at a high angle relative to a line orthogonal to the plane of the electrode layers and the layers in the sensor stack. Because of the much higher etch rate of the material of the top and bottom electrode layers, the electrode layers will have side edges that are recessed from the side edges of the free layer. This reduces the surface areas for the top and bottom electrodes, which causes the sense current passing through the sensor's free layer to be confined in a narrower channel, which is equivalent to having a sensor with narrower physical trackwidth.
    Type: Application
    Filed: May 16, 2013
    Publication date: November 20, 2014
    Applicant: HGST Netherlands B.V.
    Inventors: Patrick Mesquita Braganca, Jeffrey R. Childress, Jordan Asher Katine, Yang Li, Neil Leslie Robertson, Neil Smith, Petrus Antonius VanDerHeijden, Douglas Johnson Werner
  • Publication number: 20140291283
    Abstract: A method for making a current-perpendicular-to-the-plane magnetoresistive sensor structure produces a top electrode that is “self-aligned” on the top of the sensor and with a width less than the sensor trackwidth. A pair of walls of ion-milling resistant material are fabricated to a predetermined height above the biasing layers at the sensor side edges. A layer of electrode material is then deposited onto the top of the sensor between the two walls. The walls serve as a mask during angled ion milling to remove outer portions of the electrode layer. The height of the walls and the angle of ion milling determines the width of the resulting top electrode. This leaves the reduced-width top electrode located on the sensor. Because of the directional ion milling using walls that are aligned with the sensor side edges, the reduced-width top electrode is self-aligned in the center of the sensor.
    Type: Application
    Filed: March 29, 2013
    Publication date: October 2, 2014
    Applicant: HGST Netherlands B.V.
    Inventors: Patrick Mesquita Braganca, Jeffrey R. Childress, Jordan Asher Katine, Yang Li, Neil Leslie Robertson, Neil Smith, Petrus Antonius VanDerHeijden, Douglas Johnson Werner
  • Publication number: 20140238725
    Abstract: A method of flattening surface of conductive structure including a substrate, a dielectric layer on the substrate, and a conductive line formed in the dielectric layer is provided. A surface of the conductive line has a recess. A cover layer is formed on the substrate. A mechanical polishing process is performed to remove a portion of the cover layer. A remaining cover layer fills and levels the recess.
    Type: Application
    Filed: February 27, 2013
    Publication date: August 28, 2014
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventor: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
  • Publication number: 20140224786
    Abstract: A method and apparatus provide a resistor electrically connected to an electrically conductive trace.
    Type: Application
    Filed: October 14, 2011
    Publication date: August 14, 2014
    Inventors: Galen P. Cook, Bradley D. Chung
  • Patent number: 8790520
    Abstract: A method for manufacturing a Z-directed component for insertion into a mounting hole in a printed circuit board according to one example embodiment includes punching a plurality of segments out of at least one sheet of substrate material to form a plurality of layers of the Z-directed component. A channel is formed through the substrate material either before or after the segments are punched. At least one of the formed layers includes at least a portion of the channel. A conductive material is applied to at least one surface of at least one of the formed layers. A stack of the formed layers is combined to form the Z-directed component.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: July 29, 2014
    Assignee: Lexmark International, Inc.
    Inventors: Paul Kevin Hall, Keith Bryan Hardin, Zachary Charles Nathan Kratzer, Qing Zhang
  • Publication number: 20140182897
    Abstract: A circuit board includes an inorganic material insulating layer, a first circuit pattern layer formed on a surface of the inorganic material insulating layer, a first build-up insulating layer formed on the inorganic material insulating layer and formed of an organic material, and a second circuit pattern layer formed on a surface of the first build-up insulating layer.
    Type: Application
    Filed: December 30, 2013
    Publication date: July 3, 2014
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Doo Hwan LEE, Yul Kyo CHUNG, Yee Na SHIN, Seung Eun LEE
  • Publication number: 20140145751
    Abstract: An electronic device for implementing digital functions comprising a first and a second electrode regions, separated by an interposing region comprising a dielectric region, is described. The first and the second electrode regions comprise at least one first electrode and at least one second electrode, respectively, configured to generate in the interposing region an electric field depending on an electric potential difference applied thereto. In the interposing region, a molecular layer is comprised, which is composed of a plurality of molecules, each being capable of assuming one or more states, in a controllable manner, depending on a sensed electric field. The dielectric region has a spatially variable dielectric profile, to determine a respective spatially variable field profile of the sensed electric field at the molecular layer.
    Type: Application
    Filed: November 25, 2013
    Publication date: May 29, 2014
    Applicant: STMicroelectronics S.r.l.
    Inventor: Alessandro Paolo Bramanti
  • Publication number: 20140124777
    Abstract: A method for manufacturing a build-up substrate, the build-up substrate comprising an insulating layer and a wiring pattern layer stacked over a circuit substrate, said method comprising the steps of: (i) applying a photoactive metal oxide precursor material to one or both sides of the circuit substrate with a wiring pattern, and drying the applied photoactive metal oxide precursor material to form an insulating film; (ii) forming an opening for a via hole in the insulating film by exposure and development of the insulating film; (iii) applying a heat treatment to the insulating film to convert the insulating film into a metal oxide film, thereby forming a build-up insulating layer of the metal oxide film; and (iv) plating the build-up insulating layer to form via holes in the openings, forming a metal layer on the build-up insulating layer, and etching the metal layer to form a build-up wiring pattern; and (v) repeating the steps from (i) to (iv) at least one time.
    Type: Application
    Filed: October 29, 2012
    Publication date: May 8, 2014
    Applicant: Panasonic Corporation
    Inventors: Seiichi Nakatani, Koji Kawakita, Susumu Sawada, Yoshihisa Yamashita
  • Patent number: 8702998
    Abstract: A novel method to manufacture a flexible cable for a disk drive is disclosed. The method includes providing a flexible laminar sheet. The flexible laminar sheet has a dielectric substrate layer and an electrically conductive layer contacting a first side of the dielectric substrate layer. A portion of the electrically conductive layer is etched away to define a first plurality of electrically conductive traces and to expose an etched surface of the first side of the dielectric substrate layer. A second plurality of electrically conductive traces is deposited on the etched surface of the first side of the dielectric substrate layer.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: April 22, 2014
    Assignee: Western Digital Technologies, Inc.
    Inventor: Albert J. Guerini
  • Publication number: 20140102774
    Abstract: An apparatus for conveying an electrical signal includes: a conductive pathway having a conductive material. The conductive material has a first edge and a second edge and is configured to convey the electrical signal. The apparatus also includes a resistive material in contact with at least a portion of the conductive pathway, covering an edge of the conductive pathway, and extending beyond the edge. The resistive material has a conductivity less than the conductivity of the conductive material.
    Type: Application
    Filed: October 15, 2012
    Publication date: April 17, 2014
    Applicant: RAYTHEON COMPANY
    Inventors: Andrew K. Brown, Thomas L. Obert, Michael J. Sotelo, Darin M. Gritters, Kenneth W. Brown
  • Publication number: 20130306359
    Abstract: The present disclosure provides an article having a substrate having opposing first and second surfaces. A conductor micropattern disposed on the first surface of the substrate. The conductor micropattern has a plurality of traces defining a plurality of cells. The conductor micropattern has an open area fraction greater than 80% and a uniform distribution of trace orientation. Each of the traces has a trace width from 0.5 to 10 micrometer. The conductor micropattern is a tri-layer material comprising in sequence a semi-reflective metal, a transparent layer, and a reflective layer disposed on the transparent layer. The articles are useful in devices such as displays, in particular, touch screen displays useful for mobile hand held devices, tablets and computers. They also find use in antennas and for EMI shields.
    Type: Application
    Filed: February 1, 2012
    Publication date: November 21, 2013
    Applicant: 3M INNOVATIVE PROPERTIES COMPANY
    Inventors: Matthew H. Frey, Stephen P. Maki
  • Patent number: 8568600
    Abstract: A method of manufacturing touch screen panels includes forming a photoresist film on a first surface of a substrate having high transmittance, removing the photoresist film in regions between unit cells by utilizing exposing and developing processes, etching the substrate in the regions where the photoresist film has been removed, removing the photoresist film from the substrate after the etching, performing a tempering process on the substrate including the etched regions, forming touch screen panels at the unit cells defined by the etched regions on the first surface of the substrate, and cutting the substrate at the etched regions to separate the touch screen panels.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: October 29, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sung-Ku Kang, Jung-Mok Park
  • Patent number: 8535546
    Abstract: In order to provide a method of manufacturing a multilayer wiring substrate, a base member having a copper foil separably laminated thereon is prepared, and a solder resist layer is formed on the copper foil. Openings are formed in the solder resist layer, and a metal conductor portion is formed in each of the openings. By means of sputtering, a dissimilar metal layer is formed over the surface of the metal conductor portion and the entire surface of the solder resist layer. Copper electroplating is performed so as to form connection terminals and a conductor layer on the dissimilar metal layer. After a build-up step, the base material is removed, whereby the copper foil is exposed, and the exposed copper foil and the metal conductor portion are removed through etching, whereby the surfaces of the external connection terminals are exposed from the openings.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: September 17, 2013
    Assignee: NGK Spark Plug Co., Ltd.
    Inventor: Shinnosuke Maeda
  • Patent number: 8507801
    Abstract: A printed wiring board is formed by adhering a coverlay film having a resistance layer formed on a surface of the coverlay film body to a printed wiring board body having a conductive layer formed on a surface of a substrate through an adhesive layer. The resistance layer is separated from and opposed to the conductive layer through the adhesive layer.
    Type: Grant
    Filed: August 18, 2009
    Date of Patent: August 13, 2013
    Assignee: Shin-Etsu Polymer Co., Ltd.
    Inventors: Toshiyuki Kawaguchi, Kazutoki Tahara, Tsutomu Saga
  • Publication number: 20130175073
    Abstract: Methods for fabricating a back-end-of-line (BEOL) wiring structure, BEOL wiring structures, and design structures for a BEOL wiring structure. The BEOL wiring may be fabricated by forming a first wire in a dielectric layer and annealing the first wire in an oxygen-free atmosphere. After the first wire is annealed, a second wire is formed in vertical alignment with the first wire. A final passivation layer, which is comprised of an organic material such as polyimide, is formed that covers an entirety of a sidewall of the second wire.
    Type: Application
    Filed: January 6, 2012
    Publication date: July 11, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Edward C. Cooney, III, Jeffrey P. Gambino, Zhong-Xiang He, Tom C. Lee, Xiao H. Liu
  • Publication number: 20130133919
    Abstract: A structure and method for fabricating the structure that provides a metal wire having a first height at an upper surface. An insulating material surrounding said metal wire is etched to a second height below said first height of said upper surface. The metal wire from said upper surface, after etching said insulating material, is planarized to remove sufficient material from a lateral edge portion of said metal wire such that a height of said lateral edge portion is equivalent to said second height of said insulating material surrounding said metal wire.
    Type: Application
    Filed: November 28, 2011
    Publication date: May 30, 2013
    Applicant: International Business Machines Corporation
    Inventors: Gregory S. Chrisman, Edward C. Cooney, III, Jeffrey P. Gambino, Zhong-Xiang He, Thomas L. McDevitt, Eva A. Shah
  • Publication number: 20130032568
    Abstract: A process of making an article of manufacture, the process including constructing an electrical device which implements circuitry having a portion in cavities, the portion defined by an epoxy dielectric material delivered with solid content sufficient that etching the epoxy forms cavities located in, and underneath an initial surface of, the dielectric material, sufficient that the etching of the epoxy uses non-homogeneity with the solid content in bringing about formation of the cavities and sufficient that the etching of the epoxy is such that a plurality of the cavities have a cross-sectional width that is greater than a maximum depth with respect to the initial surface, wherein the etching forms the cavities, and a conductive material, a portion of the conductive material in the cavities thereby forming teeth in the cavities, such that the conductive material forms the portion of the circuitry of the electrical device.
    Type: Application
    Filed: October 1, 2012
    Publication date: February 7, 2013
    Inventors: Brian J. McDermott, Daniel McGowan, Ralph Leo Spotts, JR., Sid Tryzbiak