Forming Or Treating Resistive Material Patents (Class 216/16)
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Patent number: 7396711Abstract: Embodiments of the present invention describe a method of forming a multi-cornered film. According to the embodiments of the present invention, a photoresist mask is formed on a hard mask film formed on a film. The hard mask film is then patterned in alignment with the photoresist mask to produce a hard mask. The width of the photoresist mask is then reduced to form a reduced width photoresist mask. A first portion of the film is then etched in alignment with the hard mask. The hard mask is then etched in alignment with the reduced width photoresist mask to form a reduced width hard mask. A second portion of the film is then etched in alignment with the reduced width hard mask.Type: GrantFiled: December 27, 2005Date of Patent: July 8, 2008Assignee: Intel CorporationInventors: Uday Shah, Brian S. Doyle, Justin K. Brask, Robert S. Chau
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Patent number: 7309657Abstract: Provided is a method for manufacturing a circuit board including an electrode wiring formed above a surface portion of a substrate, and a plurality of electrothermal converting elements which have a heating resistor film for generating thermal energy formed above the electrode wiring. The method includes: forming an electrode wiring layer for forming the electrode wiring, forming the heating resistor film; and collectively etching the electrode wiring layer and the heating resistor film to thereby form the electrode wiring. With the method according to the present invention, the circuit board can be manufactured with a higher density, higher endurance, and lower power consumption recording head to provide high resolution images.Type: GrantFiled: August 31, 2004Date of Patent: December 18, 2007Assignee: Canon Kabushiki KaishaInventors: Masato Kamiichi, Keiichi Sasaki
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Patent number: 7282257Abstract: The present invention relates to resin compositions that are useful for preparing adhesive films, which are, in turn, useful for forming interlayer insulation layers for multi-layered printed wiring boards having an excellent mechanical strength and capable of being roughened by an oxidizing agent.Type: GrantFiled: June 25, 2004Date of Patent: October 16, 2007Assignee: Ajinomoto Co., Inc.Inventors: Hiroshi Orikabe, Kenji Kawai
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Patent number: 7278202Abstract: A surface mount resistor includes an elongated piece of resistive material having strips of conductive material attached to its opposite ends. The strips of conductive material are separated to create an exposed central portion of the resistive material therebetween. According to the method the resistive strip is attached to a single co extensive strip of conductive material and a central portion of the conductive material is removed to create the exposed central portion of the resistive strip.Type: GrantFiled: December 23, 2004Date of Patent: October 9, 2007Assignee: Vishay Dale Electronics, Inc.Inventors: Joel J. Smejkal, Steve E. Hendricks
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Patent number: 7268663Abstract: A precision AC input voltage divider of input resistance RI and feedback resistance RF on a substrate is printed as a serpentine pattern for a thin line of resistive material. The input resistance is formed between a first and second terminal, and feedback resistance is formed between the second terminal and a third terminal. A first metallic conductor is formed on the substrate, connected to the first terminal, disposed to be adjacent to the input resistance, and having a distributed capacitive coupling to the input resistance that compensates for corresponding distributed stray capacitance from the input resistance to a circuit ground. A second metallic conductor is formed on the substrate, connected to the third terminal, disposed to be adjacent the feedback resistance, and having a distributed capacitive coupling to the feedback resistance that compensates for corresponding distributed stray capacitance from the feedback resistance to the circuit ground.Type: GrantFiled: October 25, 2005Date of Patent: September 11, 2007Assignee: Agilent Technologies, Inc.Inventors: Sylvia J. Budak, Joe E. Marriott
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Patent number: 7247250Abstract: A fast heat rise resistor comprising a substrate, a foil bridge on the surface of the substrate, the foil bridge having an elevated portion and a contact portion, the elevated portion above the substrate, the contact portion in contact with the substrate, a conductive layer attached to the contact portion of said foil bridge. The activation energy and/or response time is reduced as the foil bridge is suspended over the substrate. Another aspect of the invention include a method of manufacturing the foil bridge and application to autoignition vehicle airbags.Type: GrantFiled: October 13, 2004Date of Patent: July 24, 2007Assignee: Vishay Intertechnology, Inc.Inventors: George V. Gerber, Anthony E. Troianello, Haim Goldberger
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Patent number: 7244370Abstract: In order to provide a circuit substrate with a satisfactory step coverage by the protective layer and the anti-cavitation film in an edge portion of wirings and a liquid discharge head utilizing such circuit substrate, the invention provides a method for producing a circuit substrate provided, on an insulating surface of a substrate, with a plurality of elements each including a resistive layer and a pair of electrodes formed with a predetermined spacing on said resistive layer, including a step of forming an aluminum electrode wiring layer on the resistive layer, a step of isolating the electrode wiring layer by dry etching into each element, and a step of forming the electrode wiring into a tapered cross section with an etching solution containing phosphoric acid, nitric acid and a chelating agent capable of forming a complex with the wiring metal.Type: GrantFiled: August 4, 2004Date of Patent: July 17, 2007Assignee: Canon Kabushiki KaishaInventors: Keiichi Sasaki, Masato Kamiichi, Yukihiro Hayakawa, Ershad Ali Chowdhury
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Patent number: 7223480Abstract: The present invention relates to a metal laminate which is broadly used for a flexible wiring board or the like and an etching method therefor. In particular, the present invention relates to a metal laminate which includes a layer obtained by laminating a metal layer and an insulating layer, where the insulating layer is subjected to an etching process, wherein, in a surface of the metal layer which is positioned so as to come in contact with the insulating layer, respective concentrations of main metal element and oxygen element constituting the metal layer are measured from the surface of the metal layer towards inside of the metal layer in a time-elapsing manner according to AES (Auger electron spectroscopy) and a value of the thickness of a metal oxide film of the surface of the metal layer measured at a time when atomic concentrations of the main metal element and the oxygen element constituting the metal layer become equal to each other is in a range of at least 0 ? to less than 50 ?.Type: GrantFiled: July 28, 2003Date of Patent: May 29, 2007Assignee: Mitsui Chemicals, Inc.Inventors: Koji Hirota, Masanao Kobayashi, Minehiro Mori, Naoki Nakazawa
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Patent number: 7166534Abstract: Semiconductor manufacturing processes that reduce production costs as well as increase throughput by substituting the PR strip and ACT wet cleaning procedure after the via contact etching of a semiconductor with dry cleaning to be performed while removing a photoresist in a conventional PR strip apparatus. In addition, the methods can shorten waiting time and maintain consistency in the process by performing the PR strip and cleaning at the same time in the same chamber. The resultant devices have lower via contact resistance and its deviation, as compared to the conventional PR strip and ACT wet cleaning.Type: GrantFiled: September 24, 2002Date of Patent: January 23, 2007Assignee: Hynix Semiconductor Inc.Inventor: Tae-Woo Jung
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Patent number: 7132056Abstract: A method of fabricating a fluid ejection device includes the step of forming a plurality of micro-electromechanical fluid ejection devices on a substrate that incorporates drive circuitry such that each device includes a micro-electromechanical actuator that is in electrical contact with the drive circuitry and a fluid ejection member that is positioned on the actuator. A plurality of nozzle chamber walls are formed on the substrate to define nozzle chambers such that each fluid ejection member is operatively positioned with respect to a respective nozzle chamber to eject fluid from the nozzle chamber on receipt of an electrical signal from the drive circuitry by the micro-electromechanical actuator to displace the fluid ejection member. A layer of sacrificial material is deposited on the substrate to cover the nozzle chamber walls.Type: GrantFiled: December 8, 2003Date of Patent: November 7, 2006Assignee: Silverbrook Research Pty LtdInventor: Kia Silverbrook
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Patent number: 7112286Abstract: A thin film resistor structure and a method of fabricating a thin film resistor structure is provided. The thin film resistor structure includes an electrical interface layer or head layer that is a combination of a Titanium (Ti) layer and a Titanium Nitride (TiN) layer. The combination of the Ti layer and the TiN layer mitigates resistance associated with the electrical interface layers.Type: GrantFiled: December 4, 2003Date of Patent: September 26, 2006Assignee: Texas Instruments IncorporatedInventors: Brian Vialpando, Eric William Beach, Philipp Steinmann
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Patent number: 7100270Abstract: A method of fabricating printed circuit boards integrating thick film resistor components and thin film circuit portions thereon is disclosed. This is a two-phase process, where the first phase is to create multiple thick film resistors, and the second phase is to create a thin film circuit portion on the substrate with thick film resistors in existence, involving the printing of the electrodes and the resistive coating for the thick film resistors, and the printing of a low temperature passivation layer over the resistors; and the thin film circuit is formed by titanium and copper layers over the substrate, and electroplating of interconnections to form copper plated circuit. The present fabrication process does not require drilling of holes nor electroplating of leads to the resistors, thus the whole process can be automated to a greater extent than with conventional techniques.Type: GrantFiled: September 25, 2003Date of Patent: September 5, 2006Assignee: Tong Hsing Electric Industries Ltd.Inventor: Shao-Pin Ru
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Patent number: 7026254Abstract: A precursor that may be imaged by heat is made up of a substrate, for example a copper board, and a composite layer structure composed of two layers. Preferably, the first layer is composed of an aqueous developable polymer mixture containing a photothermal conversion material, which is contiguous to the substrate. The second layer of the composite is composed of one or more non-aqueous soluble polymers, which are soluble or dispersible in a solvent which does not dissolve the first layer. The precursor is exposed with an infrared laser or a thermal print head, and upon aqueous development, the exposed regions are removed, revealing regions of the substrate surface able to be etched or otherwise treated. The second layer may also contain a photothermal conversion material. Alternatively, the composite layer may be free of photothermal conversion material when thermal imaging is carried out using a thermal print head. The precursor may be used, for example, as a mask precursor or electronic part precursor.Type: GrantFiled: April 2, 2003Date of Patent: April 11, 2006Assignee: Eastman Kodak CompanyInventors: Kevin Barry Ray, Anthony Paul Kitson
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Patent number: 7025893Abstract: A thin film heater includes at least two open regions formed along each of two spaced-apart edges of the thin film material, which edges are parallel to two spaced-apart edges of the underlying substrate. The open regions expose areas of underlying substrate. When electrical power is coupled to the two spaced-apart edges of the thin film material, uniformity of the heat generated across the thin film material is enhanced. The substrate may be planar or curved, and the open regions in the thin film material may be removed from deposited thin film material, or may be formed by preventing deposition of thin film material in such regions.Type: GrantFiled: August 12, 2003Date of Patent: April 11, 2006Assignee: Thermo Stone USA, LLCInventors: Arthur J. Goodsel, Scott A. Cooper, Kerry A. Goodsel
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Patent number: 7025892Abstract: A method is provided for creating gated filament structures for a field emission display. A multi-layer structure is provided that includes a substrate, an insulating layer and a metal gate layer positioned on at least a portion of a top surface of the insulating layer. A plurality of patterned gates are also provided in order to define a plurality of gate apertures on the top surface of the insulating layer. A plurality of spacers are formed in the gate apertures at edges of the patterned gates on the top surface of the insulating layer. The spacers are used as masks for etching the insulating layer and forming a plurality of pores in the insulating layer. The pores are plated with a filament material that extends from the insulating pores, into the gate apertures, and creates a plurality of filaments. The spacers are then removed. The multi-layer structure can further include a conductivity layer on at least a portion of a top surface of the substrate.Type: GrantFiled: January 31, 1995Date of Patent: April 11, 2006Assignee: Candescent Technologies CorporationInventors: David L. Bergeron, John M. Macaulay, Roger W. Barton, Jeffrey D. Morse
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Patent number: 7008547Abstract: Provided is a solid phase array of electrical sensors, each comprising a channel and electrical leads for attaching to a voltage, current or resistivity meter for measuring the voltage, current or resistivity through the pore, wherein the channels are formed of a single substrate.Type: GrantFiled: March 7, 2003Date of Patent: March 7, 2006Assignee: Sarnoff CorporationInventors: Jia Ming Chen, Yongchi Tian, Zilan Shen, Pradyumna Swain
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Patent number: 6998220Abstract: A method for manufacturing thin-film chip resistors, in which method a resistor layer (14) and a contact layer (15, 16) are applied onto the upper surface of a substrate (10) and structured using laser light so as to form on said substrate (10) a plurality of adjacent, separate resistor lands (24) having a predetermined approximate resistance value, allows the simplified and cheap manufacturing by performing the electrical insulation of the resistor elements (24) and the structuring of the individual resistor lands (24) for the entire resistor land simultaneously by means of a laser-lithographic direct exposure method.Type: GrantFiled: February 19, 2002Date of Patent: February 14, 2006Assignee: BC Components Holdings B.V.Inventors: Wolfgang Werner, Horst Wolf, Reiner Wilhelm Kuehl
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Patent number: 6893972Abstract: The novel process lends itself to the production of highly resolved resist structures. A resist structure having webs is produced from a photoresist on a substrate and then the sidewalls of the webs are selectively chemically amplified so that chemically amplified sidewall structures are obtained. After the removal of the chemically unamplified sections, the amplified sidewall structures are transferred to the substrate. The process permits a resolution of structures that are not producible using the currently customary exposure wavelengths.Type: GrantFiled: September 3, 2002Date of Patent: May 17, 2005Assignee: Infineon Technologies AGInventors: Jörg Rottstegge, Eberhard Kühn, Waltraud Herbst, Christian Eschbaumer, Christoph Hohle, Gertrud Falk, Michael Sebald
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Patent number: 6890448Abstract: New organic-based radiation absorbing compositions are provided that are suitable for use as an antireflective coating composition (“ARC”) for an overcoated photoresist. These compositions also serve effectively as a hard mask layer by exhibiting a sufficient plasma etch selectively from an undercoated dielectric layer.Type: GrantFiled: June 11, 1999Date of Patent: May 10, 2005Assignee: Shipley Company, L.L.C.Inventor: Edward K. Pavelchek
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Patent number: 6858151Abstract: There is provided a method for producing a metal/ceramic bonding article, the method including the steps of: bonding a metal plate 12 of an alloy containing copper and nickel directly to at least one side of a ceramic substrate 10; applying a resist 14 on a predetermined portion of the metal plate 12 to remove an undesired portion of the metal plate 12 by etching; and removing the resist 14 to form a pattern having a predetermined shape of the alloy on the ceramic substrate 10. According to this method, it is possible to reduce the displacement failure of parts to improve productivity and to prevent bonding failure during the mounting of a semiconductor device or the like thereon.Type: GrantFiled: September 25, 2002Date of Patent: February 22, 2005Assignee: Dowa Mining Co., Ltd.Inventors: Nobuyoshi Tsukaguchi, Takayuki Takahashi, Yukihiro Kitamura, Masami Kimura
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Publication number: 20040222184Abstract: In a high-frequency power source, a malfunction is prevented by precisely removing harmonic components or a modulated wave component which develops while producing a plasma, and a proper high frequency power can be impressed on a plasma processing apparatus. The high-frequency power source includes a power monitor constituted of a directional coupler, a mixer, a 100 kHz low-pass filter, a low-frequency detector, and an oscillator. A 100 MHz high-frequency wave including modulated wave components and the like extracted by the directional coupler and 99.9 MHz high-frequency wave oscillated by the oscillator are added by the mixer. An output of the addition is converted by the low-frequency detector into 100 kHz, resulting in detection.Type: ApplicationFiled: June 10, 2004Publication date: November 11, 2004Applicant: TOKYO ELECTRON LIMITEDInventors: Toshihiro Hayami, Takeshi Ohse, Jun-Ichi Takahira, Jun-Ichi Shimada
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Patent number: 6790786Abstract: The invention includes semiconductor processing methods, including methods of forming capacitors. In one implementation, a semiconductor processing method includes providing a semiconductor substrate comprising a layer comprising at least one metal in elemental or metal alloy form. The metal comprises an element selected from the group consisting of platinum, ruthenium, rhodium, palladium, iridium, and mixtures thereof. At least a portion of the layer is etched in a halogenide, ozone and H2O comprising ambient.Type: GrantFiled: March 5, 2002Date of Patent: September 14, 2004Assignee: Micron Technology, Inc.Inventors: Paul A. Morgan, Patrick M. Flynn, Janos Fucsko
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Patent number: 6666980Abstract: A method for manufacturing a resistor function in an electric conductor on the surface of a carrier, preferably a conductor on printed circuit boards, substrates and chips. By etching using an anisotropic etching technique, the conductor is provided with at least one portion which has a smaller cross-sectional area than the conductor surrounding the portion, the length and width of the portion being such that a predetermined resistance is obtained in the conductor. A resistor according to the invention is on both sides connected to a conductor on a carrier, such as a printed circuit board, a substrate or a chip. The resistor comprises a conductor portion positioned on the carrier and having a significantly smaller cross-sectional area than the conductor on both sides of the resistor.Type: GrantFiled: September 1, 2000Date of Patent: December 23, 2003Assignee: Obducat ABInventor: Bo Wikstrom
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Publication number: 20030209515Abstract: New organic-based radiation absorbing compositions are provided that are suitable for use as an antireflective coating composition (“ARC”) for an overcoated photoresist. These compositions also serve effectively as a hard mask layer by exhibiting a sufficient plasma etch selectively from an undercoated dielectric layer.Type: ApplicationFiled: June 9, 2003Publication date: November 13, 2003Applicant: Shipley Company, L.L.C.Inventor: Edward K. Pavelchek
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Patent number: 6592771Abstract: A method in which etching or ashing is conducted by providing satisfactory kinetic energy of reaction seeds such as ions or radicals without damaging a substrate, and an apparatus used in this method are provided. A predetermined film of for example polycrystalline silicon on the substrate is etched in vapor phase using reaction seeds or precursors thereof generated by contacting a reaction gas such as CF4 with a heated catalyst of for example tungsten.Type: GrantFiled: April 7, 2000Date of Patent: July 15, 2003Assignee: Sony CorporationInventors: Hideo Yamanaka, Kikuo Kaise
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Patent number: 6585909Abstract: An oxide for use in a bolometer with an oxide thin-film formed is manufactured on an insulating substrate. Metal organic compound is dissolved in solvent to form solution during manufacturing the oxide thin-film. The solution is applied on the insulating substrate, and the applied solution is dried. A bond between carbon and oxygen is cut and decomposed by irradiating a laser ray with wavelength of 400 nm or less. A generated oxide is crystallized.Type: GrantFiled: October 31, 2001Date of Patent: July 1, 2003Assignees: National Institute of Advanced Industrial Science & Technology, NEC CorporationInventors: Tetsuo Tsuchiya, Susumu Mizuta, Toshiya Kumagai, Tsutomu Yoshitake, Yuichi Shimakawa, Yoshimi Kubo
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Patent number: 6565759Abstract: A method for etching a pattern within a silicon containing dielectric layer upon a substrate employed within a microelectronics fabrication, employing a plasma activated reactive gas mixture, with layer material etch rate, etch rate ratio and pattern aspect ratio controlled by controlling the gas composition. There is provided a silicon substrate formed upon it a patterned microelectronics layer over which is formed a silicon containing dielectric layer. There is placed the silicon substrate within a reactor chamber equipped with electrodes which is evacuated. There is then filled the reactor chamber with a reactive gas mixture consisting of an oxidizing gas and two reactive gases. There may be optionally included in the reactive gas mixture nitrogen and inert gases for control purposes, but excluded from the reactive gas mixture are oxidizing gases containing carbon and oxygen.Type: GrantFiled: August 16, 1999Date of Patent: May 20, 2003Assignee: Vanguard International Semiconductor CorporationInventors: Bi-Ling Chen, Erik S. Jeng, Hao-Chieh Liu
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Publication number: 20030057181Abstract: A method of manufacturing a microstrip termination is provided, the microstrip termination containing a transmission line, a tapered edge ground and a thin film resistor connecting a transmission line to the tapered edge ground. Circuits are manufactured by first cutting holes in a substrate forming alignment holes for dicing the substrate into separate circuits. A saw is then used to cut tapered grooves along the alignment holes for forming tapered edges. The substrate is then plated and etched to form the transmission lines, thin film resistors, and ground planes. Finally, the substrate is diced into the separate termination circuits.Type: ApplicationFiled: September 21, 2001Publication date: March 27, 2003Inventor: William W. Oldfield
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Patent number: 6514671Abstract: The present invention provides integrated circuit fabrication methods and devices wherein dual damascene structures (332 and 334) are formed in consecutive dielectric layers (314 and 316) having dissimilar etching characteristics. The present invention also provides for such methods and devices wherein these dielectric layers have different dielectric constants. Additional embodiments of the present invention include the use of single layer masks, such as silicon-based photosensitive materials which form a hard mask (622) upon exposure to radiation. In additional embodiments, manufacturing systems (710) are provided for fabricating IC structures. These systems include a controller (700) which is adapted for interacting with a plurality of fabrication stations (720, 722, 724, 726, 728 and 730).Type: GrantFiled: September 29, 2000Date of Patent: February 4, 2003Assignee: Applied Materials, Inc.Inventors: Suketu A. Parikh, Mehul B. Naik, Samuel Broydo, H. Peter W. Hey
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Publication number: 20030000917Abstract: In a semiconductor device having a front surface where circuits are formed and a back surface, a hemispherical solid immersion lens is formed at the back surface of the semiconductor device in a body with the semiconductor device.Type: ApplicationFiled: August 29, 2002Publication date: January 2, 2003Applicant: NEC CorporationInventor: Hideki Kitahata
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Patent number: 6500350Abstract: A method is provided for forming a patterned layer of resistive material in electrical contact with a layer of electrically conducting material. A three-layer structure is formed which comprises a metal conductive layer, an intermediate layer formed of material which is degradable by a chemical etchant, and a layer of resistive material of sufficient porosity such that the chemical etchant for said intermediate layer may seep through the resistive material and chemically degrade said intermediate layer so that the resistive material may be ablated from said conductive layer wherever the intermediate layer is chemically degraded. A patterned photoresist layer is formed on the resistive material layer. The resistive material layer is exposed to the chemical etchant for said intermediate layer so that the etchant seeps through the porous resistive material layer and degrades the intermediate layer. Then, portions of the resistive material layer are ablated away wherever the intermediate layer has been degraded.Type: GrantFiled: February 8, 2001Date of Patent: December 31, 2002Assignee: Morton International, Inc.Inventors: Andrew T. Hunt, Wen-Yi Lin, Shara S. Shoup, Richard W. Carpenter, Stephen E. Bottomley, Tzyy Jiuan Hwang, Michelle Hendrick
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Publication number: 20020195419Abstract: New organic-based radiation absorbing compositions are provided that are suitable for use as an antireflective coating composition (“ARC”) for an overcoated photoresist. These compositions also serve effectively as a hard mask layer by exhibiting a sufficient plasma etch selectively from an undercoated dielectric layer.Type: ApplicationFiled: June 11, 1999Publication date: December 26, 2002Inventor: EDWARD K. PAVELCHEK
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Patent number: 6497824Abstract: A method for integrating a thin film resistor (60) into an interconnect process flow. Metal interconnect lines (40) are formed over a semiconductor body (10). An interlevel dielectric (50) is then formed over the metal interconnect lines (40). Conductively filled vias (62) are then formed through the interlevel dielectric (50) to the metal interconnect lines (40). A thin film resistor (60) is then formed connecting between at least two of the conductively filled vias (62) using a single mask step. Connection to the resistor (60) is from below using a via process sequence already required for connecting between interconnect layers (40, 64). Thus, only one additional mask step is required to incorporate the resistor (60).Type: GrantFiled: September 14, 2000Date of Patent: December 24, 2002Assignee: Texas Instruments IncorporatedInventors: Chun-Liang A. Chen, Philipp Steinmann, Stuart M. Jacobsen
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Patent number: 6475703Abstract: A multilayer circuit board having air bridge crossover structures and an additive method for producing the same, wherein the circuit includes specially designed metallic fortifying layers to mechanically and/or electrically fortify the circuit.Type: GrantFiled: December 1, 1998Date of Patent: November 5, 2002Assignee: Visteon Global Technologies, Inc.Inventors: Delin Li, Achyuta Achari, Alice Dawn Zitzmann, Robert Edward Belke, Jr., Brenda Joyce Nation, Edward McLeskey, Mohan R. Paruchuri, Lakhi Nandlal Goenka
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Patent number: 6475400Abstract: A method for controlling the sheet resistance of thin film resistors. The sheet resistance can be inexpensively controlled within a tight tolerance by determining a desired final value for the sheet resistance of thin film resistor material to be deposited on a substrate, depositing the resistor material on the substrate using a deposition process which is consistent enough to achieve a target sheet resistance within a first specified tolerance, the resistor material being deposited to achieve a target sheet resistance which is equal to the desired final value minus the first specified tolerance, and removing a small amount of material from the surface of the deposited thin film resistor material by etching or ion bombardment to raise the sheet resistance to the desired final value within a second specified tolerance characteristic of the removing process where the second specified tolerance is less than the first specified tolerance.Type: GrantFiled: February 26, 2001Date of Patent: November 5, 2002Assignee: TRW Inc.Inventor: Michael D. Lammert
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Publication number: 20020134963Abstract: A new cleaning chemistry based on a choline compound, such as choline hydroxide, is provided in order to address the problem of dual damascene fabrication. An etch stop inorganic layer at the bottom of a dual damascene structure protects the underlying interconnect of copper and allows a better cleaning. A two step etch process utilizing the etch stop layer is used to achieve the requirements of ULSI manufacturing in a dual damascene structure.Type: ApplicationFiled: December 4, 2001Publication date: September 26, 2002Applicant: EKC Technology, Inc.Inventors: Catherine M. Peyne, David J. Maloney, Shihying Lee, Wai Mun Lee, Leslie W. Arkless
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Publication number: 20020130102Abstract: The present invention provides a method of forming a thin-film resistor positioned on a semiconductor wafer. The method comprises forming a resistance layer and an insulating layer in a predetermined area of the dielectric layer, the insulating layer being positioned on the resistance layer; performing a first etching process to remove the insulating layer on two ends of the resistance layer to form two openings; forming a conductive layer on the insulating layer and filling the two openings, the conductive layer being electrically linked with the two ends of the resistance layer from the two openings; and performing a second etching process to remove the conductive layer outside the resistance layer and partial conductive layer on the insulating layer to form two disconnected conductive layers, the two openings being separately positioned below the two disconnected conductive layers.Type: ApplicationFiled: March 13, 2001Publication date: September 19, 2002Inventor: Jia-Sheng Lee
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Publication number: 20020117470Abstract: A method for controlling the sheet resistance of thin film resistors. The sheet resistance can be inexpensively controlled within a tight tolerance by determining a desired final value for the sheet resistance of thin film resistor material to be deposited on a substrate, depositing the resistor material on the substrate using a deposition process which is consistent enough to achieve a target sheet resistance within a first specified tolerance, the resistor material being deposited to achieve a target sheet resistance which is equal to the desired final value minus the first specified tolerance, and removing a small amount of material from the surface of the deposited thin film resistor material by etching or ion bombardment to raise the sheet resistance to the desired final value within a second specified tolerance characteristic of the removing process where the second specified tolerance is less than the first specified tolerance.Type: ApplicationFiled: February 26, 2001Publication date: August 29, 2002Inventor: Michael D. Lammert
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Patent number: 6420272Abstract: In semiconductor dynamic random access memory circuits using stacked capacitor storage elements formed using high permittivity dielectric material, it is typical to form the stacked capacitors using noble metal electrodes. Typically, the etching process for the noble metal electrodes requires the use of a hard mask patterning material such as silicon oxide. Removal of this hard mask frequently results in damage to the dielectric surface surrounding the patterned noble metal electrode.Type: GrantFiled: December 14, 1999Date of Patent: July 16, 2002Assignees: Infineon Technologies A G, International Business Machines CorporationInventors: Hua Shen, David Edward Kotecki, Satish D. Athavale, Jenny Lian, Gerhard Kunkel, Nimal Chaudhary
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Publication number: 20020086243Abstract: A multilayer circuit board having air bridge crossover structures and an additive method for producing the same, wherein the circuit includes specially designed metallic fortifying layers to mechanically and/or electrically fortify the circuit.Type: ApplicationFiled: December 1, 1998Publication date: July 4, 2002Inventors: DELIN LI, ACHYUTA ACHARI, ALICE DAWN ZITZMANN, ROBERT EDWARD BELKE, BRENDA JOYCE NATION, EDWARD MCLESKEY, MOHAN R. PARUCHURI, LAKHI NANDLAL GOENKA
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Patent number: 6379569Abstract: The invention relates to a process for chemically etching a layer (2) having electrical conduction properties, on a transparent substrate (1) of the glass type. It includes at least one step of depositing a mask (3) comprising at least one hot-melt ink on the layer to be etched.Type: GrantFiled: February 23, 1999Date of Patent: April 30, 2002Assignee: Saint-Gobain VitrageInventor: Marc Rouberol
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Publication number: 20020014403Abstract: After a Ta radiation absorber 13 is subjected to reactive ion overetching to form a desired pattern till an upper portion of the SiO2 buffer film 12 is removed, the buffer film 12 is removed by two steps of reactive sputter pre-underetching and final wet etching. In the wet etching, a substrate is rotated while spraying a dilute hydrofluoric acid solution, spray and rotation are ceased, the substrate is illuminated with a light beam to detect regularly reflected light, the detected signal is amplified, differentiated and compared with a reference voltage to detect an etching endpoint, and etching is ceased after a predetermined time has elapsed from the detection of the etching endpoint. At an inspection step, an image of a reflective mask is obtained with a microscope and it is determined that the side etching amount of the buffer film is short if the luminance, at a point of the maximum change rate on a luminance curve around the edge of the Ta radiation absorber 13, is lower than a reference value.Type: ApplicationFiled: April 3, 2001Publication date: February 7, 2002Inventor: Eiichi Hoshino
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Publication number: 20020003127Abstract: A method of manufacturing a wireless suspension blank is a method of manufacturing a wireless blank in which three-layered laminate formed of a metallic layer having the spring property and a conductive layer laminated on the metallic layer through an electrically insulating layer are used, wherein as the laminate used is a laminate in which an insulating layer is formed of core-insulating layer and adhesive layers laminated on both sides of the core-insulating layer, and the ratio of higher etching rate to lower etching rate of the respective layers of the insulating layer is between 6:1 and 1:1. By the photo etching method processed are the metallic layer and the conductive layer. The insulating layer is processed by the wet etching method.Type: ApplicationFiled: July 6, 2001Publication date: January 10, 2002Inventors: Katsuya Sakayori, Shigeki Kawano, Hiroko Amasaki, Kazuo Umeda, Satoshi Sasaki, Hiroshi Yagi
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Patent number: 6322711Abstract: A method for forming a thin film resistor. There is first provided an insulator substrate. There is then formed upon the insulator substrate a blanket thin film resistive layer. There is then removed through a non-photolithographic etching method a portion of the blanket thin film resistive layer to form upon the substrate a patterned thin film resistive layer. Finally, there is then formed through a non-photolithographic printing method upon the patterned thin film resistive layer a patterned conductor lead layer. Alternatively, the portion of the blanket thin film resistive layer may be removed to form the patterned thin film resistive layer after the patterned conductor lead layer is formed upon the blanket thin film resistive layer.Type: GrantFiled: June 22, 1999Date of Patent: November 27, 2001Assignee: Yageo CorporationInventor: Wood Mu-Yuan Chen
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Patent number: 6319846Abstract: A method for removing a multiplicity of solder bodies connected to a semiconductor wafer through a copper wetting layer from the semiconductor wafer is disclosed. In the method, a semiconductor wafer that has on a top surface a multiplicity of solder bodies electrically connected to a multiplicity of bond pads through a multiplicity of copper wetting layers is first provided. When the multiplicity of solder bodies is found out of specification or must be removed for any other quality reasons, the semiconductor wafer is exposed to an etchant that has an etch rate toward the copper wetting layer at least 5 times the etch rate toward a metal that forms the multiplicity of bond pads. The semiconductor wafer may be removed from the etchant when the multiplicity of copper wetting layers is substantially dissolved such that the multiplicity of solder bodies is separated from the multiplicity of bond pads. The multiplicity of solder bodies may be either solder bumps or solder balls.Type: GrantFiled: January 5, 2001Date of Patent: November 20, 2001Assignee: Taiwan Semiconductor Manufacturing Company, LtdInventors: Kuo-Wei Lin, James Chen, Eugene Chu, Alex Fahn, Chiou-Shian Peng, Gilbert Fane, Kenneth Lin
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Patent number: 6280644Abstract: The invention provides a method of planarizing an irregular surface of a semiconductor wafer. In one embodiment, the method comprises applying a photoresist material over recessed areas and protruding areas of the irregular surface, etching the photoresist, etching partially into protruding areas of the irregular surface to remove a portion of the irregular surface, and polishing the irregular surface to a substantially planar surface. In some embodiments method may include chemically and mechanically polishing the irregular surface.Type: GrantFiled: April 23, 1999Date of Patent: August 28, 2001Assignee: Agere Systems Guardian Corp.Inventors: Edward P. Martin, Morgan J. Thoma, Daniel J. Vitkavage
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Publication number: 20010013502Abstract: There is provided a resist film removing composition used in a manufacture of a thin film circuit element having an organic insulation film that can remove a resist film remaining after etching easily without swelling the organic insulation film. The resist film removing composition comprises 50 to 90% by weight of an alkanolamine having 3 or more carbon atoms, 8 to 40% by weight of a water-miscible solvent and 2 to 30% by weight of water.Type: ApplicationFiled: October 21, 1998Publication date: August 16, 2001Applicant: SHARP CORPORATION; MITSUBISHI GAS CHEMICAL COMPANY INCORPORATEDInventors: MASAHIRO NOHARA, YUKIHIKO TAKEUCHI, TAIMI OKETANI, TAKETO MARUYAMA, TETSUYA KARITA, HISAKI ABE, TETSUO AOYAMA
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Publication number: 20010002337Abstract: In one aspect, the invention provides a method of exposing a material from which photoresist cannot be substantially selectively removed utilizing photoresist. In one preferred implementation, a first material from which photoresist cannot be substantially selectively removed is formed over a substrate. At least two different material layers are formed over the first material. Photoresist is deposited over the two layers and an opening formed within the photoresist over an outermost of the two layers. First etching is conducted through the outermost of the two layers within the photoresist opening to outwardly expose an innermost of the two layers and form an exposure opening thereto. After the first etching, photoresist is stripped from the substrate. After the stripping, a second etching is conducted of the innermost of the two layers within the exposure opening.Type: ApplicationFiled: December 26, 2000Publication date: May 31, 2001Inventors: Gurtej S. Sandhu, Shubneesh Batra
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Patent number: 6232618Abstract: A temperature-dependent measuring resistor is connected to a reference resistor in series, wherein this series connection is flowed through by a constant impressed current. A connection point located between the two resistors is connected to the N-input of a first feedback differential amplifier, whose P-input is supplied with direct current voltage tapped from a voltage divider. During a temperature increase in the area of the measuring resistor, the potential increases at the output of the first differential amplifier, which delivers the constant impressed current and is connected to the measuring resistor, while the potential at the output of the differential amplifier falls when the temperature falls. The temperature-dependent voltage signal that is output at the differential amplifier is supplied in subtracting connection to the P-input of an after-connected second differential amplifier, whose output is connected to a measurement unit for measuring the voltage characteristic of the temperature.Type: GrantFiled: December 22, 1998Date of Patent: May 15, 2001Assignee: Heraeus Electro-Nite International N.V.Inventors: Karlheinz Wienand, Andreas Müller
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Publication number: 20010000897Abstract: A method for producing stable atmospheric pressure glow discharge plasmas using RF excitation and the use of said plasmas for modifying the surface layer of materials. The plasma generated by this process and its surface modification capability depend on the type of gases used and their chemical reactivity. These plasmas can be used for a variety of applications, including etching of organic material from the surface layer of inorganic substrates, as an environmentally benign alternative to industrial cleaning operations which currently employ solvents and degreasers, as a method of stripping paint from surfaces, for the surface modification of composites prior to adhesive bonding operations, for use as a localized etcher of electronic boards and assemblies and in microelectronic fabrication, and for the sterilization of tools used in medical applications.Type: ApplicationFiled: December 7, 2000Publication date: May 10, 2001Inventors: Kin Li, Minas Tanielian