Forming Or Treating Resistive Material Patents (Class 216/16)
-
Publication number: 20130029481Abstract: A method of making templated circuitry employs a template system that includes a template of an insulator material on a carrier having a conductive surface. The template includes multiple levels and multiple regions, wherein a first level exposes the conductive surface of the carrier. A first metal is electrochemically deposited on the conductive surface in first regions of the first level. A circuit material is deposited to cover the first metal. The template is etched until a second level of the template exposes the conductive surface in second regions on opposite sides of the first regions. A second metal is electrochemically deposited on the conductive surface in the second regions. The template of deposited materials is transferred from the carrier to a substrate.Type: ApplicationFiled: July 28, 2011Publication date: January 31, 2013Inventors: David Fitzpatrick, Kevin Dooley, Lorraine Byrne
-
Publication number: 20130026444Abstract: A method and semiconductor device for synthesizing graphene using ion implantation of carbon. Carbon is implanted in a metal using ion implantation. After the carbon is distributed in the metal, the metal is annealed and cooled in order to precipitate the carbon from the metal to form a layer of graphene on the surface of the metal. The metal/graphene surface is then transferred to a dielectric layer in such a manner that the graphene layer is placed on top of the dielectric layer. The metal layer is then removed. Alternatively, recessed regions are patterned and etched in a dielectric layer located on a substrate. Metal is later formed in these recessed regions. Carbon is then implanted into the metal using ion implantation. The metal may then be annealed and cooled in order to precipitate the carbon from the metal to form a layer of graphene on the metal's surface.Type: ApplicationFiled: October 8, 2012Publication date: January 31, 2013Applicants: TEXAS INSTRUMENTS, INC., BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEMInventors: BOARD OF REGENTS, THE UNIVERSITY OF TE, TEXAS INSTRUMENTS, INC.
-
Publication number: 20130001187Abstract: A method for manufacturing a magnetic sensor using an electrical lapping guide deposited and patterned simultaneously with a hard bias structure of the sensor material. The method includes depositing a sensor material, and patterning and ion milling the sensor material to define a track width of the sensor. A magnetic, hard bias material is then deposited and a second patterning and ion milling process is performed to simultaneously define the back edge of an electrical lapping guide and a back edge of the sensor.Type: ApplicationFiled: June 29, 2011Publication date: January 3, 2013Inventors: Quang Le, Shin Funada, Jui-Lung Li
-
Publication number: 20130000965Abstract: Disclosed herein are a dielectric composition of a multilayered circuit board including two types of inorganic fillers of 10 to 60 parts by weight with respect to an epoxy resin of 100 parts by weight, a multilayered printed circuit board including a dielectric layer manufactured of the dielectric composition, and a method for preparing the multilayered printed circuit board. According to the present invention, by mixing two types of inorganic fillers such as SiO2 and CaCO3 in manufacturing the dielectric layer of the multilayered circuit board, a high adhesive strength to a plating layer can be achieved without using a fluoride-based solution including 3NH4HF2 as an oxidant while etching the dielectric layer and furthermore, an environmentally hazardous substance can be prevented from being discharged.Type: ApplicationFiled: May 11, 2012Publication date: January 3, 2013Inventors: Dong Joo SHIN, Seong Min Chin, Moon Soo Park, Sung Taek Lim, Sung Hyun Kim, Choon Keun Lee
-
Patent number: 8334187Abstract: Methods of fabricating an integrated circuit device, such as a thin film resistor, are disclosed. An exemplary method includes providing a semiconductor substrate; forming a resistive layer over the semiconductor substrate; forming a hard mask layer over the resistive layer, wherein the hard mask layer includes a barrier layer over the resistive layer and a dielectric layer over the barrier layer; and forming an opening in the hard mask layer that exposes a portion of the resistive layer.Type: GrantFiled: June 28, 2010Date of Patent: December 18, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Wen Chang, Der-Chyang Yeh, Chung-Yi Yu, Hsun-Chung Kuang, Hua-Chou Tseng, Chih-Ping Chao, Ming Chyi Liu, Yuan-Tai Tseng
-
Publication number: 20120300596Abstract: In a detent escapement 100, a blade 130 includes a plurality of blade components that includes a one side actuating spring 140 which includes a portion capable of contacting the unlocking stone 124, and a one side actuating spring support arm 133 which determines a position of an unlocking stone contact portion 140G which is positioned in a tip of the one side actuating spring 140. At least two of the blade components are formed of the same material as each other, and each thickness is the same as each other.Type: ApplicationFiled: August 31, 2010Publication date: November 29, 2012Inventors: Masayuki Koda, Takashi Niwa
-
Patent number: 8282284Abstract: A micro drive assembly may comprise a substrate, a micro shall oriented in-plane with the substrate and at least one micro bearing to support rotation of the micro shaft. The micro shaft and micro bearing may be in or less than the micrometer domain.Type: GrantFiled: June 1, 2007Date of Patent: October 9, 2012Assignee: MicroZeus, LLCInventor: Harold L. Stalford
-
Publication number: 20120241200Abstract: The problem of the present invention is to provide a circuit board comprising a shape retention unit capable of thinning while maintaining mechanical strength. The present invention solves the above-mentioned problem by providing a circuit board comprising a metal supporting substrate, a first insulating layer formed on the above-mentioned metal supporting substrate, and a wiring layer formed on the above-mentioned first insulating layer, wherein an open area is formed in the above-mentioned metal supporting substrate, and the circuit board comprises a shape retention unit having a second insulating layer contacting with the above-mentioned metal supporting substrate and a reinforcing layer formed on the above-mentioned second insulating layer, and bridging the above-mentioned metal supporting substrate divided by the above-mentioned open area.Type: ApplicationFiled: December 24, 2010Publication date: September 27, 2012Applicant: DAI NIPPON PRINTING CO., LTD.Inventors: Junichi Chiyonaga, Hiromichi Takatsu, Yoichi Miura, Yoichi Nagai
-
Publication number: 20120199736Abstract: A micro-reflectron for a time-of-flight mass spectrometer including a substrate and integrated with the volume of the substrate, means for application of a potential gradient in a volume suitable for constituting a flight zone of the ions. The means of application includes at least two polarization electrodes and a wall of at least one resistive material that can be polarized between these electrodes so as to generate a continuous potential gradient, itself providing the function of reflectron, this flight zone, these electrodes and this wall being obtained by the technology of microelectromechanical systems (MEMS) and this micro-reflectron having a thickness of less than 5 millimetres while its other dimensions are less than 10 times this thickness.Type: ApplicationFiled: February 6, 2012Publication date: August 9, 2012Inventors: Jean-Sebastien DANEL, Laurent DURAFFOURG, Frederic PROGENT, Charles-Marie TASSETTI
-
Publication number: 20120152599Abstract: A multi-layer printed-wiring-board is used in densely packaging electronic components such as semiconductors having improved function, and a production method therefor, and more specifically it achieves a multi-layer printed-wiring-board having excellent copper-foil-peel-strength and high connection-reliability in which occurrence of structural defects such as delamination (interlayer peeling) is prevented, and a production method therefor. Because of thinning of the printed-wiring-board or diversification of insulating layers constituting the printed-wiring-board, peeling such as delamination may occur between the insulating layers or in an interface between the insulating layer and the plated conductor.Type: ApplicationFiled: September 2, 2010Publication date: June 21, 2012Applicant: PANASONIC CORPORATIONInventors: Yoshito Kitagawa, Naoyuki Tani, Toshiyuki Asahi
-
Publication number: 20120125881Abstract: A method of manufacturing a coordinate detector having a resistive film and a common electrode for applying a voltage to the resistive film is disclosed that includes the steps of (a) applying a photoresist onto the resistive film formed on a substrate formed of an insulator; (b) forming a resist pattern on the resistive film by exposing the applied photoresist to light through a predetermined mask and subsequently developing the applied photoresist; (c) forming a resistive film removal region by removing a portion of the resistive film without the resist pattern; (d) removing the resist pattern after step (c); and (e) forming the common electrode over the resistive film removal region after step (d).Type: ApplicationFiled: February 3, 2012Publication date: May 24, 2012Applicant: FUJITSU COMPONENT LIMITEDInventor: Koichi KONDOH
-
Publication number: 20120062346Abstract: A parallel plate waveguide structure may be configured to suppress spurious propagating modes by including a lossy frequency selective surface (FSS) formed from a resistive film. The electromagnetic material properties of individual layers disposed between the conductive plates of the waveguide may be engineered to extend the suppression band of the fundamental TE mode up to the cutoff frequency of the second TE mode, and to simultaneously create a multi-octave TM mode suppression band. Applications include, for example, cavity mode suppression in microwave and millimeterwave assemblies at the board, package, and chip level.Type: ApplicationFiled: October 19, 2011Publication date: March 15, 2012Inventor: William E. McKinzie, III
-
Publication number: 20120062355Abstract: A nanoflat resistor includes a first aluminum electrode (360), a second aluminum electrode (370); and nanoporous alumina (365) separating the first and second aluminum electrodes (360, 370). A substantially planar resistor layer (330) overlies the first and second aluminum electrodes (360, 370) and nanoporous alumina (365). Electrical current passes from the first aluminum electrode (360), through a portion of the planar resistor layer (350) overlying the nanoporous alumina (365) and into the second aluminum electrode (370). A method for constructing a nanoflat resistor (390) is also provided.Type: ApplicationFiled: May 19, 2009Publication date: March 15, 2012Inventors: Arjang Fartash, Peter Mardilovich
-
Patent number: 8129092Abstract: The present invention provides a resist pattern thickening material, which can utilize ArF excimer laser light; which, when applied over a resist pattern such as an ArF resist having a line pattern or the like, can thicken the resist pattern regardless of the size of the resist pattern; which has excellent etching resistance; and which is suited for forming a fine space pattern or the like, exceeding the exposure limits. The present invention also provides a process for forming a resist pattern and a method for manufacturing a semiconductor device, wherein the resist pattern thickening material of the present invention is suitably utilized.Type: GrantFiled: February 27, 2006Date of Patent: March 6, 2012Assignee: Fujitsu LimitedInventors: Miwa Kozawa, Koji Nozaki
-
Publication number: 20120049183Abstract: A film formation is performed using a target in which a material which is volatilized more easily than gallium when heated at 400° C. to 700° C., such as zinc, is added to gallium oxide by a sputtering method with high mass-productivity which can be applied to a large-area substrate, such as a DC sputtering method or a pulsed DC sputtering method. This film is heated at 400° C. to 700° C., whereby the added material is segregated in the vicinity of a surface of the film. Another portion of the film has a decreased concentration of the added material and a sufficiently high insulating property; therefore, it can be used for a gate insulator of a semiconductor device, or the like.Type: ApplicationFiled: August 17, 2011Publication date: March 1, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventor: Shunpei YAMAZAKI
-
Publication number: 20120031746Abstract: The present invention provides a method of manufacturing a touch screen, comprising the steps of: a) forming a conductive layer on a substrate; b) forming an etching resist pattern on the conductive layer; and c) forming a conductive pattern having a line width smaller than the line width of the etching resist pattern by over-etching the conductive layer by using the etching resist pattern and a touch screen manufactured by the method. According to the present invention, a touch screen comprising a conductive pattern having an ultrafine line width can be economically and efficiently provided.Type: ApplicationFiled: February 8, 2010Publication date: February 9, 2012Applicant: LG CHEM, LTDInventors: Ji-Young Hwang, In-Seok Hwang, Sang-Ki Chun, Dong-Wook Lee, Yong-Koo Son, Min-Choon Park, Seung-Heon Lee, Beom-Mo Koo, Young-Jun Hong, Ki-Hwan Kim, Su-Jin Kim, Hyeon Choi
-
Patent number: 8092696Abstract: An insulating layer made of an insulator film or the like is prepared. Then, a thin metal film and a thin copper film are formed in sequence on the insulating layer. The thin copper film is subsequently laminated with a dry film or the like, and exposed and developed to form a plating resist thereon that have patterns opposite to conductor patterns which are formed in a subsequent step. This is followed by forming conductor patterns made of copper, by electrolytic plating using an electrolytic copper sulfate plating solution, on the surfaces of the thin copper film where the plating resist is not formed. The plating resist is then removed by, for example, stripping. After this, the thin copper film is held at a temperature of not less than 200° C. and not more than 300° C. for approximately an hour to be thermally treated. Then, the thin copper film and the thin metal film are removed by chemical etching except the portions under the conductor patterns.Type: GrantFiled: December 13, 2007Date of Patent: January 10, 2012Assignee: Nitto Denko CorporationInventors: Kei Nakamura, Takeshi Yamato
-
Publication number: 20110244263Abstract: A method of patterning and an article having a patterned structure defined therein are provided. The method comprises the steps of providing a substrate having a patterned conductive metal film disposed thereon. The patterned conductive metal film has at least one raised feature. The patterned conductive metal film defines at least one recess therein that is adjacent to the at least one raised feature. A surface of the substrate is exposed in the at least one recess. The pattern is modified through electrolysis in an electrodeposition setup including an electrolyte and two electrodes. The patterned conductive metal film is one of the electrodes during electrolysis. The method is ideal for shrinking initial patterns having features that are on the magnitude of microscale dimensions to obtain a final pattern having features that are on the magnitude of nanoscale dimensions.Type: ApplicationFiled: April 4, 2011Publication date: October 6, 2011Inventors: Peicheng Ku, Leung Kway Lee
-
Publication number: 20110235213Abstract: The object of the present invention is to provide a suspension substrate such that the thickness of an insulating layer for supporting a connecting terminal having a flying structure is uniform. The present invention attains the object by providing a suspension substrate, comprising a metal supporting substrate, an insulating layer formed on the metal supporting substrate, and a wiring layer formed on the insulating layer, wherein a wiring layer projecting section is provided by a plurality; an adjusting section formed on the insulating layer and composed of a first adjusting section and a second adjusting section is provided on both sides of the plural wiring layer projecting sections; and a gap between a first outermost wiring layer projecting section and the first adjusting section, a gap between the adjacent wiring layer projecting sections, and a gap between a second outermost wiring layer projecting section and the second adjusting section are equal.Type: ApplicationFiled: March 22, 2011Publication date: September 29, 2011Applicant: DAI NIPPON PRINTING CO., LTD.Inventor: Masao OHNUKI
-
Patent number: 8021564Abstract: A method for detecting an end point of a resist peeling process in which a resist is gasified to be peeled off by producing hydrogen radicals by catalytic cracking reaction where a hydrogen-containing gas contacts with a high-temperature catalyst, and contacting the produced hydrogen radicals with a resist on a substrate, includes monitoring one or more parameters indicating a state of the catalyst and detecting the end point of the resist peeling process based on variations of the monitored parameters. The hydrogen-containing gas may be a H2 gas. The parameters indicating the state of the catalyst may be one or more electrical parameters when a power is supplied to the catalyst. Further, the catalyst may be a filament made of a high melting point metal.Type: GrantFiled: October 5, 2007Date of Patent: September 20, 2011Assignee: Tokyo Electron LimitedInventors: Isamu Sakuragi, Kazuhiro Kubota
-
Publication number: 20110214728Abstract: Certain example embodiments of this invention relate to large-area transparent conductive coatings (TCCs) including carbon nanotubes (CNTs) and nanowire composites, and methods of making the same. The ?dc/?opt ratio of such thin films may be improved via stable chemical doping and/or alloying of CNT-based films. The doping and/or alloying may be implemented in a large area coating system, e.g., on glass and/or other substrates. In certain example embodiments, a CNT film may be deposited and then doped via chemical functionalization and/or alloyed with silver and/or palladium. Both p-type and n-type dopants may be used in different embodiments of this invention. In certain example embodiments, silver and/or other nanowires may be provided, e.g., to further decrease sheet resistance. Certain example embodiments may provide coatings that approach, meet, or exceed 90% visible transmission and 90 ohms/square target metrics.Type: ApplicationFiled: March 4, 2010Publication date: September 8, 2011Applicant: Guardian Industries Corp.Inventor: Vijayen S. Veerasamy
-
Publication number: 20110210804Abstract: Provided is a resin multilayer device having a balun, wherein the resin multilayer device comprises: a substrate; a first resin layer formed on the substrate; two balanced signal transmission lines that are electrically independently disposed on the first resin layer; a second resin layer formed on the two balanced signal transmission lines and the first resin layer; an unbalanced signal transmission line disposed on the second resin layer and facing the two balanced signal transmission lines; and a third resin layer formed on the unbalanced signal transmission line and the second resin layer.Type: ApplicationFiled: May 6, 2011Publication date: September 1, 2011Applicant: FUJIKURA LTD.Inventors: Yusuke UEMICHI, Takuya AIZAWA, Osamu NAKAO
-
Publication number: 20110111344Abstract: A photosensitive resin composition comprising (A) a binder polymer, (B) a photopolymerizing compound having an ethylenic unsaturated bond in the molecule, (C) a photopolymerization initiator and (D) a polymerization inhibitor, wherein the content of the (D) polymerization inhibitor is 20-100 ppm by mass based on the total solid content of the composition.Type: ApplicationFiled: April 24, 2009Publication date: May 12, 2011Applicant: HITACHI CHEMICAL COMPANY, LTD.Inventors: Yoshiki Ajioka, Mitsuru Ishi, Junichi Iso
-
Publication number: 20110089967Abstract: Provided are a micro-electro-mechanical system (MEMS) probe card and a method for manufacturing the same. The method includes preparing first to nth low-temperature co-fired ceramic (LTCC) substrates each having a via hole, filling each via hole with a via filler conductor or a resistor, stacking the first to nth LTCC substrates and firing the stacked substrates at a temperature of 1,000° C. or less to prepare a LTCC multilayer substrate, forming an insulating layer on the surface of the LTCC multilayer substrate, and forming a thin film conductive line on the surfaces of the insulating layer and the via filler conductor.Type: ApplicationFiled: April 21, 2009Publication date: April 21, 2011Inventor: Sanghee Kim
-
Publication number: 20110086488Abstract: A reactive ion etching (RIE) process comprising a chlorine source gas and an oxygen source gas with an atomic ratio of chlorine to oxygen in the plasma of at least 6 to 1 is used to etch chromium alloy films such as SiCr, SiCrC, SiCrO, SiCrCO, SiCrCN, SiCrON, SiCrCON, CrO, CrN, CrON, and NiCr for example. Additionally, a fluorine source may be added to the etch chemistry.Type: ApplicationFiled: October 12, 2009Publication date: April 14, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: Abbas ALI
-
Publication number: 20110084061Abstract: Techniques for providing heat to a small area and apparatus capable of providing heat to a small area are provided.Type: ApplicationFiled: October 14, 2009Publication date: April 14, 2011Applicant: KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATIONInventors: Kwangyeol LEE, Donghoon CHOI
-
Patent number: 7922922Abstract: An object of this invention is to provide a manufacturing method that, by using a general-purpose semiconductor fabrication process, can easily manufacture an ink jet print head in which energy generating elements are complicatedly installed in the ink path. To this end, the present invention comprising steps of providing a substrate having a removal projected portion, forming an energy generating element along the projected portion, forming a supporting member on the energy generating element, and forming a ink chamber by removing the projected portion from the substrate.Type: GrantFiled: November 5, 2007Date of Patent: April 12, 2011Assignee: Canon Kabushiki KaishaInventor: Masaya Uyama
-
Publication number: 20110000426Abstract: A substrate processing apparatus for heating a substrate is provided. The substrate processing apparatus can include a top and bottom planar member. A heater layer can be disposed between the top and the bottom planar member and held in place by evacuating a region between the two planar members. The heater layer can be made of alternating insulating and conducting layers with heater elements formed on the conducting layers in predetermined pattern.Type: ApplicationFiled: June 25, 2010Publication date: January 6, 2011Applicant: Sokudo Co., Ltd.Inventor: Harald Herchen
-
Publication number: 20110000705Abstract: The present invention provides a display device substrate that enables microfabrication of lines and is capable of reducing faulty connection and enhancing the reliability of display devices including the display device substrate, a method for producing the display device substrate, a display device, a method for forming a multilayer wiring structure, and a multilayer wiring board. The display substrate of the present invention includes an insulating substrate and includes at least one of a terminal area having a connection terminal to be connected to an external connection component and a peripheral circuit region having a peripheral circuit formed thereon, on the insulating substrate. The display device substrate includes an organic insulating film and an inorganic insulating film, and the inorganic insulating film is stacked directly on and above the organic insulating film such that an organic-inorganic film stacked body is formed.Type: ApplicationFiled: October 29, 2008Publication date: January 6, 2011Inventor: Hiroyuki Moriwaki
-
Publication number: 20100245031Abstract: An electrical multilayer component has a stack of dielectric layers and electrode layers arranged one above another. Electrode layers of identical electrical polarity are jointly contacted to an external contact arranged at a side face of the stack. A resistor sintered to the stack and containing ceramic resistance material is arranged on an end face of the stack.Type: ApplicationFiled: March 26, 2010Publication date: September 30, 2010Inventors: Axel Pecina, Zeljko Maric
-
Patent number: 7785482Abstract: A method of manufacturing an ignition device is provided. The method includes patterning a plurality of resistors on a membrane to form heating elements and thermally isolating the heating elements from an external environment via a cavity disposed adjacent to the heating elements.Type: GrantFiled: December 7, 2005Date of Patent: August 31, 2010Assignee: General Electric CompanyInventors: Kanakasabapathi Subramanian, Richard Joseph Saia, Aaron Jay Knobloch, David Joseph Najewicz, Nicholas Okruch, Jr.
-
Patent number: 7765679Abstract: A mass flow sensor is manufactured by a process of carrying out a micro-machining process on an N or lightly doped P-type silicon substrate with orientation <100>. This mass flow sensor comprises a central thin-film heater and a pair of thin-film heat sensing elements, and a thermally isolated membrane for supporting the heater and the sensors out of contact with the substrate base. The mass flow sensor is arranged for integration on a same silicon substrate to form a one-dimensional or two-dimensional array in order to expand the dynamic measurement range. For each sensor, the thermally isolated membrane is formed by a process that includes a step of first depositing dielectric thin-film layers over the substrate and then performing a backside etching process on a bulk silicon with TMAH or KOH or carrying out a dry plasma etch until the bottom dielectric thin-film layer is exposed.Type: GrantFiled: September 19, 2006Date of Patent: August 3, 2010Assignee: Siargo, Inc.Inventors: Yahong Yao, Chih-Chang Chen, Gafeng Wang, Liji Huang
-
Patent number: 7759618Abstract: A strip-form silicon carbide furnace heating element is provided having a higher radiating surface area to volume ratio than a conventional tubular element.Type: GrantFiled: July 16, 2004Date of Patent: July 20, 2010Assignee: Sandvik Materials Technology UK LimitedInventor: John George Beatson
-
Publication number: 20100176825Abstract: A tactile sensor for curved surfaces applicable to objects with multi-dimensional curvature and a small radius of curvature and a manufacturing method thereof are disclosed. The tactile sensor for curved surfaces includes a lower pattern including a plurality of lower polymer film layers spaced at specified intervals in a lower direction, lower metal layers disposed on the lower polymer film layers, and a number of lower resistors disposed on the lower metal layers, an upper pattern including a plurality of upper polymer film layers spaced at specified intervals in a direction perpendicular to the lower direction, upper metal layers disposed on the upper polymer film layers, and a number of upper resistors disposed below the upper metal layers to be electrically connected to the lower resistors, and a lower polymer layer and an upper polymer layer to bond the lower pattern and the upper pattern to each other.Type: ApplicationFiled: May 25, 2007Publication date: July 15, 2010Applicant: KOREA RESEARCH INSTITUTE OF STANDARDS AND SCIENCEInventors: Jong-Ho Kim, Hyun-joon Kwon, Yon-kyu Park, Min-seok Kim, Dae-im Kang, Jae-hyuk Choi
-
Patent number: 7744768Abstract: A resist pattern thickening material has resin, a crosslinking agent and a compound having a cyclic structure, or resin having a cyclic structure at a part. A resist pattern has a surface layer on a resist pattern to be thickened with etching rate (nm/s) ratio of the resist pattern to be thickened the surface layer of 1.1 or more, under the same condition, or a surface layer to a resist pattern to be thickened. A process for forming a resist pattern includes applying the thickening material after forming a resist pattern to be thickened on its surface. A semiconductor device has a pattern formed by the resist pattern. A process for manufacturing the semiconductor device has applying, after forming a resist pattern to be thickened, the thickening material to the surface of the resist pattern to be thickened, and patterning the underlying layer by etching, the pattern as a mask.Type: GrantFiled: December 22, 2006Date of Patent: June 29, 2010Assignee: Fujitsu LimitedInventors: Miwa Kozawa, Koji Nozaki, Takahisa Namiki, Junichi Kon, Ei Yano
-
Patent number: 7645706Abstract: An electronic substrate manufacturing method includes: forming a wiring pattern on a substrate; providing a mask with an opening for the substrate on which the wiring pattern has been formed; performing a specified treatment in a part area of the wiring pattern through the opening of the mask. The opening has a size based on an accuracy of an alignment between the substrate and the mask.Type: GrantFiled: June 30, 2006Date of Patent: January 12, 2010Assignee: Seiko Epson CorporationInventor: Nobuaki Hashimoto
-
Publication number: 20090286186Abstract: A method of manufacturing a coordinate detector having a resistive film and a common electrode for applying a voltage to the resistive film is disclosed that includes the steps of (a) applying a photoresist onto the resistive film formed on a substrate formed of an insulator; (b) forming a resist pattern on the resistive film by exposing the applied photoresist to light through a predetermined mask and subsequently developing the applied photoresist; (c) forming a resistive film removal region by removing a portion of the resistive film without the resist pattern; (d) removing the resist pattern after step (c); and (e) forming the common electrode over the resistive film removal region after step (d).Type: ApplicationFiled: May 11, 2009Publication date: November 19, 2009Inventor: Koichi Kondoh
-
Patent number: 7603772Abstract: Substrate precursor structures include a substrate blank having at least one aperture extending substantially through the substrate blank. At least a portion of at least one conductive layer covers a surface of the at least one aperture of the substrate blank. A mask pattern covers a portion of the at least one conductive layer and exposes another portion of the at least one conductive layer to define at least one conductive element, at least a portion of which extends over the surface of the at least one aperture.Type: GrantFiled: March 13, 2007Date of Patent: October 20, 2009Assignee: Micron Technology, Inc.Inventors: Warren M. Farnworth, Steven M. McDonald, Nishant Sinha, William M. Hiatt
-
Publication number: 20090229857Abstract: An electrode for forming an electrochemical cell with a substrate and a method of forming said electrode. The electrode comprises a carrier (1) provided with an insulating layer (7) which is patterned at a front side. Conducting material in an electrode layer (4) is applied in the cavities of the patterned insulating layer and in contact with the carrier. An connection layer (5) is applied at the backside of the carrier and in contact with the carrier. The periphery of the electrode is covered by the insulating material.Type: ApplicationFiled: May 21, 2009Publication date: September 17, 2009Inventors: Mikael FREDENBERG, Patrik Moller, Peter Wiwen-Nilsson, Cecillia Aronsson, Matteo Dainese
-
Patent number: 7588657Abstract: In accordance with the invention, substrate-supported linear arrays are formed by the steps of adhering a thin layer of polymer between a pair of substrates and separating the substrates perpendicular to the layer. The polymer layer separates to form substrate-supported polymer gratings on both substrates, each grating having a period proportional to the thickness of the layer. The process has been used to make gratings with periods in the sub-micron range or larger over areas covering square centimeters.Type: GrantFiled: September 29, 2004Date of Patent: September 15, 2009Assignee: Princeton UniversityInventors: William B Russel, Stephen Y Chou, Leonard F Pease, III, Parikshit A Deshpande
-
Publication number: 20090213188Abstract: A method of manufacturing an actuator apparatus includes forming, on the base plate, a test pattern that is electrically discontinuous with the electrodes of the piezoelectric element and has the same layer as the lower electrode, the test pattern having the lower electrode with the upper electrode and the piezoelectric material layer removed by etching, and measuring electric resistance of the lower electrode of the test pattern to acquire the etch amount of the lower electrode when the piezoelectric element is formed.Type: ApplicationFiled: February 13, 2009Publication date: August 27, 2009Applicant: SEIKO EPSON CORPORATIONInventors: Masato Shimada, Kazushige Hakeda, Tsutomu Nishiwaki, Eiju Hirai
-
Publication number: 20090159558Abstract: A method of manufacturing an integrated circuit including a memory device that includes the following processes: forming a mask layer structure above a composite structure including a resistivity changing layer and an electrode layer disposed above the resistivity changing layer; partially patterning the mask layer structure using a first substance; stopping patterning the mask layer structure before exposing the top surface of the electrode layer; at least partially exposing the top surface of the electrode layer using a second substance, the second substance chemically not reacting with the electrode layer material.Type: ApplicationFiled: December 20, 2007Publication date: June 25, 2009Inventor: Stephane Cholet
-
Patent number: 7534361Abstract: The present invention relates to a circuit board including a flexible film provided with an extremely fine circuit pattern, a laminated member for a circuit board, and a method for making a laminated member for a circuit board with excellent productivity. A circuit board of the present invention includes a flexible film and a circuit pattern composed of a metal provided on the flexible film, and dimensional change rate of the circuit pattern is within ±0.01%. A laminated member for a circuit board of the present invention includes a reinforcing plate, a self-stick, removable organic layer, a flexible film, and a circuit pattern composed of a metal laminated in that order.Type: GrantFiled: June 26, 2006Date of Patent: May 19, 2009Assignee: Toray Industries, Inc.Inventors: Takayoshi Akamatsu, Futoshi Okuyama, Nobuyuki Kuroki, Hiroshi Enomoto, Tetsuya Hayashi, Yoshio Matsuda, Yoichi Shinba, Masahiro Oguni
-
Patent number: 7476328Abstract: A printed circuit board having prescribed conductive patterns formed on an insulating layer is provided about 20 mm apart from an AC electrode provided in a plasma etching device. An earth electrode is provided on the side opposing the AC electrode. More specifically, the printed circuit board is provided outside a sheath layer that is a region having a high plasma density generated in the vicinity of the AC electrode. The frequency of an AC power supply is preferably not more than 1 GHz. The pressure in the device is preferably in the range from 1.33×10?2 Pa to 1.33×102 Pa. The inter-electrode distance between the AC electrode and the earth electrode is preferably not more than 150 mm, more preferably from 40 mm to 100 mm.Type: GrantFiled: December 23, 2005Date of Patent: January 13, 2009Assignee: Nitto Denko CorporationInventor: Takashi Oda
-
Patent number: 7470544Abstract: Provided is a sensor array and a method of forming the same. The sensor array includes an array of apertures etched into a 3D patterned resist layer to expose areas of one or more agents and/or reagents deposited on a substrate. The sensor is formed using a Self-Aligned Imprint Lithography (“SAIL”) method, a process that allows for a one-time deposition of all required materials followed by a series of etching/cleaning steps. The location of reagents on the sensor template, as well as the concentration gradient of each reagent, may be controlled through the sensor manufacturing process. Bores of a single reagent, or bores containing two or more reagents, may be formed using the SAIL process.Type: GrantFiled: May 26, 2005Date of Patent: December 30, 2008Assignee: Hewlett-Packard Development Company, L.P.Inventor: Manish Sharma
-
Patent number: 7445726Abstract: A photoresist trimming process is described. An etcher equipped with an etching chamber, a wafer holder, a TCP source and a TCP window is provided. After plasma is generated in the etching chamber, the etching chamber is heated without a wafer therein, and the temperature at the TCP window is monitored simultaneously. It is started, at any time after the temperature at the TCP window reaches a predetermined one, to treat wafers with photoresist layers to be trimmed thereon through the etching chamber.Type: GrantFiled: September 5, 2005Date of Patent: November 4, 2008Assignee: United Microelectronics Corp.Inventors: Kevin C K Wang, Jiunn-Hsiung Liao
-
Publication number: 20080225088Abstract: A fluid jet device and a method for manufacturing the same are provided. The fluid jet device includes a substrate, a resistor layer and an orifice layer. The resistor layer is formed on the substrate. The resistor layer includes tantalum, silicon and nitrogen. The orifice layer is disposed on over the substrate to form a manifold between the orifice layer and the substrate. The manifold is used for containing a fluid. The orifice layer has a nozzle communicated with to the manifold. When the resistor layer is charged, the resistor layer heats the adjacent fluid to generate a bubble therein so as to allow the fluid to be pushed out of the nozzle.Type: ApplicationFiled: March 14, 2008Publication date: September 18, 2008Applicant: Qisda CorporationInventors: Chen-Kuei Chung, Yi-Zhi Hong
-
Publication number: 20080217048Abstract: A wired circuit board includes an insulating base layer, a conductive pattern formed on the insulating base layer and including a wire and a terminal portion, an insulating cover layer formed on the insulating base layer and having an opening portion to expose the terminal portion, and a metal thin film including a protecting portion interposed between the wire and the insulating cover layer, and an exposed portion formed continuously from the protecting portion on a peripheral end portion of the terminal portion exposed from the opening portion.Type: ApplicationFiled: March 3, 2008Publication date: September 11, 2008Applicant: Nitto Denko CorporationInventors: Katsutoshi Kamei, Takahiko Yokai, Visit Thaveeprungsriporn
-
Patent number: 7403095Abstract: A thin film resistor structure and a method of fabricating a thin film resistor structure is provided. The thin film resistor structure includes an electrical interface layer or head layer that is a combination of a Titanium (Ti) layer and a Titanium Nitride (TiN) layer. The combination of the Ti layer and the TiN layer mitigates resistance associated with the electrical interface layers.Type: GrantFiled: October 4, 2005Date of Patent: July 22, 2008Assignee: Texas Instruments IncorporatedInventors: Brian Vialpando, Eric William Beach, Philipp Steinmann
-
Publication number: 20080164236Abstract: An insulating layer made of an insulator film or the like is prepared. Then, a thin metal film and a thin copper film are formed in sequence on the insulating layer. The thin copper film is subsequently laminated with a dry film or the like, and exposed and developed to form a plating resist thereon that have patterns opposite to conductor patterns which are formed in a subsequent step. This is followed by forming conductor patterns made of copper, by electrolytic plating using an electrolytic copper sulfate plating solution, on the surfaces of the thin copper film where the plating resist is not formed. The plating resist is then removed by, for example, stripping. After this, the thin copper film is held at a temperature of not less than 200° C. and not more than 300° C. for approximately an hour to be thermally treated. Then, the thin copper film and the thin metal film are removed by chemical etching except the portions under the conductor patterns.Type: ApplicationFiled: December 13, 2007Publication date: July 10, 2008Applicant: NITTO DENKO CORPORATIONInventors: Kei NAKAMURA, Takeshi YAMATO