With Measuring, Testing, Or Inspecting Patents (Class 216/59)
  • Publication number: 20110132873
    Abstract: A distance between electrodes can be accurately measured by using a lifter. A substrate processing apparatus includes an upper electrode 120 and a lower electrode 310 facing each other within a processing chamber 102; a lift pin 332 that is protrusible from and retractable below the lower electrode and lifts up a substrate mounted on the lower electrode to be separated from the lower electrode; a lifter 330 that elevates the lift pin up and down; and a controller 400 that elevates the lift pin upward and brings the lift pin into contact with the upper electrode by driving the lifter while the substrate is not mounted on the lower electrode and measures a distance between the electrodes based on a moving distance of the lifter.
    Type: Application
    Filed: December 2, 2010
    Publication date: June 9, 2011
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Hiroshi Tsujimoto, Makoto Kobayashi, Jun Tamura, Nobuhiro Wada
  • Publication number: 20110108524
    Abstract: An arrangement for performing pressure control within a processing chamber substrate processing is provided. The arrangement includes a peripheral ring configured at least for surrounding a confined chamber volume that is configured for sustaining a plasma for etching the substrate during substrate processing. The peripheral ring includes a plurality of slots that is configured at least for exhausting processed byproduct gas from the confined chamber volume during substrate processing. The arrangement also includes a conductive control ring that is positioned next to the peripheral ring and is configured to include plurality of slots. The pressure control is achieved by moving the conductive control ring relative to the peripheral ring such that a first slot on the peripheral ring and a second slot on the conductive control ring are offset with respect to one another in a range of zero offset to full offset.
    Type: Application
    Filed: August 31, 2010
    Publication date: May 12, 2011
    Inventors: Rajinder Dhindsa, Michael C. Kellogg, Babak Kadkhodayan, Andrew D. Bailey, III
  • Patent number: 7922925
    Abstract: Substrates with a coating, in particular a metal-containing coating, are freed of coating in some regions, in particular in the edge region, with the aid of plasma directed onto the coated side of the substrate. The width of the region in which the coating is removed may be set such that plasma from a number of plasma heads arranged next to one another in a row or from one plasma head with variable cross section is directed onto the substrate in the desired width from which the coating is to be removed, wherein the plasma head or heads is/are suitably aligned with respect to the substrate and/or the required number of plasma heads in each case are set in operation. It is also possible to remove coatings only partially in terms of the layer thickness.
    Type: Grant
    Filed: June 16, 2004
    Date of Patent: April 12, 2011
    Assignee: Saint-Gobain Glass France
    Inventors: Helmut Forstner, Alfred Hofrichter
  • Publication number: 20110068085
    Abstract: A method of controlling wafer temperature in a plasma reactor by obtaining the next scheduled change in RF heat load on the workpiece, and using thermal modeling to estimate respective changes in wafer backside gas pressure and in coolant flow through a wafer support pedestal that would compensate for the next scheduled change in RF heat load, and making the respective changes in the backside gas pressure or in the coolant flow prior to the time of the next scheduled change.
    Type: Application
    Filed: November 24, 2010
    Publication date: March 24, 2011
    Inventors: Paul Lukas Brillhart, Richard Fovell, Douglas A. Buchberger, JR., Douglas H. Burns, Kallol Bera, Daniel J. Hoffman
  • Patent number: 7910013
    Abstract: For each one of plural plasma parameters, such as ion density, wafer voltage, etch rate, wafer current, a relevant surface of constant value is fetched from a memory. The relevant surface of constant value corresponds to a user-selected value of one of the plasma parameters, the surface being defined in a space of which each one of plural, chamber parameters (e.g., source power, bias power and chamber pressure) is a dimension. An intersection of these relevant surfaces is found, the intersection corresponding to a target value of source power, bias power and chamber pressure. The source power, the bias power and the chamber pressure, respectively, are set to their corresponding target values.
    Type: Grant
    Filed: December 11, 2006
    Date of Patent: March 22, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Daniel J. Hoffman, Ezra Robert Gold
  • Publication number: 20110056912
    Abstract: Uniformity in a plasma process can be increased by increasing a plasma confining effect by a cusp magnetic field over the whole circumference. There is provided a plasma processing apparatus which performs a process on a substrate by generating plasma of a processing gas in a depressurized processing chamber. The apparatus includes a magnetic field generation unit 200 including two magnet rings 210 and 220 vertically spaced from each other and arranged along a circumferential direction of the processing chamber. Each of the magnet rings includes multiple segments 212 and 222 of which magnetic poles are alternately reversed two by two along a circumferential direction of an inner surface of the magnet ring. In the magnetic field generation unit 200, arrangement of upper and lower magnetic poles is changed by rotating the lower magnet ring 220 in a circumferential direction with respect to the upper magnet ring 210.
    Type: Application
    Filed: September 3, 2010
    Publication date: March 10, 2011
    Applicant: TOKYO ELECTRON LIMITED
    Inventor: Shoichiro Matsuyama
  • Patent number: 7901952
    Abstract: The invention concerns a method of processing a wafer in a plasma reactor chamber by controlling plural chamber parameters in accordance with desired values of plural plasma parameters. The method includes concurrently translating a set of M desired values for M plasma parameters to a set of N values for respective N chamber parameters. The M plasma parameters are selected from a group including wafer voltage, ion density, etch rate, wafer current, etch selectivity, ion energy and ion mass. The N chamber parameters are selected from a group including source power, bias power, chamber pressure, inner magnet coil current, outer magnet coil current, inner zone gas flow rate, outer zone gas flow rate, inner zone gas composition, outer zone gas composition. The method further includes setting the N chamber parameters to the set of N values.
    Type: Grant
    Filed: December 11, 2006
    Date of Patent: March 8, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Daniel J. Hoffman, Ezra Robert Gold
  • Publication number: 20110049098
    Abstract: In a plasma etching method of performing a plasma etching on an amorphous carbon layer of a substrate to be processed by using an inorganic film as a mask, the substrate being mounted in a processing chamber, the plasma etching on the amorphous carbon layer is performed by using O2 gas as a processing gas and the O2 gas to flow in the processing chamber such that a residence time of the O2 gas becomes 0.37 msec or less. The amorphous carbon layer is used as an etching mask of an etching target film formed on the substrate. The plasma etching is performed by using the O2 gas only.
    Type: Application
    Filed: August 23, 2010
    Publication date: March 3, 2011
    Applicant: TOKYO ELECTRON LIMITED
    Inventor: Kousuke KOIWA
  • Patent number: 7897058
    Abstract: A method of forming features, e.g. contact holes, at a higher density than is possible with conventional lithographic techniques involves forming an array of sacrificial positive features, conformally depositing a sacrificial layer so that negative features are formed interleaved with the positive features, directionally etching the sacrificial layer and removing the sacrificial features. The result is an array of holes at a higher density than the original sacrificial features. These may then be transferred into the underlying substrate using a desired process. Also, the method may be repeated to create arrays at even higher densities.
    Type: Grant
    Filed: May 17, 2006
    Date of Patent: March 1, 2011
    Assignees: ASML Netherlands B.V., ASML Holding NV
    Inventors: Richard Johannes Franciscus Van Haren, Maurits Van Der Schaar, Ewoud Vreugdenhil, Harry Sewell
  • Patent number: 7892444
    Abstract: A method for controlling a plasma processing apparatus which includes a vacuum vessel, a first, second and third RF power supply, a first and second electrode, and a phase control unit for controlling a phase difference between a second RF voltage from the second RF power supply and a third RF voltage from the third RF power supply. The controlling method includes the steps of supplying a predetermined power from the first RF power supply to ignite plasma, after confirming ignition of plasma, supplying a predetermined power respectively from the second RF power supply and the third RF power supply, and when starting power supply from the second RF power supply and the third RF power supply, fixing the phase to a predetermined phase angle using a preset mode without carrying out phase control, and after a matching operation has stabilized, starting the phase control.
    Type: Grant
    Filed: April 4, 2007
    Date of Patent: February 22, 2011
    Assignee: Hitachi High-Technologies Corporation
    Inventor: Ryoji Nishio
  • Patent number: 7892442
    Abstract: A method of manufacturing a thin-film magnetic head works a part to be worked to a target length by carrying out an etching process on an object to be worked using an etching apparatus.
    Type: Grant
    Filed: March 8, 2007
    Date of Patent: February 22, 2011
    Assignee: TDK Corporation
    Inventors: Hiroo Sawada, Jun Shouji, Mitsuhiro Kitao, Eiji Yamada
  • Patent number: 7892980
    Abstract: The present invention provides apparatus for controlling the operation of plasma etching a semiconductor substrate by an alternating etching method, the apparatus comprising: a process chamber (1) in which said substrate (2) is processed, means for generating a plasma (6); at least one first window (7) formed in a first wall (8) of said chamber (1) facing the surface (2a) to be etched of said substrate (2); at least one second window (10) formed in a second wall (11) of said chamber (1) lying in a plane different from said first wall (8); first means (18) coupled to said second window (10) to detect a light signal (17) relating to a selected wavelength emitted by said plasma (6); means (13, 15) for emitting a monochromatic light signal (14) through said first window (7) towards said surface (2a) in a direction (9) substantially perpendicular to said surface (2a) in such a manner that said incident signal (14a) is reflected on said surface (2a); second means (16) for detecting said reflected signal (14b); a
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: February 22, 2011
    Inventors: Michel Puech, Nicolas Launay
  • Publication number: 20110031214
    Abstract: A method and apparatus for vacuum processing of a workpiece, the apparatus including a flow equalizer disposed in a vacuum processing chamber between a workpiece support pedestal and a pump port located in a wall of the vacuum processing chamber. In an embodiment, the flow equalizer has a first annular surface concentric about the workpiece support pedestal to provide conductance symmetry about the workpiece support even when the pump port is asymmetrically positioned within the vacuum processing chamber. In an embodiment, the flow equalizer has a second annular surface facing a lower surface of the workpiece support pedestal to restrict conductance as the flow equalizer is moved is response to a chamber pressure control signal. In an embodiment, the apparatus for vacuum processing of a workpiece includes tandem vacuum processing chambers sharing a vacuum pump with each tandem chamber including a flow equalizer to reduce cross-talk between the tandem chambers.
    Type: Application
    Filed: August 6, 2009
    Publication date: February 10, 2011
    Inventors: Jisoo Kim, Thorsten B. Lill
  • Patent number: 7883629
    Abstract: During the patterning of stressed layers having different types of intrinsic stress, the effects of the deposition of a silicon dioxide based etch indicator material between the first and second dielectric layers may be significantly reduced by a controlled etch on the basis of optical measurement data indicating the etch rate and, thus, the performance of the respective etch process. In other cases, highly efficient etch indicator species may be incorporated into the stressed dielectric layers or may be formed on a surface portion thereof with reduced layer thickness, thereby providing an enhanced endpoint detection signal without creating the negative effects of silicon dioxide based indicator layers. In one illustrative embodiment, a stressed silicon, nitrogen and carbon-containing layer may be combined with a stressed silicon and nitrogen-containing layer, wherein the carbon species provides a prominent endpoint detection signal.
    Type: Grant
    Filed: October 8, 2007
    Date of Patent: February 8, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Matthias Schaller, Heike Salz, Ralf Richter, Sylvio Mattick
  • Patent number: 7883630
    Abstract: Apparatus and processes are disclosed for milling copper adjacent to organic low-k dielectric on a substrate by directing a charged-particle beam at a portion of the copper and exposing the copper to a precursor sufficient to enhance removal of the copper relative to removal of the dielectric, wherein the precursor contains an oxidizing agent, has a high sticking coefficient and a long residence time on the copper, contains atoms of at least one of carbon and silicon in amount sufficient to stop oxidation of the dielectric, and contains no atoms of chlorine, bromine or iodine. In one embodiment, the precursor comprises at least one of the group consisting of NitroEthanol, NitroEthane, NitroPropane, NitroMethane, compounds based on silazane such as HexaMethylCycloTriSilazane, and compounds based on siloxane such as Octa-Methyl-Cyclo-Tetra-Siloxane. Products of the processes are also disclosed.
    Type: Grant
    Filed: September 26, 2008
    Date of Patent: February 8, 2011
    Assignee: DCG Systems, Inc.
    Inventors: Vladimir V. Makarov, Theodore R. Lundquist
  • Patent number: 7875198
    Abstract: A method of deriving etching correction values for the patterns of a photomask and a method of fabricating a photomask are described. The former method includes the following steps. The layout data of the photomask are provided, and local etching correction values of respective patterns are determined from the pattern configurations at respective areas of the photomask. A global etching correction value is determined from a wafer coverage ratio calculated mainly from the layout data. The local etching correction values of the respective patterns are added with the global etching correction value to obtain total etching correction values of the respective patterns. In the method of fabricating a photomask, the layout data are subjected to an etching correction based on the total etching correction values of the respective patterns and then to an optical proximity correction, and the photomask patterns are formed based on the resulting layout data.
    Type: Grant
    Filed: November 6, 2006
    Date of Patent: January 25, 2011
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Chao-Lung Lo, Sunwook Jung
  • Patent number: 7877161
    Abstract: A processing system and method for chemical oxide removal (COR) is presented, wherein the processing system comprises a first treatment chamber and a second treatment chamber, wherein the first and second treatment chambers are coupled to one another. The first treatment chamber comprises a chemical treatment chamber that provides a temperature controlled chamber, and an independently temperature controlled substrate holder for supporting a substrate for chemical treatment. The substrate is exposed to a gaseous chemistry, such as HF/NH3, under controlled conditions including surface temperature and gas pressure. The second treatment chamber comprises a heat treatment chamber that provides a temperature controlled chamber, thermally insulated from the chemical treatment chamber. The heat treatment chamber provides a substrate holder for controlling the temperature of the substrate to thermally process the chemically treated surfaces on the substrate.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: January 25, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Masayuki Tomoyasu, Merritt Lane Funk, Kevin Augustine Pinto, Masaya Odagiri, Lemuel Chen, Asao Yamashita, Akira Iwami, Hiroyuki Takahashi
  • Patent number: 7871830
    Abstract: A method for controlling the plasma etching of semiconductor wafers determines the impedance of a plasma chamber using values representing voltage, current, and the phase angle between them, as provided by a sensor. All or less than all of the data during a first time period may be used to calculate a model. During a second time period, real time data is used to calculate a version of the instant impedance of the chamber. This version of impendence is compared to a time-projected version of the model. The method determines that etching should be stopped when the received data deviates from the extrapolated model by a certain amount. In some embodiments a rolling average is used in the second time period, the rolling average compared to the model to determine the end point condition.
    Type: Grant
    Filed: January 18, 2006
    Date of Patent: January 18, 2011
    Assignee: Pivotal Systems Corporation
    Inventors: Sumer S. Johal, Barton Lane, Georges J. Gorin, Sylvia G. J. P. Spruytte, Herve C. Kieffel
  • Patent number: 7867409
    Abstract: A manufacturing method and apparatus for IC fabrication controls the ion angular distribution at the surface of a wafer with electrodes in a wafer support that produce electric fields parallel to the wafer surface without disturbing plasma parameters beyond the wafer surface. The ion angular distribution function (IADF) at the wafer surface is controlled for better feature coverage or etching. Grid structure is built into the substrate holder within the coating at the top of the holder. The grid components are electrically biased to provide electric fields that combine with the sheath field to distribute the ion incidence angles from the plasma sheath onto the wafer. The grid can be dynamically biased or phased to control uniformity of the effects.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: January 11, 2011
    Assignee: Tokyo Electron Limited
    Inventor: Jozef Brcka
  • Publication number: 20100320170
    Abstract: A plasma processing apparatus includes a plasma reaction chamber in which a plasma is generated for processing. First and second electrodes are located in the chamber for generating the plasma. First and second RF power sources provide RF power to the first and second electrodes, respectively. The apparatus also includes first and second impedance matching circuits through which the RF power is respectively provided from the first and second RF power supplies to the first and second electrodes. A first plasma controller monitors plasma density and, in response thereto, adjusts the RF power supplied by the first RF power source to the first electrode to achieve a given plasma density. A second plasma controller monitors the ion energy of plasma species impinging on a semiconductor structure associated with the second electrode and, in response thereto, adjusts the RF power supplied by the second RF power source to the second electrode to achieve a given ion energy.
    Type: Application
    Filed: August 25, 2010
    Publication date: December 23, 2010
    Applicants: SONY CORPORATION, SONY ELECTRONICS INC.
    Inventor: Seiji Iseda
  • Publication number: 20100314354
    Abstract: Methods and apparatus may operate to position a sample within a processing chamber and operate on a surface of the sample. Further activities may include creating a layer of reactive material in proximity with the surface, and exciting a portion of the layer of reactive material in proximity with the surface to form chemical radicals. Additional activities may include removing a portion of the material in proximity to the excited portion of the surface to a predetermined level, and continuing the creating, exciting and removing actions until at least one of a plurality of stop criteria occurs.
    Type: Application
    Filed: August 23, 2010
    Publication date: December 16, 2010
    Inventors: Neal R. Rueger, Mark J. Williamson, Gurtej S. Sandhu, Justin R. Arrington
  • Patent number: 7848898
    Abstract: Methods for monitoring process drift using plasma characteristics are provided. In one embodiment, a method for monitoring process drift using plasma characteristics includes obtaining metrics of current and voltage information of a first waveform coupled to a plasma during a plasma process formed on a substrate, obtaining metrics of current and voltage information of a second waveform coupled to the plasma during the plasma process formed on the substrate, the first and second waveforms having different frequencies, determining at least one characteristic of the plasma using the metrics obtained from each different frequency waveform, and adjusting the plasma process in response to the determined at least one characteristic of the plasma.
    Type: Grant
    Filed: January 16, 2009
    Date of Patent: December 7, 2010
    Assignee: Applied Materials Inc.
    Inventors: Steven C. Shannon, Daniel J. Hoffman, Jeremiah T. P. Pender, Tarreg Mawari
  • Patent number: 7842189
    Abstract: A processing apparatus includes counters each used to measure the length of RF discharge time over which power is applied to a consumable component in correspondence to a specific type of processing executed in a processing chamber, a storage to store wear coefficient information indicating wear coefficients each corresponding to one of the plurality of types of processing, and a control unit that obtains information indicating RF discharge time lengths measured by the counters in correspondence to the individual types of processing, obtains the wear coefficients corresponding to the individual types of processing indicated in the wear coefficient information stored in the storage, calculates a wear index value for the consumable component based upon the RF discharge time lengths and the wear coefficients corresponding to the individual types of processing, and executes consumable component management processing based upon the calculated wear index value.
    Type: Grant
    Filed: January 19, 2006
    Date of Patent: November 30, 2010
    Assignee: Tokyo Electron Limited
    Inventor: Ryotaro Midorikawa
  • Patent number: 7833427
    Abstract: Methods and devices for selective etching in a semiconductor process are shown. Chemical species generated in a reaction chamber provide both a selective etching function and concurrently form a protective coating on other regions. An electron beam provides activation to selective chemical species. In one example, reactive species are generated from a halogen and carbon containing gas source. Addition of other gasses to the system can provide functions such as controlling a chemistry in a protective layer during a processing operation.
    Type: Grant
    Filed: August 14, 2006
    Date of Patent: November 16, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Neal R. Rueger, Mark J. Williamson, Gurtej S. Sandhu
  • Patent number: 7833388
    Abstract: A method for manufacturing a magnetic layer with a magnetic anisotropy. The method includes an endpoint detection process for determining an end point to carefully control the final thickness of the magnetic layer. The method includes depositing a magnetic layer and then depositing a sacrificial layer over the magnetic layer. A low power angled ion milling is then performed until the magnetic layer has been reached. The angled ion milling can be performed at an angle relative to normal and without rotation in order to form an anisotropic surface texture that induces a magnetic anisotropy in the magnetic layer. An indicator layer may be included between the magnetic layer and the sacrificial layer in order to further improve endpoint detection.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: November 16, 2010
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Matthew Joseph Carey, Jeffrey Robinson Childress, Stefan Maat
  • Patent number: 7829468
    Abstract: A method of fault detection for use in a plasma processing chamber is provided. The method comprises monitoring plasma parameters within a plasma chamber with a single planar ion flux (PIF) probe, analyzing the resulting information, measuring the plasma parameters as a function of time and analyzing the resulting data. The data can be observed, characterized, compared with reference data, digitized, processed, or analyzed to reveal a specific fault. The PIF probe is preferably positioned at a grounded surface within the reactor. Chamber faults that can be detected include a build-up of process by-products in the process chamber, a helium leak, a match re-tuning event, a poor stabilization rate, and a loss of plasma confinement.
    Type: Grant
    Filed: June 7, 2006
    Date of Patent: November 9, 2010
    Assignee: Lam Research Corporation
    Inventors: Douglas Keil, Eric Hudson, Chris Kimball, Andreas Fischer
  • Patent number: 7815812
    Abstract: A method for controlling a process for fabricating integrated devices on a substrate. The method includes ex-situ and in-situ measurements of pre-etch and post-etch dimensions for structures formed on the substrate and uses the results of the measurements to adjust process recipes and to control the operational status of etch and external substrate processing equipment. In one exemplary application, the method is used during a multi-pass process for fabricating a capacitive structure of a trench capacitor.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: October 19, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Matthew F. Davis, Lei Lian, Barbara Schmidt
  • Patent number: 7815813
    Abstract: An end point detection method in the case where a catalyst arranged in a treatment chamber of a gas phase reaction processing apparatus is heated at high temperature by supplying electric power thereto and the treatment is carried out by cracking a reaction gas by the catalyst heated at high temperature, comprises the steps of supplying the electric power to the catalyst from a constant current source, detecting electric potential difference between both ends of the catalyst, performing primary differentiation of the detected electric potential difference, and determining an end point of the treatment based on obtained primary differential value.
    Type: Grant
    Filed: August 22, 2006
    Date of Patent: October 19, 2010
    Assignees: Tokyo Ohka Kogyo Co., Ltd., Japan Advanced Institute of Science and Technology
    Inventors: Kazuhisa Takao, Hiroshi Ikeda, Hideki Matsumura, Atsushi Masuda, Hironobu Umemoto
  • Publication number: 20100258233
    Abstract: Disclosed is a ceramic substrate including silicon in which the concentration of a silicon oxide and a silicon composite oxide in the surface thereof is less than or equal to 2.7 Atom %.
    Type: Application
    Filed: November 6, 2008
    Publication date: October 14, 2010
    Applicant: Mitsubishi Materials Corporation
    Inventors: Hiroshi Tonomura, Takeshi Kitahara, Hiroya Ishizuka, Yoshirou Kuromitsu, Yoshiyuki Nagatomo
  • Patent number: 7803280
    Abstract: The invention provides a method in which waviness generated on a glass substrate surface during pre-polishing is removed, thereby finishing the glass substrate to have a surface excellent in flatness. The method for finishing a pre-polished glass substrate uses ion beam etching, gas cluster ion beam etching or plasma etching, the method including: a step of measuring flatness of the glass substrate surface using a shape measurement unit, and a step of measuring a concentration distribution of the dopant contained in the glass substrate. Processing conditions of the glass substrate surface are set up for each site of the glass substrate based on the results obtained from the step of measuring flatness and the step of measuring a concentration distribution of the dopant. Finishing includes keeping an angle formed by a normal line of the glass substrate and an incident beam onto the glass substrate at from 30° to 89°.
    Type: Grant
    Filed: June 1, 2009
    Date of Patent: September 28, 2010
    Assignee: Asahi Glass Company, Limited
    Inventors: Koji Otsuka, Kenji Okamura
  • Patent number: 7794616
    Abstract: An etching gas for etching an oxide film formed on a substrate, includes a main gas composed of an unsaturated fluorocarbon-based gas; and an additive gas composed of a straight-chain saturated fluorocarbon-based gas expressed by CXF(2X+2) (x represents a natural number of 5 or larger). The additive gas is C5F12 gas, C6F14 gas or C7F16 gas. Another etching gas includes a main gas composed of an unsaturated fluorocarbon-based gas; and an additive gas composed of a cyclic saturated fluorocarbon-based gas expressed by CXF2X (X represents a natural number of 5 or larger). In this case, the additive gas is C5F10 gas or C6F12 gas.
    Type: Grant
    Filed: August 9, 2005
    Date of Patent: September 14, 2010
    Assignee: Tokyo Electron Limited
    Inventors: Masanobu Honda, Akinori Kitamura, Kazuya Nagaseki
  • Patent number: 7794615
    Abstract: A plasma processing apparatus includes an upper matching unit 44 which is a variable matching unit whose impedance can be varied, and a main controller 100. The upper matching unit 44 includes a controller 104 for variably controlling the impedance positions of a variable reactance element of a matching circuit 102, a RF sensor for measuring a load impedance including the matching circuit 102, and a VPP measuring circuit 112 for measuring a peak value (peak-to-peak value) of a radio frequency voltage in a waveguide line at the output side of the upper matching unit 44. The main controller 100 executes and controls an autorunning of the matching units 44, 88 for optimizing an off preset of the impedance positions thereof. The plasma can be readily get ignited without requiring to set or change special processing conditions while influencing none of the processes.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: September 14, 2010
    Assignee: Tokyo Electron Limited
    Inventor: Hiroshi Ogawa
  • Patent number: 7785486
    Abstract: Additional variants of the method of etching structures into an etching body, in particular recesses in a silicon body that are laterally defined in a precise manner by an etching mask, using a plasma, is described. In addition, the use of this method in the introduction of structures, in particular trenches having a high aspect ratio, into a dielectric layer or a dielectric base body and in a layer of silicon is described, isotropic underetching and/or isotropic, sacrificial-layer etching, in particular using fluorine radicals or a highly oxidizing fluorine compound such as ClF3, being performed after the production of the structures in at least some areas in the case of the layer made of silicon.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: August 31, 2010
    Assignee: Robert Bosch GmbH
    Inventors: Andrea Urban, Franz Laermer, Klaus Breitschwerdt, Volker Becker
  • Patent number: 7780864
    Abstract: A method of processing a workpiece in the chamber of a plasma reactor in which the plasma ion density radial distribution in the process region is controlled by adjusting the ratio between the amounts of the (VHF) capacitively coupled power and the inductively coupled power while continuing to maintain the level of total plasma source power. The method can also include applying independently adjustable LF bias power and HF bias power to the workpiece and adjusting the average value and population distribution of ion energy at the surface of the workpiece by adjusting the proportion between the LF and HF bias powers.
    Type: Grant
    Filed: April 24, 2006
    Date of Patent: August 24, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Alexander Paterson, Valentin N. Todorow, Theodoros Panagopoulos, Brian K. Hatcher, Dan Katz, Edward P. Hammond, IV, John P. Holland, Alexander Matyushkin
  • Patent number: 7776226
    Abstract: A multi-chamber system of an etching facility for manufacturing semiconductor devices occupies a minimum amount of floor space in a clean room by installing a plurality of processing chambers in multi-layers and in parallel along a transfer path situated between the processing chambers. The multi-layers number 2 to 5, and the transfer path can be rectangular in shape and need only be slightly wider than the diameter of a wafer. The total width of the multi-chamber system is the sum of the width of one processing chamber plus the width of the transfer path.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: August 17, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Sang Kim, Gyu-Chan Jeoung, Gyu-hwan Kwag
  • Patent number: 7771604
    Abstract: A combined wide-image and loop-cutter pattern is provided for both cutting and forming a wide-image section to a hard mask on a substrate formed by sidewall imaging techniques in a reduced number of photolithographic steps. A single mask is formed which provides a wide mask section while additionally providing a mask to protect the critical edges of an underlying hard mask during hard mask etching. After the hard mask is cut into sections, the protective portions of the follow-on mask are removed to expose the critical edges of the underlying hard mask while maintaining shapes necessary for defining wide-image sections. Thus, the hard mask cutting, hard mask critical edge protecting, and large area mask may be formed in a reduced number of steps.
    Type: Grant
    Filed: October 4, 2004
    Date of Patent: August 10, 2010
    Assignee: International Business Machines Corporation
    Inventors: Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak, Charles W. Koburger, III
  • Patent number: 7771603
    Abstract: A process for polishing a glass substrate, which enables to polish a glass substrate having a large waviness formed by mechanical polishing, to have a surface excellent in flatness, is provided. A process for polishing a glass substrate, comprising a step of measuring the surface profile of a mechanically polished glass substrate to identify the width of waviness present in the glass substrate, and a step of applying dry etching using a beam having a beam size in FWHM (full width of half maximum) value of at most the above size of waviness, to polish the surface of the glass substrate.
    Type: Grant
    Filed: July 18, 2007
    Date of Patent: August 10, 2010
    Assignee: Asahi Glass Company, Limited
    Inventors: Koji Otsuka, Masabumi Ito, Hiroshi Kojima
  • Patent number: 7767104
    Abstract: A fabrication method in thin layers, for example of integrated electronic circuits or MEMS. A correction method allows design errors made for example by photolithography in a thin layer to be repaired, and without necessarily having to utilize a new mask or without having to correct an erroneous mask. A lithography device allows certain of operations of such a method to be employed.
    Type: Grant
    Filed: December 15, 2004
    Date of Patent: August 3, 2010
    Assignee: Commissariat a l'Energie Atomique
    Inventor: Laurent Pain
  • Patent number: 7764377
    Abstract: Methods and apparatus for spectrum-based endpointing. An endpointing method includes selecting a reference spectrum. The reference spectrum is a spectrum of white light reflected from a film of interest on a first substrate and has a thickness greater than a target thickness. The reference spectrum is empirically selected for particular spectrum-based endpoint determination logic so that the target thickness is achieved when endpoint is called by applying the particular spectrum-based endpoint logic. The method includes obtaining a current spectrum. The current spectrum is a spectrum of white light reflected from a film of interest on a second substrate when the film of interest is being subjected to a polishing step and has a current thickness that is greater than the target thickness. The method includes determining, for the second substrate, when an endpoint of the polishing step has been achieved. The determining is based on the reference and current spectra.
    Type: Grant
    Filed: August 26, 2005
    Date of Patent: July 27, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Dominic J. Benvegnu, Jeffrey Drue David, Bogdan Swedek
  • Patent number: 7758763
    Abstract: A substrate comprising a resist layer overlying a dielectric feature, is processed in a substrate processing chamber comprising an antenna, and first and second process electrodes. A process gas comprising CO2 is introduced into the chamber. The process gas is energized to form a plasma by applying a source voltage to the antenna, and by applying to the electrodes, a first bias voltage having a first frequency of at least about 10 MHz and a second bias voltage having a second frequency of less than about 4 MHz. The ratio of the power level of the first bias voltage to the second bias voltage is sufficient to obtain an edge facet height of the underlying dielectric feature that is at least about 10% of the height of the dielectric feature.
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: July 20, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Yifeng Zhou, Siyi Li, Terry Leung, Michael D. Armacost
  • Patent number: 7749398
    Abstract: Calibration wafers and methods for calibrating a plasma process performed in a plasma processing apparatus, such as an ionized physical vapor deposition apparatus. The calibration wafer includes one or more selective-redeposition sources that may be used for calibrating a plasma process. The selective-redeposition sources are constructed to promote the redeposition of a controllable and/or measurable amount of material during the plasma process.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: July 6, 2010
    Assignee: Tokyo Electron Limited
    Inventors: Jozef Brcka, Rodney L. Robison, Takashi Horiuchi
  • Patent number: 7744770
    Abstract: A device transfer method is provided. The device transfer method is disclosed by which, when a laser ablation technique is used to selectively exfoliate devices arranged on a substrate, the energy is transmitted efficiently to transfer the devices with a high degree of accuracy and at a high speed. A laser irradiation apparatus is used which includes a laser light source for generating a laser beam, a reflection section for reflecting the laser beam toward a required direction, and a control section for controlling whether or not the laser beam is to be irradiated in an interlocking relationship with the reflection section. The laser beam is selectively irradiated on a plurality of devices arranged on a transfer source substrate to cause laser ablation such that the selected devices are transferred to a transfer destination substrate by the selective laser ablation.
    Type: Grant
    Filed: June 22, 2005
    Date of Patent: June 29, 2010
    Assignee: Sony Corporation
    Inventors: Masato Doi, Toyoharu Oohata
  • Patent number: 7741221
    Abstract: A method for forming a semiconductor device includes providing a plurality of features in a layout, selecting critical features from the plurality of features, placing a first plurality of short-range dummy etch features in the layout at a first distance from the critical features to increase the feature density near the critical features, wherein each of the first plurality of short-range dummy etch features has a first width, removing at least one of the first plurality of short-range dummy etch features from the layout that will subsequently interfere with the electrical performance of at least one active feature so that a second plurality of short-range dummy etch features remains, and using the layout to pattern a layer on a semiconductor substrate.
    Type: Grant
    Filed: December 14, 2005
    Date of Patent: June 22, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ruiqi Tian, Willard E. Conley, Mehul D. Shroff
  • Patent number: 7728253
    Abstract: A system and method employing a microplasma to electrically charge nano- or micro-particles in a gas phase and, subsequently, trap the charged particles within the microplasma using the microplasma's built-in electric fields are disclosed. Confinement of the particles allows their density to be increased over time such that very low concentrations of particles can be detected, e.g., by methods such as laser scattering and/or detection of the plasma-induced charge on the particles. Preferably, charge detection methods are employed when nano-particles are to be trapped and detected.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: June 1, 2010
    Assignee: Northeastern University
    Inventor: Jeffrey A. Hopwood
  • Patent number: 7727413
    Abstract: A method of processing a workpiece in the chamber of a plasma reactor includes introducing a process gas into the chamber, simultaneously (a) capacitively coupling VHF plasma source power into a process region of the chamber that overlies the wafer, and (b) inductively coupling RF plasma source power into the process region, and controlling plasma ion density by controlling the effective frequency of the VHF source power. In a preferred embodiment, the step of coupling VHF source power is performed by coupling VHF source power from different generators having different VHF frequencies, and the step of controlling the effective frequency is performed by controlling the ratio of power coupled by the different generators.
    Type: Grant
    Filed: April 24, 2006
    Date of Patent: June 1, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Alexander Paterson, Valentin N. Todorow, Theodoros Panagopoulos, Brian K. Hatcher, Dan Katz, Edward P. Hammond, IV, John P. Holland, Alexander Matyushkin
  • Publication number: 20100126963
    Abstract: In a system and method of etching a sample disposed in an etching chamber, a plurality of separately stored charges of an etching gas is discharged, one at a time, into a sample etching chamber. The discharge of each charge of etching gas occurs such that a momentary overlap exists in the end discharge of one charge of etching gas with the beginning discharge of another charge of etching gas, whereupon the desired flow of etching gas into the etching chamber is maintained. During discharge of one charge of etching gas, a previously discharged charge of etching gas is recharged. The process of discharging a plurality of separately stored charges of an etching gas, one at a time, and recharging at least one previously discharged charges of etching gas during the discharge of at least one charge of etching gas continues until the sample is etched to a desired extent.
    Type: Application
    Filed: November 30, 2006
    Publication date: May 27, 2010
    Applicant: XACTIX, INC.
    Inventors: Kyle S. Lebouitz, David L. Springer
  • Patent number: 7722778
    Abstract: Universal plasma unconfinement detection systems configured to detect the plasma unconfinement condition in the plasma processing chamber and methods therefor. The detection systems and methods are designed to reliably and accurately detect the existence of the plasma unconfinement condition in a process-independent and recipe-independent manner.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: May 25, 2010
    Assignee: Lam Research Corporation
    Inventors: Andreas Fischer, David Pirkle
  • Patent number: 7718080
    Abstract: Methods and devices for selective etching in a semiconductor process are shown. Chemical species generated in a reaction chamber provide both a selective etching function and concurrently form a protective coating on other regions. An electron beam provides activation to selective chemical species. In one example, reactive species are generated from a plasma source to provide an increased reactive species density. Addition of other gasses to the system can provide functions such as controlling a chemistry in a protective layer during a processing operation. In one example an electron beam array such as a carbon nanotube array is used to selectively expose a surface during a processing operation.
    Type: Grant
    Filed: August 14, 2006
    Date of Patent: May 18, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Neal R. Rueger, Mark J. Williamson, Gurtej S. Sandhu
  • Patent number: 7713430
    Abstract: Apparatus, systems and methods for plasma etching substrates are provided. The invention achieves dissipation of charge build-up on a substrate being plasma etched to avoid notching or twisting in high aspect ratio contents and similar features. Charge build-up on a substrate being etched by plasma etching can be dissipated by a method for etching a substrate, the method comprising: providing a plasma processing chamber comprising a chamber enclosure and a substrate support adapted to support a substrate within the chamber enclosure; supporting a substrate on the substrate support; forming a plasma within the chamber enclosure such that a surface of the substrate is in contact with the plasma; etching the substrate by generating a negative bias on the substrate surface relative to the plasma; and intermittently changing the bias on the substrate surface to positive relative to the plasma. The present method can be readily integrated into known plasma processing systems.
    Type: Grant
    Filed: February 23, 2006
    Date of Patent: May 11, 2010
    Assignee: Micron Technology, Inc.
    Inventor: Aaron R. Wilson
  • Patent number: 7713432
    Abstract: The present invention provides a method and an apparatus for improving the etch uniformity across a substrate during a plasma etch process that employs the use of an inductively coupled plasma helical inductor. The plasma apparatus comprising a vacuum chamber, a support member in the vacuum chamber for holding the substrate, an etchant gas supply for providing an etchant gas to the vacuum chamber, an exhaust in fluid communication with the vacuum chamber, an RF power source and a helical inductor disposed around or near a portion of the vacuum chamber. A sensor is provided for measuring a process attribute to generate a signal to a controller that then controls a mechanism that varies the position of the helical inductor so that the uniformity of the plasma etch is improved.
    Type: Grant
    Filed: September 16, 2005
    Date of Patent: May 11, 2010
    Inventors: David Johnson, Russell Westerman