Of Electrical Device (e.g., Semiconductor) Patents (Class 228/179.1)
  • Patent number: 6728106
    Abstract: A heat dissipation structure of an IC includes a circuit board provided with through holes perforated thereinto, an IC mounted on the upper surface of the circuit board, a solder filling a space between the circuit board and the IC via the through holes and being cured, and solder lands formed on the circuit board and attached with the solder.
    Type: Grant
    Filed: March 13, 2002
    Date of Patent: April 27, 2004
    Assignee: LG Electronics, Inc.
    Inventor: Jong Sik Kim
  • Patent number: 6712111
    Abstract: A carrier tool having a protective ring with a sheet extended over an underside of the ring is used, a semiconductor wafer is made to adhere to the sheet, the semiconductor wafer, being surrounded by the protective ring, is carried from a container device to a bonding stage. Bonding is performed on the bonding stage, and the wafer is carried out to another container device, consequently damage of the wafer is avoided.
    Type: Grant
    Filed: March 11, 2002
    Date of Patent: March 30, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tetsuya Tokunaga, Takahiro Yonezawa, Hiroyuki Kiyomura, Tatsuo Sasaoka
  • Publication number: 20040016791
    Abstract: An automated soldering system includes a robotic soldering machine and a plurality of feed lines for delivering workpieces to be soldered by the soldering machine. Each of the feed lines transports workpieces such as LCD modules from an input end to a soldering area, and from the soldering area to an outlet end. The soldering areas are arranged within the range of motion of a soldering arm of the soldering machine are preferably arranged in a bilateral triangle having the pivot axis of the soldering are at its apex. The soldering arm is programmed to work reciprocally among the soldering areas, thus increasing the yield of the robotic soldering machine so that the soldering machine is more cost effective. The soldering machine may be programmed to perform different soldering operations at different soldering areas.
    Type: Application
    Filed: June 12, 2003
    Publication date: January 29, 2004
    Applicant: HannStar Display Corp.
    Inventor: Johnny Wang
  • Publication number: 20030223203
    Abstract: A method of mounting a package such as a Butterfly package to a printed circuit board in order to make efficient use of the board's real estate is described. According to a preferred embodiment of the invention the package is mounted on its side such that leads of one side (now the bottom) of the butterfly package are connected either directly to surface mount pads on the PCB or project through and connected to through-holes in the PCB. The leads on the other side (now top) are connected to a flex circuit or ribbon cable. A heatsink can be attached to the package without impinging significantly on the PCB layout.
    Type: Application
    Filed: May 27, 2003
    Publication date: December 4, 2003
    Inventors: Eric Lutkiewicz, Bob Van Leeuwen, Peter J. KleinBeernink
  • Patent number: 6648210
    Abstract: Tombstoning susceptibility and reflow peak temperature reduction of solder alloys, in particularly lead-free solder alloys, has been found to be achieved effectively by mixing the solder alloy in the form of an alloy paste with a low melting alloy utilised in powder form, in particular a Bi-containing alloy.
    Type: Grant
    Filed: February 9, 2001
    Date of Patent: November 18, 2003
    Assignee: Multicore Solders Limited
    Inventor: Hector Andrew Hamilton Steen
  • Publication number: 20030193741
    Abstract: The present invention provides a magnetic head construction, a connection method and a connecting device by which excellent electrical connection can be carried out between a core electrode and a substrate land face on a flexure in a magnetic head employing the piggy back system. In order to attain the object of interest, in the present invention, a fine adjustment actuator is arranged between a core and a flexure; a projection portion which is projected from the fine adjustment actuator when viewed from the flexure is provided in the core; a hole is provided in the position, on the flexure, corresponding to the projection portion; only the core is fixed by a support portion provided through the hole portion and a clamp pin without applying any load to the fine adjustment actuator; and while maintaining this fixing state, an electrode and a substrate land are bonded to each other with a wire.
    Type: Application
    Filed: May 27, 2003
    Publication date: October 16, 2003
    Applicant: TDK Corp.
    Inventors: Toru Mizuno, Kouji Tanaka, Satoshi Yamaguchi
  • Patent number: 6622905
    Abstract: An apparatus, comprising a substrate having a surface, comprising one or more solder pads, each having a center and connected to a via, each via having a center; positioned relative to the surface such that at least one of the one or more solder pad centers is offset from the connecting via center and an area of the at least one of the one or more solder pads overlaps an area of the connecting via.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: September 23, 2003
    Assignee: Intel Corporation
    Inventors: Daniel E. Shier, Phil Geng, Scott N. Dixon
  • Patent number: 6607115
    Abstract: An electrical junction box for a vehicle has a connector circuit having bus bars fixed on an insulation substrate to connect to electrical connectors, a fuse circuit having bus bars fixed on an insulation substrate to connect to fuses, and a relay circuit having third bus bars fixed on an insulation substrate to connect to relays in use. In assembling the box, in order to avoid generation of stress and allow for dislocation of the circuits, the method includes the steps of: (i) joining upstanding welding portions of bus bars of the connector circuit and the fuse or relay circuit by arranging them adjacent each other and welding them together; and (ii) after step (i), joining laterally projecting welding portions of bus bars of the connector circuit and the fuse or relay circuits by welding them together when superimposed one on the other.
    Type: Grant
    Filed: July 20, 2001
    Date of Patent: August 19, 2003
    Assignee: Sumitomo Wiring Systems, Ltd.
    Inventors: Noriko Kobayashi, Yukitaka Saito, Tatsuya Sumida
  • Publication number: 20030136812
    Abstract: An electromagnetic shield is provided and includes a shield body having an upper wall connected to opposing side walls and opposing end walls. At least two opposing walls of the electromagnetic shield each have a plurality of resilient fingers formed at a lower edge thereof. The electromagnetic shield also includes a solder mass securely held by the fingers by being interleaved between the fingers of each of the at least two opposing walls. The interleaving of the solder mass results in the solder mass being securely held by the fingers and ready for mounting to an electronic component for shielding a portion of the electronic component from undesirable and potentially damaging emissions from neighboring components. A method of mounting an electromagnetic shield to an electronic component having a planar surface and a method of interleaving the solder mass are also provided.
    Type: Application
    Filed: January 13, 2003
    Publication date: July 24, 2003
    Applicant: NAS INTERPLEX, INC.
    Inventor: Jack Seidler
  • Patent number: 6595404
    Abstract: Forming solder bumps each having a constant height by surely supplying onto each of electrode pads a solder ball corresponding to a predetermined volume while omitting Au plating performed on the electrode pads onto which the solder bumps are to be formed. For achieving the forming of the solder bumps, the adhesive film is formed instead of the Au plating, the adhesive film being used as an oxidation-preventing film and as film for temporarily fixing each of the solder balls, the solder balls being supplied by stencil mask or the vacuum adsorbing mask.
    Type: Grant
    Filed: January 12, 2001
    Date of Patent: July 22, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Takamichi Suzuki, Yoshihide Yamaguchi, Noriyuki Oroku, Kosuke Inoue
  • Patent number: 6592018
    Abstract: The present method relates to the use of a peelable anti-solder mask as a sealant against potting compound. In certain electrical apparatus, a modular component (300) must be attached to a side of a printed circuit board (PCB) (110) which has previously been exposed to solder. Solder ‘pick up’ is prevented by application of a removable mask (202) over areas of the exposed side of the PCB (110) which will receive the modular component (300). Potting compound is used to protect components of electrical circuits (108) from vibration, moisture and static discharges. The anti-solder mask (202) can be used as a thin gasket to prevent the ingress of potting compound between the modular component (300) and the PCB (110).
    Type: Grant
    Filed: October 2, 2001
    Date of Patent: July 15, 2003
    Assignee: Siemens Aktiengesellschaft
    Inventors: Russell Taylor, Tom Copeland
  • Patent number: 6581820
    Abstract: Disclosed herein is a lead bonding method for SMD packages. The lead bonding method includes the step of placing a package body with its lead-positioning surface facing upward. A lead with solder is arranged on the lead-positioning surface of the package body using vision system. The lead is spot-welded onto the package body to fix the lead to the package body. The package body spot-welded together with the lead is arranged in a positioning depression of a jig with the lead facing downward. The solder formed on the lead are melted to bond the lead to the package body.
    Type: Grant
    Filed: July 27, 2001
    Date of Patent: June 24, 2003
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jong-Sung Jung, Jong-Tae Kim, Guem-Young Youn, Chang-Dug Kim
  • Patent number: 6572009
    Abstract: A method and apparatus for retaining heat at a pin-in-hole rework site on a printed circuit board during solder fountain rework of the board. A preheated heat retention plate is attached to the rework side of the printed circuit board. The heat retention plate covers a substantial portion of the board surface. During rework of the printed circuit board, the heat retention plate minimizes the temperature gradient between the rework site of the printed circuit board and the remainder of the printed circuit board. During the rework, the heat retention plate can be heated by an active heater in order to maintain a constant temperature gradient between the rework site of the board and the remainder of the board. By minimizing the escape of heat from the rework site, the number of solder cycles required to rework the board is decreased, resulting in reduced board rework times and increased board longevity.
    Type: Grant
    Filed: January 3, 2002
    Date of Patent: June 3, 2003
    Assignee: International Business Machines Corporation
    Inventors: Scott Peter Graves, Phillip Duane Isaacs
  • Publication number: 20030089758
    Abstract: In a wire-bonding process, a chip is provided with at least a first contact pad. A chip carrier is further provided with at least a second contact pad. A plurality of stacked conductive bumps are formed on the first contact pad. A conductive wire is formed by a reverse bonding process. The conductive wire electrically connects the second contact pad of the chip carrier to the stacked conductive bumps over the first contact pad of the chip.
    Type: Application
    Filed: December 31, 2002
    Publication date: May 15, 2003
    Inventor: Chun-Chi Lee
  • Patent number: 6550664
    Abstract: A device includes a die that contains a filter circuit. The filter is implemented using film bulk acoustic resonators. A package contains the die. The package includes a base portion. Signal paths are incorporated in the base portion. Solder joints attach the die to the base portion. The solder joints electrically connect pads on the die to the signal paths in the base portion. The solder joints do not include, and are used instead of, wire bonds.
    Type: Grant
    Filed: December 9, 2000
    Date of Patent: April 22, 2003
    Assignee: Agilent Technologies, Inc.
    Inventors: Paul Bradley, John D. Larson, III, Richard C. Ruby
  • Patent number: 6543673
    Abstract: A method and system are disclosed for protecting an electrical component from electrostatic discharge prior to its electrical connection to an additional component. Specifically, a flex on suspension circuit of a disc drive that is electrically connected to the read/write head is disclosed as having exposed leads for connection to a printed circuit cable assembly. The exposed leads are shunted with a solder conductor such as solder tape after testing of the circuit and head to prevent electrostatic build-up across the read and write elements. The flex on suspension circuit is then electrically connected to the printed circuit assembly cable by reflowing the solder conductor to bond the exposed leads of the flex on suspension circuit to the electrical contacts of the printed circuit assembly cable and also to remove the electrical short established between the exposed leads by the solder conductor.
    Type: Grant
    Filed: June 26, 2001
    Date of Patent: April 8, 2003
    Assignee: Seagate Technology LLC
    Inventors: Michael Henry Lennard, William Leon Rugg
  • Patent number: 6536653
    Abstract: A one-step bumping/bonding process for forming a semiconductor package is disclosed. In the method, a first electronic substrate which has either a plurality of conductive pads or a plurality of recessed openings formed on top of a plurality of apertures through the substrate is first provided and aligned with a second electronic substrate that has a plurality of conductive pads with each aperture aligned to a conductive pad on the second substrate. A plurality of solder balls is then planted on top of the plurality of conductive pads or the plurality of recessed openings on the surface of the first electronic substrate by a pick-and-place technique. Alternatively, a plurality of solder paste may be printed by a thick film stencil printing process similarly in place of the plurality of solder balls.
    Type: Grant
    Filed: January 16, 2001
    Date of Patent: March 25, 2003
    Assignee: Industrial Technology Research Institute
    Inventors: Hsing-Seng Wang, Rong-Shen Lee, Chiang-Han Day
  • Patent number: 6531232
    Abstract: The invention relates to a system comprising a first substrate (100) with at least one bonding area (110a, 110b), liable to be assembled with a second substrate (200), the bonding area (110a, 110b) comprising an area made of a material (104) that can be wetted with a meltable material. According to the invention, the bonding area (110a, 110b) comprises at least one cavity (120) to receive meltable material.
    Type: Grant
    Filed: April 16, 2001
    Date of Patent: March 11, 2003
    Assignee: Commissariat a l'Energie Atomique
    Inventors: François Baleras, Pierre Renard
  • Patent number: 6523255
    Abstract: Method for repairing, reworking or replacing damaged probes that are formed using a flying lead wire bonding process used for testing integrated circuit devices and other electronic devices, with the same column and row spacing as the original probes and using the same height as the original probes.
    Type: Grant
    Filed: June 21, 2001
    Date of Patent: February 25, 2003
    Assignee: International Business Machines Corporation
    Inventors: Da-Yuan Shih, Keith Edward Fogel, Paul Alfred Lauro, Brian Samuel Beaman
  • Publication number: 20030015575
    Abstract: There is provided an improved lead-free solder material which is preferably used as a connecting material in a mounting process of an electronic component.
    Type: Application
    Filed: May 17, 2002
    Publication date: January 23, 2003
    Inventors: Atsushi Yamaguchi, Masato Hirano, Yoshinori Sakai
  • Patent number: 6481616
    Abstract: To eliminate breakage of electronic parts or defective bonding, and enhance reliability of electronic parts, in regulation of electronic parts in bump bonding device. A bump bonding device comprising a stage 1 for mounting and heating an electronic part, and a position regulating device including a rotatable regulating plate 2 having a side for positioning the electronic part, a plate 4 having a side for positioning the electronic part in collaboration with the regulating plate, and a regulating spring 5 for applying a regulating force to the regulating plate in order to press the electronic part to the plate 4.
    Type: Grant
    Filed: October 17, 2001
    Date of Patent: November 19, 2002
    Assignee: Matsushita Electric Industrial Co. Ltd.
    Inventors: Makoto Imanishi, Akihiro Yamamoto, Hiroyuki Otani, Shinzo Eguchi, Takahiro Yonezawa, Kazushi Higashi, Koichi Yoshida, Kouji Hirotani
  • Patent number: 6467674
    Abstract: A sealing film is formed on a semiconductor substrate on which a number of columnar electrodes are formed, and then the upper surface of the sealing film is polished to expose the upper surfaces of the columnar electrodes made of a soft metal. During the polishing, laterally broadened edges are generated on the upper sides of the columnar electrodes. Then, the upper surfaces of the columnar electrodes, including the laterally broadened edges, are etched so as to remove the edges. In this manner, the shape of the upper surfaces of the columnar electrodes can be formed as initially designed, and therefore the bonding strengths can be made uniform. Thus, the reliability of the device can be improved.
    Type: Grant
    Filed: November 27, 2000
    Date of Patent: October 22, 2002
    Assignee: Casio Computer Co., Ltd.
    Inventor: Ichiro Mihara
  • Patent number: 6454160
    Abstract: The method for hermetically encapsulating microsystems in situ consists, in a first phase, of mounting on a common substrate (1), several microsystems (6) surrounded by a metal adhesion layer (4) deposited on the substrate (1). In a second phase, in a common deposition step a first metal layer (7) is deposited by electrolytic means on each microsystem (6) and on an annular zone (7a) of the adhesion layer (4) surrounding each microsystem (6), so as to completely cover each microsystem by overlap. Subsequently a second metal layer (9) is deposited by electrolytic means on the first metal layer (7) and on the adhesion layer so as to cover most of the first layer with the exception of at least one passage (10) per microsystem (6), providing access to the first layer (7). The metal of the first layer is different from the metals of the adhesion layer, the second layer and the microsystem.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: September 24, 2002
    Assignee: Asulab S.A.
    Inventor: François Gueissaz
  • Patent number: 6449836
    Abstract: In interconnecting printed circuit boards: preparing a first and second printed circuit board is accomplished with the first having an insulating substrate of thermoplastic resin and a conductive pattern with a land, while the second has a conductive pattern with a land; overlapping the land of the first with the land of the second is done to form an interconnection portion; and heating the interconnection portion at a temperature approximately higher than a glass transition temperature of the thermoplastic resin while applying pressure to the interconnection portion to create an electrical interconnection sealed with a part of the thermoplastic resin constituting the insulating substrate of the first board is accomplished. The insulating substrate of the first board is overlapped with an insulating substrate of the second printed board to interpose a film, the film including material to reduce a modulus of elasticity of the insulating substrate of the first board.
    Type: Grant
    Filed: July 26, 2000
    Date of Patent: September 17, 2002
    Assignee: Denso Corporation
    Inventors: Toshihiro Miyake, Katsuaki Kojima, Hiroyasu Iwama, Makoto Totani, Yoshitaro Yazaki, Takehito Teramae, Tomohiro Yokochi, Kenzo Hirano, Tomoyuki Nanami
  • Patent number: 6427899
    Abstract: A machine and method for bonding puncture-type conductive contact members of an interconnect to the bond pads of a bare semiconductor die includes the use of one or two ultrasonic vibrators mounted to vibrate one or both of the die and interconnect. A short axial linear burst of ultrasonic energy enables the contact members to pierce hard oxide layers on the surfaces of the bond pads at a much lower compressive force and rapidly achieve full penetration depth.
    Type: Grant
    Filed: August 3, 2001
    Date of Patent: August 6, 2002
    Assignee: Micron Technology, Inc.
    Inventors: David R. Hembree, Michael E. Hess, John O. Jacobson, Warren M. Farnworth, Alan G. Wood
  • Patent number: 6412165
    Abstract: A method of increasing the cycle life of a thermostatic disc element for use in a disc assembly used in thermostatic switches in which a weld slug is used to weld the disc element to the disc assembly thereby causing a heat affected zone of the disc element comprising the step of engaging the surface of the disc element opposite the surface adjacent the weld slug with a fulcrum member at a location spaced from the heat affected zone so that upon reversal of the curvature of the disc element, the disc element will bend about the fulcrum member at a location removed from the heat affected zone.
    Type: Grant
    Filed: April 23, 1998
    Date of Patent: July 2, 2002
    Assignee: Texas Instruments Incorporated
    Inventor: Sheldon S. White
  • Publication number: 20020079353
    Abstract: A method and apparatus for retaining heat at a pin-in-hole rework site on a printed circuit board during solder fountain rework of the board. A preheated heat retention plate is attached to the rework side of the printed circuit board. The heat retention plate covers a substantial portion of the board surface. During rework of the printed circuit board, the heat retention plate minimizes the temperature gradient between the rework site of the printed circuit board and the remainder of the printed circuit board. During the rework, the heat retention plate can be heated by an active heater in order to maintain a constant temperature gradient between the rework site of the board and the remainder of the board. By minimizing the escape of heat from the rework site, the number of solder cycles required to rework the board is decreased, resulting in reduced board rework times and increased board longevity.
    Type: Application
    Filed: January 3, 2002
    Publication date: June 27, 2002
    Inventors: Scott Peter Graves, Phillip Duane Isaacs
  • Patent number: 6411516
    Abstract: A printed circuit board assembly includes a printed circuit board, with a first side and a second side and at least one opening formed therebetween. The opening has a slug at least partially disposed therein and attached to the first side. The second side of the circuit board has a hot component positioned thereon and overlying the opening. A solder joint is formed between the slug and the hot component to allow dissipation of heat from the hot component.
    Type: Grant
    Filed: June 15, 2001
    Date of Patent: June 25, 2002
    Assignee: Hughes Electronics Corporation
    Inventors: Aaron Palumbo, Alex Toh, Abhay Umdekar
  • Publication number: 20020070262
    Abstract: A device includes a die that contains a filter circuit. The filter is implemented using film bulk acoustic resonators. A package contains the die. The package includes a base portion. Signal paths are incorporated in the base portion. Solder joints attach the die to the base portion. The solder joints electrically connect pads on the die to the signal paths in the base portion. The solder joints do not include, and are used instead of, wire bonds.
    Type: Application
    Filed: December 9, 2000
    Publication date: June 13, 2002
    Inventors: Paul Bradley, John D. Larson, Richard C. Ruby
  • Patent number: 6399475
    Abstract: Process for producing electrical connections on the surface of a semiconductor package containing an integrated-circuit chip and having metal electrical-connection regions on the surface of the package, consisting of: covering these connection regions with a first metal layer forming an anti-diffusion barrier; covering this first layer with an anti-oxidation second metal layer; and depositing a metal solder drop or solder ball on the second metal layer. The solder drop comprises an addition of metal particles in suspension which contain at least one of the metals of the first metal layer so as to produce a precipitate comprising these additional metal particles and at least partly the metal of the second metal layer, the precipitate remaining in suspension in the solder drop.
    Type: Grant
    Filed: October 4, 2000
    Date of Patent: June 4, 2002
    Assignee: STMicroelectronics S.A.
    Inventor: Luc Petit
  • Patent number: 6386436
    Abstract: The present invention is drawn to a method of making solder bump interconnections or BGAs ranging from chip-level connections to either single chip or multichip modules, flip-chip packages and printed circuit board connections. According to the method of the present invention, a die wafer or a substrate with a conductive contact location is positioned in close proximity and aligned with a mold wafer having a pocket corresponding to the contact location of the die wafer. A source of a molten solder is also provided which interconnects with the mold wafer. The molten solder from the source is introduced into the pocket of the mold wafer such that the molten solder wets the contact location aligned with the pocket. Before the molten solder inside the pocket is allowed to solidify, the die wafer and the mold wafer are separated from each other.
    Type: Grant
    Filed: February 16, 2001
    Date of Patent: May 14, 2002
    Assignee: Micron Technology, Inc.
    Inventor: David R. Hembree
  • Patent number: 6388187
    Abstract: Before electrically connecting at least two photovoltaic elements, a medium capable of absorbing at least 10% or more of a light having a wavelength of 0.4 &mgr;m to 2.0 &mgr;m is provided on an electric connection portion of the photovoltaic element, whereby the present invention provides a method of electrically connecting a group of photovoltaic elements to one another with a high yield and easy automatization.
    Type: Grant
    Filed: December 23, 1998
    Date of Patent: May 14, 2002
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yoshifumi Takeyama, Tsunenobu Satoi, Shozo Kasai, Tsutomu Murakami, Masayuki Kusakari, Koji Tsuzuki, Yoshimitsu Hayashi, Koichi Shimizu
  • Publication number: 20020053590
    Abstract: A method and system are disclosed for protecting an electrical component from electrostatic discharge prior to its electrical connection to an additional component. Specifically, a flex on suspension circuit of a disc drive that is electrically connected to the read/write head is disclosed as having exposed leads for connection to a printed circuit cable assembly. The exposed leads are shunted with a solder conductor such as solder tape after testing of the circuit and head to prevent electrostatic build-up across the read and write elements. The flex on suspension circuit is then electrically connected to the printed circuit assembly cable by reflowing the solder conductor to bond the exposed leads of the flex on suspension circuit to the electrical contacts of the printed circuit assembly cable and also to remove the electrical short established between the exposed leads by the solder conductor.
    Type: Application
    Filed: June 26, 2001
    Publication date: May 9, 2002
    Applicant: Seagate Technology LLC
    Inventors: Michael Henry Lennard, William Leon Rugg
  • Patent number: 6375064
    Abstract: A conductive paste is loaded in circular holes made in a reinforcing film of a carrier tape which includes a film substrate and the reinforcing film, followed by applying a heat treatment to the conductive paste to form projecting electrodes consisting of solder. Then, the reinforcing film is peeled off to permit the projecting electrode to project from the film substrate.
    Type: Grant
    Filed: March 15, 2000
    Date of Patent: April 23, 2002
    Assignee: Casio Computer Co., Ltd.
    Inventors: Kenji Edasawa, Shiro Ozaki, Kazuhiro Sugiyama, Isao Kurashima
  • Patent number: 6377468
    Abstract: Circuit elements of surface-mounting type such as MOSFETs etc. are mounted on a circuit board by soldering. The circuit board is retained slantingly by a base so that any one of the MOSFET falls out by its self-weight when the solder melts due to an abnormal heat generation of the MOSFET. The falling of the MOSFET is stopped by a stopper member, and then the MOSFET becomes in an electrically open state and retained at the stopped position in consequence of the subsequent cooling of the solder. Accordingly, even if one or more of the MOSFETs cause the abnormal heat generation, the continuous heat generation of the MOSFET is stopped and also the other circuit elements are prevented from being short-circuited.
    Type: Grant
    Filed: June 15, 2000
    Date of Patent: April 23, 2002
    Assignees: ANDEN Co., Ltd., DENSO Corporation
    Inventors: Hideyuki Ohtani, Fukuo Ishikawa, Hideki Kabune, Hiroshi Hattori
  • Publication number: 20020043549
    Abstract: The present invention relates to the use of a peelable anti-solder mask as a sealant against potting compound. In certain electrical apparatus, a modular component (300) must be attached to a side of a printed circuit board (PCB) (110) which has previously been exposed to solder. Solder ‘pick up’ is prevented by application of a removable mask (202) over areas of the exposed side of the PCB (110) which will receive the modular component (300). Potting compound is used to protect components of electrical circuits (108) from vibration, moisture and static discharges. The anti-solder mask (202) can be used as a thin gasket to prevent the ingress of potting compound between the modular component (300) and the PCB (110).
    Type: Application
    Filed: October 2, 2001
    Publication date: April 18, 2002
    Inventors: Russell Taylor, Tom Copeland
  • Patent number: 6369345
    Abstract: A method and apparatus for coupling a microelectronic component (114) to a printed circuit board (112) are disclosed. The component (114) is coupled to the circuit board (112) by placing leads (116) of component (114) in contact with conducting pads (118) on the circuit board (120), dispensing a bead of solder paste (110) onto the leads (116), and applying heat to the applied paste (110) to cause the solder to reflow. The solder bead is dispensed using a solder paste dispenser (108) and heated using a light source (102).
    Type: Grant
    Filed: August 18, 2000
    Date of Patent: April 9, 2002
    Assignee: Motorola, Inc.
    Inventors: Andrew W. Zaloga, Carolyn M. Stokman, Jeffery J. Kokovitch
  • Publication number: 20020038723
    Abstract: In a mounting mechanism of a metal plate on a printed board housed in a portable telephone or the like, a metal plate connected with a terminal portion of a cell or the like is joined to a land via solder, and a cut-out portion is provided at a joining portion of the metal plate which is joined to the land, and the total length of fillets of the solder between the land and the joining portion is extended by the cut-out portion. Accordingly, the mounting strength of a metal plate mounted to the land disposed on the printed board can be improved.
    Type: Application
    Filed: June 13, 2001
    Publication date: April 4, 2002
    Inventor: Itaru Takeda
  • Patent number: 6357649
    Abstract: A plurality of solder bumps are arranged in a row at regular pitch in a lead wire soldering region of a solar battery. A soldering apparatus for soldering a lead wire to the lead wire soldering region via the solder bumps comprises a lead wire feeding section for feeding out the lead wire. An end of the lead wire in the lead wire feeding section is chucked and the lead wire is laid over all length of the row of solder bumps. The soldering apparatus further comprises a soldering unit for soldering the lead wire onto the solder bump. The soldering unit has a lead wire holding member for holding the lead wire on a solder bump and a soldering iron. The soldering apparatus repeats an operation for welding the lead wire to the solder bump by means of the soldering iron, while the lead wire is held by the lead wire holding member.
    Type: Grant
    Filed: March 22, 2000
    Date of Patent: March 19, 2002
    Assignee: Kaneka Corporation
    Inventors: Toshihide Okatsu, Masataka Kondo, Akimine Hayashi, Eiji Kuribe
  • Publication number: 20020030087
    Abstract: To eliminate breakage of electronic parts or defective bonding, and enhance reliability of electronic parts, in regulation of electronic parts in bump bonding device. A bump bonding device comprising a stage 1 for mounting and heating an electronic part, and a position regulating device including a rotatable regulating plate 2 having a side for positioning the electronic part, a plate 4 having a side for positioning the electronic part in collaboration with the regulating plate, and a regulating spring 5 for applying a regulating force to the regulating plate in order to press the electronic part to the plate 4.
    Type: Application
    Filed: October 17, 2001
    Publication date: March 14, 2002
    Inventors: Makoto Imanishi, Akihiro Yamamoto, Hiroyuki Otani, Shinzo Eguchi, Takahiro Yonezawa, Kazushi Higashi, Koichi Yoshida, Kouji Hirotani
  • Publication number: 20020030086
    Abstract: An improved pitch and roll mechanism is disclosed herein which provides for increased flexibility, stability, and accuracy of motion in positioning a miniaturized electronic component in a flip chip bonding system. The pitch and roll mechanism generally includes a pitch axis assembly comprising a plurality of bearing surfaces, each possessing a circular curvature, and at least one roller bearing in operative contact with at least one of the aforementioned pitch axis bearing surfaces. In addition, a roll axis assembly, mounted at a right angle, or perpendicularly, to the pitch axis assembly, is provided. The roll axis assembly typically includes a plurality of bearing surfaces, each possessing a circular curvature, and at least one roller bearing in operative contact with at least one of the aforementioned roll axis bearing surfaces. The curvatures of the pitch and roll axis bearing surfaces are such that a single, coincident center of rotation for both the pitch and roll axis assemblies is created.
    Type: Application
    Filed: May 4, 2001
    Publication date: March 14, 2002
    Inventors: Steven M. Solon, David Leggett
  • Patent number: 6354485
    Abstract: A thermally enhanced semiconductor package includes a sheet metal cap having flexible flanges provided with solder contacts for reliable attachment to a circuit board. The package assembly further includes a semiconductor chip with a contact-bearing front surface facing forwardly, and chip bonding contacts overlying the front face of the chip. The flange bonding contacts are coplanar with the chip bonding contacts, or can be brought into coplanar alignment by flexure of the cap. The package can be surface-mounted to a circuit board by placing the package onto pads of solder paste, and then heating the assembly to melt the solder paste in order to join the bonding contacts on the chip and on the flange to corresponding contacts on the circuit board.
    Type: Grant
    Filed: August 30, 1999
    Date of Patent: March 12, 2002
    Assignee: Tessera, Inc.
    Inventor: Thomas H. Distefano
  • Publication number: 20020014518
    Abstract: Lands formed on a flexible printed circuit board are electrically connected with lands formed on a rigid printed circuit board through solder. At this point, solder resist is formed between neighboring two lands on the rigid printed circuit board, and is terminated with an end portion that is interposed between the rigid printed circuit board and the flexible printed circuit board. Accordingly, even when surplus solder is extruded onto the rigid printed circuit board, the solder resist can prevent solder bridges from being formed between the lands.
    Type: Application
    Filed: July 19, 2001
    Publication date: February 7, 2002
    Inventors: Makoto Totani, Toshihiro Miyake, Tomohiro Yokochi, Takehito Teramae, Yoshitaro Yazaki, Kazuyuki Deguchi, Hajime Nakagawa
  • Patent number: 6340110
    Abstract: A printed circuit board which has been soldered in a molten solder bath is cooled immediately thereafter with a cooling liquid at a rate of at least 10° C./second. Thermal effects of high-temperature solder during soldering are suppressed, and the metal matrix of the solder is refined, resulting in soldered connection of increased strength.
    Type: Grant
    Filed: February 18, 2000
    Date of Patent: January 22, 2002
    Assignee: Senju Metal Industry Co., Ltd.
    Inventors: Hideki Nakamura, Shohei Mawatari
  • Publication number: 20020003160
    Abstract: A method of fabricating solder assemblies for forming solder connections that include a dielectric base having a non solder-wettable surface, a plurality of solderwettable pads exposed to said surface, and an electrically conductive potential plane element having a non solderwettable surface overlying the surface of the base in proximity to the pads but spaced from said pads. The nonwettable surface of the potential plane element may include a metal such as nickel or a metal oxide. The potential plane element thus performs the functions of a solder mask to prevent solder from forming short circuits between adjacent pads, and may also act as a ground plane, power plane or shielding element.
    Type: Application
    Filed: August 30, 2001
    Publication date: January 10, 2002
    Inventors: Masud Beroz, Belgacem Haba
  • Patent number: 6332567
    Abstract: An improved method of manufacturing a piezoelectric element and an improved piezoelectric element are provided. The improved method comprises the steps of causing a gas discharge in a predetermined discharge gas at approximately atmospheric pressure and generating an excited active species of the discharge gas as a result of the gas discharge. Then, at least one of a connecting surface of an electrode formed of a piezoelectric piece on a piezoelectric resonator and a connecting portion of a lead terminal are exposed to the excited active species, whereby the exposed connecting portions are surface treated. Finally, the electrode and the lead terminal are connected together, and at least the electrode and the lead terminal are sealed in a case. The improved piezoelectric element is formed by this process and uses less solder and is more stable than prior art piezoelectric elements.
    Type: Grant
    Filed: March 17, 1997
    Date of Patent: December 25, 2001
    Assignee: Seiko Epson Corporation
    Inventors: Yasumitsu Ikegami, Takuya Miyakawa
  • Patent number: 6322659
    Abstract: A method for bonding includes positioning a bonding strip adjacent a sole first bond head, the bonding strip having a plurality of strip units, and bonding, with only the first bond head, a first number of the plurality of strip units. The method further includes transporting the bonding strip from the first bond head and positioning the bonding strip adjacent a sole second bond head, and bonding, with only the second bond head, a remaining number of the plurality of strip units on the bonding strip. In one embodiment, the method also includes heating at least one of the plurality of strip units prior to bonding the bonding strip. In one embodiment, the method also includes clamping, with a sole clamp, the bonding strip, thereby limiting warpage of the bonding strip.
    Type: Grant
    Filed: June 24, 1999
    Date of Patent: November 27, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Randy V. Tekavec, Larry Giaudrone, Peter Sakakini
  • Patent number: 6315190
    Abstract: A wire bonding method for connecting first and second points with a wire, comprising the steps of: connecting the wire to the first bonding point, raising the capillary and performing a reverse operation so as to move the capillary in the opposite direction from the second bonding point, raising the capillary obliquely upward toward the second bonding point (and then raising the capillary further), then raising the capillary and performing another reverse operation so as to move the capillary in the opposite direction from the second bonding point, and raising and then moving the capillary toward the second bonding point, thus connecting the wire to the second bonding point; thus forming a stable wire loop that has a high shape retention strength.
    Type: Grant
    Filed: June 25, 1999
    Date of Patent: November 13, 2001
    Assignee: Kabushiki Kaisha Shinkawa
    Inventor: Shinichi Nishiura
  • Patent number: 6302317
    Abstract: Wafers are previously positioned so that the wafer orientation flat is oriented in a particular direction. A transporting means then moves and places the previously positioned wafer on a bonding stage where bumps are formed on the wafer by means of a bonding head. The transporting means has a sensor for detecting the position of the orientation flat of a wafer on the bonding stage from a position above the bonding stage, thereby avoiding the adverse effects of heat from the bonding stage during orientation flat detection.
    Type: Grant
    Filed: June 18, 1999
    Date of Patent: October 16, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shoriki Narita, Makoto Imanishi, Takaharu Mae, Shinji Kanayama, Nobuhisa Watanabe
  • Patent number: 6299056
    Abstract: There is provided an LED that can prevent the dissolution and separation of electrodes due to etching in the manufacturing stage and has a high light emission efficiency even when horizontally mounted as well as a method for manufacturing the LED. In a light-emitting diode 100 which is cut from a wafer by dicing and in which a positive electrode 4 and a negative electrode 3 are formed parallel to a pn junction plane 20, the positive electrode 4 provided by a p-side ohmic contact metal layer 41 formed on a surface of a p-type semiconductor layer (p-type GaN layer 2) and a p-side electrode metal layer 42 made of an alloy including gold and nickel, while the negative electrode 3 is provided by an n-side ohmic contact metal layer 31 formed on a surface of an n-type semiconductor layer 1 and an n-side electrode metal layer 32 made of an alloy including gold and nickel. The side surface 7 of a light-emitting diode chip that is brought in contact with a dicing blade is etched by an acid solution.
    Type: Grant
    Filed: March 31, 2000
    Date of Patent: October 9, 2001
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Kiyohisa Oota