Of Electrical Device (e.g., Semiconductor) Patents (Class 228/179.1)
  • Patent number: 6295709
    Abstract: A PCB assembly which allows economical and reliable rework. The PCB assembly contains a soldermask and a trace with a portion of the trace exposed by a soldermask relief When one needs to rework the PCB assembly, one bonds a rework wire, using conventional intermetalic bonding materials, to the portion of the trace exposed by the soldermask relief There is no need to bond a rework wire to a component. Further, there is no need to scrape a off the soldermask and possibly damage the traces and/or vias. The bonds are high reliability bonds, and the labor required to perform such bonds are minimal.
    Type: Grant
    Filed: August 19, 1997
    Date of Patent: October 2, 2001
    Assignee: Micron Technology, Inc.
    Inventor: Dean A. Klein
  • Publication number: 20010023028
    Abstract: A soldering method, which secures reliable joints without using flux, is disclosed. Soldering is performed using an auxiliary connecting material capable of physically destroying and dispersing an oxide film, which is naturally grown on the surface of a main connecting material such as solder or brazing between two terminals, to realize a reliable solder wetting (a state of the main connecting material being fused and mixed). For an auxiliary connecting material, hydrocarbon such as n-tetradecane (C14H30), for example, can be used. N-tetradecane boils between connection surfaces and cubically expands; energy generated therefrom physically disperses the oxide film and causes a fresh surface to be exposed; solders on both terminals are mixed; and an electrical and mechanical joint is securely achieved. The residue of the auxiliary connecting material is an insulating material, and therefore does not need cleaning. An excellent electrical joint which is moisture-resistant as well as highly reliable is attained.
    Type: Application
    Filed: March 30, 2001
    Publication date: September 20, 2001
    Applicant: NIPPONDENSO CO., LTD.
    Inventors: Toshihiro Miyake, Koii Kondo, Takashi Kurahashi, Nozomu Okumura, Makoto Takagi
  • Patent number: 6290118
    Abstract: A pair of soldering irons are fixed to a sliding plate at a predetermined interval. The soldering irons are integrally moved so as to reciprocate in a rectangular direction relative to a conveyor belt. One of the soldering irons is conveyed to a working position of the conveyor belt and the other of them is separated from the conveyor belt. While one of the soldering irons solders a circuit board, the other is cleaned. The circuit board has a slit into which a metal plate is inserted and soldered. For the slit, a soldering land constituted of a main-land and a sub-land is provided. The main-land is formed along one of longer sides of the slit. The sub-land is elongated from the main-land along a shorter side of the slit. The soldering land is not formed all around the slit so that the slit is not closed by solder when the circuit board is dip-soldered.
    Type: Grant
    Filed: February 8, 2000
    Date of Patent: September 18, 2001
    Assignee: Fuji Photo Film Co., Ltd.
    Inventors: Masayoshi Muramatsu, Kenichi Watanabe
  • Patent number: 6279814
    Abstract: A punching pin of a soldering apparatus cuts out a solder piece from a solder plate onto a feeder pin, and the feeder pin presses the solder piece against a predetermined junction of a conductive wiring pattern incorporated in a printed circuit board; then, an electric circuit component is mounted on the printed circuit board, and is strongly soldered to the conductive wiring pattern, because the punching pin and the feeder pin supply a fixed amount of solder to the predetermined junction.
    Type: Grant
    Filed: June 23, 1999
    Date of Patent: August 28, 2001
    Assignee: Yamaha Corporation
    Inventors: Akifumi Inoue, Koshiro Takeda
  • Patent number: 6250538
    Abstract: An mounting apparatus for mounting an electrical component onto a substrate of an electrical assembly. The mounting apparatus employs a compensating element to facilitate the component mounting operation. The compensating element includes a spring member and a damping member. The spring member applies an optimal contact pressure for securely mounting said component without damaging the component. The damping element acts to damp the spring member during so as to effectively reduce a spring force that acts on the mounting apparatus during the component delivery stage.
    Type: Grant
    Filed: April 26, 2000
    Date of Patent: June 26, 2001
    Assignee: Siemens Aktiengesellschaft
    Inventors: Hans-Horst Grasmueller, Thomas Bachthaler, Richard Numberger, Frank Barnowski
  • Patent number: 6250539
    Abstract: A method, which is for forming accurate low wire loop shapes or short wire loop shapes which are stable and which have a high shape retention force in devices in which height differences between first and second bonding points are small and the wiring distance is short, including the steps of bonding a ball formed at the end of the wire extending out of the capillary to the first bonding point, raising the capillary while delivering the wire, moving the capillary toward the second bonding point, and then raising the capillary diagonally upward.
    Type: Grant
    Filed: September 29, 1999
    Date of Patent: June 26, 2001
    Assignee: Kabushiki Kaisha Shinkawa
    Inventors: Shinichi Nishiura, Tooru Mochida
  • Patent number: 6250537
    Abstract: A self-cleaning soldering thimble assembly includes a thimble and a scraper disposed therein. The scraper is supported by two support rods that extend through the bottom of the thimble. The thimble slides along the support rods. When the thimble is dipped into a solder pot to refill the thimble with solder, the support rods abut the bottom of the solder pot, and the thimble continues to slide down the support rods causing the scraper to scrape away dross on the thimble.
    Type: Grant
    Filed: March 6, 2000
    Date of Patent: June 26, 2001
    Assignee: Delphi Technologies, Inc.
    Inventors: Miguel I. Avila, Oscar Vazquez
  • Patent number: 6241143
    Abstract: An exposed connecting portion is formed by partially removing a film substrate by such laser etching while leaving a transmission line pattern. A film-type transmission line is placed in such a manner as to overlap the exposed connecting portion and a transmission line pattern on a side to be connected. Bonding, for example thermo compression bonding, is applied to the two overlapped line patterns. Since a gold ribbon is not used and overlapping of a high-dielectric substrate and the film substrate is unnecessary, impedance irregularity is reduced. This makes it possible to carry out bonding without the medium of the film substrate and a connection with high reliability may be achieved.
    Type: Grant
    Filed: September 10, 1999
    Date of Patent: June 5, 2001
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Kazushi Kuroda
  • Patent number: 6239400
    Abstract: A process and a device for bonding two millimeter elements. The process makes, at determined locations of each of the two millimeter elements, bonding zones set to the potential of a second plane. Then, the process makes the bond by determined connections between the bonding zones and between conducting lines of the two millimeter elements. The device includes a coplanar line. Such a process and device may find particular application to millimeter circuits implementing conducting lines of the microstrip type.
    Type: Grant
    Filed: November 23, 1999
    Date of Patent: May 29, 2001
    Assignee: Thomson-CSF
    Inventors: Gérard Cachier, Jean-Yves Daden, Alain Grancher
  • Patent number: 6223973
    Abstract: An apparatus and method for connecting together first and second printed circuit boards 10/20 (PCBs), wherein one or both of the PCBs is a flex circuit. The method includes overlapping the two PCBs such that their respective matching circuit trace arrays 12/22 face each other and are separated by a small predetermined distance K, and then introducing molten solder 30 proximate an overlapping PCB edge 18, such as by wave soldering, so as to urge capillation of the molten solder between the two PCBs, thereby forming solder joints operatively connecting together the two circuit trace arrays.
    Type: Grant
    Filed: November 16, 1999
    Date of Patent: May 1, 2001
    Assignee: Visteon Global Technologies, Inc.
    Inventors: Stephen H. P. Wong, Billy Kiang
  • Patent number: 6223429
    Abstract: To provide a highly reliable semiconductor device structure that enables cost reduction in the production of packages, inclusive of the cost for chips, and may cause less changes in connection resistance even under conditions of a long-term environmental resistance test. In a semiconductor device comprising a semiconductor chip face-down bonded to a wiring board, it has a structure wherein projecting metal portions are provided at the opposing wiring board terminals without forming bumps on bonding pads of the chip, the whole chip surface is bonded with an organic, anisotropic conductive adhesive material, and the whole or at least an edge of the back of the chip is covered with a sealing material.
    Type: Grant
    Filed: July 30, 1998
    Date of Patent: May 1, 2001
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Aizou Kaneda, Masaaki Yasuda, Itsuo Watanabe, Tomohisa Ohta, Fumio Inoue, Yoshiaki Tsubomatsu, Toshio Yamazaki, Hiroto Ohata, Kenzo Takemura, Akira Nagai, Osamu Watanabe, Naoyuki Shiozawa, Kazuyoshi Kojima, Toshiaki Tanaka, Kazunori Yamamoto
  • Patent number: 6214718
    Abstract: A semiconductor assembling method joins a bonding wire with a bonding object by pressing the bonding wire against the bonding object with a bonding pressurizing tool and by effecting at least one junction process of thermal junction or ultrasonic junction. The method includes steps of measuring a time elapsing from a last bonding process to a subsequent bonding process or a temperature of the pressurizing tool, and changing at least one junction condition of pressurizing force, pressurizing time, ultrasonic oscillation output, and ultrasonic oscillation time for the subsequent bonding process, based on the measured time. A semiconductor assembling apparatus includes a measuring device for measuring the time or temperature and a junction condition changing device for changing the condition to perform the method.
    Type: Grant
    Filed: May 10, 1999
    Date of Patent: April 10, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshiyuki Nagai, Shinzou Eguchi
  • Patent number: 6213382
    Abstract: A gold alloy wire in which 0.2 to 5.0% by weight of palladium (Pd) and 1 to 100 ppm by weight of bismuth (Bi) are added to gold having a purity of at least 99.99% by weight. Preferably, at least one element selected from the group consisting of yttrium (Y), lanthanum (La), calcium (Ca) and beryllium (Bi) in an amount of 3 to 250 ppm by weight is further added to said gold. The gold alloy wire is especially adapted to forming a gold bump.
    Type: Grant
    Filed: January 5, 1999
    Date of Patent: April 10, 2001
    Assignee: Tanaka Denshi Kogyo K.K.
    Inventor: Hideyuki Akimoto
  • Patent number: 6209776
    Abstract: In a flyback transformer device wherein the leads of diodes or like electronic components are connected between pairs of terminal pieces provided upright at opposite ends of a coil bobbin, the lead ends, of the components are fixedly connected to the respective terminal pieces by electric welding. A coil conductor wound around the bobbin has an end twined around the terminal piece, and the twined portion is soldered by dipping.
    Type: Grant
    Filed: December 23, 1994
    Date of Patent: April 3, 2001
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Akio Kurogi, Hiroshi Okamoto, Hideo Onishi, Yasushi Akado
  • Patent number: 6206272
    Abstract: An alignment weight is provided. The alignment weight includes a body of material having first and second opposing surfaces. A number of depressions are formed in the first surface. The depressions receive pins of a floating pin field when placed on a floating pin field during connection of the floating pin field to a printed circuit board.
    Type: Grant
    Filed: April 8, 1999
    Date of Patent: March 27, 2001
    Assignee: Intel Corporation
    Inventors: Cheryl M. Waldron-Floyde, Brad C. Irwin
  • Patent number: 6202299
    Abstract: A semiconductor chip connection component is provided with an adhesive, desirably in a solid, non-tacky condition on its bottom surface. The adhesive may be present in a pattern covering less than all of the component bottom surface, so as to provide a void-free interface when the adhesive bonds the component to the top surface of a chip. The adhesive desirably is brought to a flowable condition by heat transferred from the chip itself. The connection component may include leads having base metal strips in a trace area underlying the top surface and noble metal portions protruding beyond an edge of the top layer. A flowable, curable material encapsulates the base metal sections. Because the base metal sections desirably are free of undercuts, the same can be encapsulated in a void-free manner during formation of the component.
    Type: Grant
    Filed: December 11, 1998
    Date of Patent: March 20, 2001
    Assignee: Tessera, Inc.
    Inventors: Thomas H. DiStefano, Gus Karavakis, Zlata Kovac, Craig Mitchell
  • Patent number: 6193130
    Abstract: A bump bonding apparatus comprising: a loader section that holds trays which accommodate semiconductor pellets and an unloader section that holds trays which accommodate semiconductor pellets to which bumps have been applied, the loader and unloader sections being provided next to each other on one side of a bonding stage; a buffer station and a supply and holding station provided so as to positionally correspond to the loader section and unloader section, respectively; a first pusher for sending trays from the loader section to the buffer station, a second pusher for sending trays from the supply and holding station to the unloader section, a third pusher for sending trays from the buffer station to the supply and holding station, and a pellet transfer mechanism for picking up a semiconductor pellet in the tray in the supply and holding station, transferring it to the bonding stages and then returning the semiconductor pellets to which bumps have been applied on the bonding stages back to the tray in which t
    Type: Grant
    Filed: February 12, 1999
    Date of Patent: February 27, 2001
    Assignee: Kabushiki Kaisha Shinkawa
    Inventors: Hiroshi Ushiki, Hirofumi Moroe, Koichi Takahashi
  • Patent number: 6173883
    Abstract: A thermal mass (18) is reflow soldered atop of a multi-layered medium (10) in order to yield minimum thermal resistance between a heat source (22) located on the multi-layered medium (10) and the thermal mass (18) for greater heat dissipation efficiency. Moreover, the thermal mass (18) can be auto-placed onto the multi-layered medium (10) in order to accurately and closely position the thermal mass (18) next to the heat source (22).
    Type: Grant
    Filed: November 17, 1998
    Date of Patent: January 16, 2001
    Assignee: Motorola, Inc.
    Inventors: Harold Joseph Gorenz, Jr., Patrick David Smith, Jeffrey P. Hasler
  • Patent number: 6170155
    Abstract: This invention relates to a system of components to be hybridized including at least one first component (110) with first pads (114a) and with a first coefficient of expansion, and at least one second component (112) with second pads (114b) and with a second coefficient of expansion. According to the invention, at a hybridization temperature Th the pads are approximately superposable, and at an ambient temperature Ta the pads are mutually offset by a distance compensating for the differential expansion of the first and second components.
    Type: Grant
    Filed: May 15, 1997
    Date of Patent: January 9, 2001
    Assignee: Commissariat a l'Energie Atomique
    Inventors: François Marion, Chantal Chantre
  • Patent number: 6168070
    Abstract: There is disclosed herein a method for soldering an electronic component 10 having a heatspreader 14 on a bottom surface thereof and at least one lead 18 (e.g.
    Type: Grant
    Filed: October 14, 1998
    Date of Patent: January 2, 2001
    Assignee: Visteon Global Technologies, Inc.
    Inventor: Peter Joseph Sinkunas