Abstract: A semiconductor device has an n.sup.+ source region, a first n.sup.- channel region, a barrier layer, a second n.sup.- channel region, a pair of n.sup.+ drain regions, an insulating film, and a pair of metal electrodes over the respective n.sup.+ drain regions, all successively disposed on an upper surface of an n.sup.+ crystal substrate. The drain regions and the metal electrodes jointly provide a storage electric capacitance. A source electrode is disposed on the lower surface of the n.sup.+ crystal substrate. Bit information can be written and read at a high speed by tunneling through the barrier layer. According to a method of manufacturing the above semiconductor device, the n.sup.+ source region, the first n.sup.- channel region, the barrier layer, the second n.sup.- channel region, the n.sup.+ drain regions, the insulating film, and the metal electrodes are successively deposited on the n.sup.+ crystal substrate in a growing apparatus.

Abstract: A notched insulation gate static induction transistor integrated circuit ording to the present invention comprises an enhancement mode CMOS logic circuit including a notched insulation gate static induction transistor in which a threshold voltage is determined to prevent current from flowing in a standby mode, and a depletion enhancement mode CMOS logic circuit including a notched insulation gate static induction transistor in which a threshold voltage is determined to cause current to slightly flow in the standby mode. The enhancement mode CMOS logic circuit and the depletion enhancement mode CMOS logic circuit are formed on a major surface of a substrate, and the depletion enhancement mode CMOS logic circuit is used in a circuit in which an average power consumption in a switching operation is higher than that in the standby mode.

Abstract: In a gate insulated static induction thyristor with a split gate type shorted cathode structure, a first gate region of the split gate structure is used as a cathode short-circuit gate and the cathode region is formed between the first and second gate regions. A MOS structure is formed on the second gate region as a insulated gate control gate region electrode isolated therefrom. The MOS gate structure suppresses the minority carrier (hole) storage effect to permit high-speed switching of the thyristor, and the shorted cathode structure provides for increased maximum controllable current/voltage durability. The split gate structure can be used in combination with planar, buried, recessed and double gate structures.

Abstract: Base regions of a second conductivity type are formed and spaced apart from one another in a first major surface of a semiconductor substrate of a first conductivity type which functions as a drain region. Source regions of the first conductivity type are formed in each of the base regions and spaced apart from one another. Gate insulating films are formed on portions of the drain region which are located between adjacent source regions. Gates are formed on the gate insulating films. Source electrodes are formed such that each electrode short-circuits one-base region to the source regions formed in the base region. A first anode region of the second conductivity type is formed on a second major surface of the semiconductor substrate. A second anode region of the second conductivity type is formed on the first anode region. This second anode region is made of polycrystalline silicon of the second conductivity type and has an impurity concentration higher than that of the first anode region.

Abstract: A static induction thyristor has a first semiconductor area having a high impurity concentration of a first conductivity type. A second semiconductor area having low impurity concentration is formed adjacent to the first semiconductor area. A third semiconductor area having a high impurity concentration of a second conductivity type which is the conductivity type opposite to the first conductivity type is formed on a part of a surface of the second semiconductor area so located as to form a fourth semiconductor area located within the third semiconductor area. A fifth semiconductor area having a high impurity concentration of the first conductivity type is formed on the part of the surface of the second semiconductor area in spaced relation to the forth semiconductor area.

Abstract: A lateral static induction transistor suited for use as a picture element of a solid state imaging device. The lateral static induction transistor includes a semiconductor substrate of a first conduction type of P type or N type, a first epitaxial layer of the same conduction type as the first conduction type which is formed on the semiconductor substrate, a second epitaxial layer of a second conduction type opposite to the first conduction type which is formed on the first epitaxial layer, a source zone and a plurality of drain zones which are formed in the second epitaxial layer near the surface thereof, and a plurality of gates each thereof being formed so as to partially lie over the source zone and one of the drain zones on the second epitaxial layer through an insulating layer.

Abstract: The present invention is to provide a static induction semiconductor device with a distributed main electrode structure and a static induction semiconductor device with a static induction main electrode shorted structure where the main electrode region is composed of regions of higher and lower impurity densities relative to each other and formed partly in contact with the lower impurity density region as well, and alternatively a static induction short-circuit region opposite in conductivity type to the main electrode region is formed in the lower impurity density region surrounded by the higher impurity density region.

Abstract: A static induction semiconductor device has a low-resistance drain region, a high-resistance layer disposed on the drain region, a low-resistance source region spaced from the high-resistance layer, a low-resistance gate region disposed in the high-resistance layer, and a hetero layer disposed in an interface between the high-resistance layer and the source region and an interface between the gate region and a surface protective layer on the gate and source regions. The hetero layer, which may be made of AlGaAs, has a band gap larger than a semiconductor crystal such as GaAs of the drain, source, and gate regions. The static induction semiconductor device has a low resistance turned on and can operate in a bipolar mode.

Abstract: A semiconductor device comprises a first electrode buried in one main face of a substrate and surrounded by a first insulator, a field oxide film covering the surface of the first electrode, a semiconductor layer connected with the first electrode, a second insulator covering the surface of the semiconductor layer, a second electrode connected with the semiconductor layer, a gate electrode connected with the semiconductor layer between the second insulator and the field oxide film, and an outgoing electrode connected with the first electrode.

Abstract: A semiconductor device including a normally-on SI thyristor, and a MOSFET connected in cascade with the SI thyristor. The gate of the SI thyristor is connected to the source of the MOSFET. This arrangement makes it possible to turn the device on and off by controlling only the voltage gate of the MOSFET, obviating a current to maintain the on state of the device. The device needs little driving energy and has a low on state voltage and a high switching speed. It can readily be integrated into one chip.

Abstract: The present invention has for its object to provide a planar MOS-controlled thyristor of improved main thyristor turn-ON characteristics and a vertical MOS-controlled thyristor of improved main thyristor turn-ON characteristics and increased integration density. In the planar MOS-controlled thyristor a p-channel MOSFET for turning OFF the main thyristor and an n-channel MOSFET for turning it ON are provided in an integrated form and a channel is provided between the cathode region and a high resistance layer. The current in the channel can be controlled by the base or gate potential through utilization of the J-FET or static induction effect. In the vertical MOS-controlled thyristor a vertical p-channel MOSFET for turning OFF the main thyristor and a vertical n-channel MOSFET for turning it ON are provided in an integrated form and a base layer or channel is provided between the cathode region and a high resistivity layer.

Abstract: In a MOS controlled power device, or MOS composite a static induction thyristor, an static induction thyristor (SI thyristor) unit, a MOS transistor connected in cascode relation to the SI thyristor unit and a voltage regulation element are merged onto the single monolithic chip. The SI thyristor unit has a cathode region of first conductivity type having high impurity concentration, an anode and a gate regions of second conductivity type having high impurity concentration, and a channel region of first conductivity type having low impurity concentration. The MOS transistor has a drain region which is the same region as the cathode region, a well or a base of second conductivity type formed adjacent to the channel region of the SI thyristor unit, and a source region of first conductivity type having high impurity concentration. The source region is formed within the well or above the base.

Abstract: A static induction device (SI device) at least shares a structure in which an SI thyristor, an IGT and a capacitor are merged onto the single monolithic chip. The SI thyristor has a cathode, an anode and a gate regions, and a channel. The IGT has a well on a surface of the channel, a source and drain regions within the well, a gate insulating film on the well, and a gate electrode on the gate insulating film. The capacitor comprises the gate region of the SI thyristor, the gate insulating film on the gate region, and the gate electrode. The cathode and the drain region are connected to each other through a high-conductive electrode.

Abstract: An emitter switched thyristor with buried dielectric layer includes a contiguous P-N-P-N series of semiconductor regions between an anode contact and cathode contact. These regions correspond to an anode region of second conductivity type, a first base region of first conductivity type, a second base region of second conductivity type on the first base region, and a floating emitter region contacting the second base region and forming a P-N junction therewith. In addition, a field effect transistor is also provided between the cathode contact and the floating emitter for controlling turn-on and turn-off. An insulating region is also provided between the cathode region and the second base region and prevents the formation of a parasitic thyristor between the cathode contact and the anode contact. The insulating region preferably includes a buried dielectric layer selected from the group consisting of SiO.sub.2, Si.sub.3 N.sub.4, Al.sub.2 O.sub.3 and MgAl.sub.2 O.sub.4.

Abstract: A static induction type semiconductor device of a surface gate type, includes a source region, gate region and drain region. A channel region is formed between the drain region and the source region, such that when a bias potential is applied between the gate region and the source region, carriers flow to the drain region from the source region via the channel region. A source electrode is provided on the semiconductor layer. A source contact region is provided between the source electrode and the source region to establish electrical connection therebetween. The source contact region is segmented into a plurality of smaller regions or sections whose total area is smaller than the area of the corresponding portion of the source region, for improving the current gain, and for preventing or significantly reducing local current concentration.

Abstract: In a semiconductor apparatus and method for producing the same where an upper surface of a semiconductor chip having a thick film electrode is coated with a passivation film, the semiconductor chip being molded with a resin mold such as a power SIT, a conductive film made of a doped polysilicon, a metal material, or the like and which has a thickness of for example 3000 angstroms or more is circumferentially disposed from a bottom circumference of the thick film electrode to a part of region between a field oxide film and a passivation film so as to effectively prevent cracks in the passivation film caused by a cyclic temperature test from extending into the field oxide film.

Abstract: A semiconductor thyristor of the Static Induction type having a split-gate structure, e.g., driving gates and non-driving gates, for controlling cathode-anode current flow. The split-gate structure comprises a plurality of primary driving gates formed in recesses of the channel region which respond to an external control signal for providing primary current control, and a plurality of secondary non-driving gates which are influenced by electric fields in the channel region extant during thyristor operation for providing secondary current control. In operation, the driving and non-driving gates coact so that the non-driving gates, having an induced potential lower than the potential applied to the driving gates, absorb charge carriers injected in the channel during thyristor operation.

Abstract: A semiconductor thyristor of the Static Induction type having a split-gate structure, e.g., driving gates and non-driving gates, for controlling cathode-anode current flow. The split-gate structure comprises a plurality of primary driving gates formed in recesses of the channel region which respond to an external control signal for providing primary current control, and a plurality of secondary non-driving gates which are influenced by electric fields in the channel region extant during thyristor operation for providing secondary current control. In operation, the driving and non-driving gates coact so that the non-driving gates, having an induced potential lower than the potential applied to the driving gates, absorb charge carriers injected in the channel during thyristor operation.