With Extended Latchup Current Level (e.g., Comfet Device) Patents (Class 257/139)
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Patent number: 10186609Abstract: According to one embodiment, a semiconductor device 100 includes a semiconductor substrate 1 including a first principal surface and a second principal surface, an emitter electrode 46, a gate wiring 49, a collector electrode 43, a first unit cell region 10 that is extended along one direction in a plane parallel to the first principal surface, and a second unit cell region 20 that is extended along one direction, in which the semiconductor substrate 1 of the first unit cell region 10 and the second unit cell region 20 includes an N? type drift layer 39, an N type hole barrier layer 38, a trench electrode 13, a P type body layer 36, an insulating film 35, an N type field stop layer 41, and a P+ type collector layer 42, and the second unit cell region 20 includes an N type cathode layer 47 that is fitted into the collector layer 42 and is extended along one direction.Type: GrantFiled: September 15, 2017Date of Patent: January 22, 2019Assignee: Renesas Electronics CorporationInventor: Kazuhiro Yamada
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Patent number: 10186606Abstract: A semiconductor device includes: a semiconductor substrate having a drift layer; a base layer on the drift layer; a collector layer and a cathode layer arranged on the drift layer opposite to the base layer; multiple trenches penetrating the base layer and reaching the drift layer, and arranged along one direction; a gate electrode arranged in each trench via a gate insulating film; and an emitter region arranged in a surface portion of the base layer, and contacting with each trench. The semiconductor substrate includes an IGBT region having the emitter region and an FWD region in which an injection limiting region and a contact region are arranged in the surface portion of the base layer alternately along the one direction.Type: GrantFiled: January 13, 2016Date of Patent: January 22, 2019Assignee: DENSO CORPORATIONInventor: Masakiyo Sumitomo
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Patent number: 10181509Abstract: A high power vertical insulated-gate switch is described that includes an active region, containing a cell array, and a surrounding termination region. The termination region is for at least the purpose of controlling a breakdown voltage and does not contain any switching cells. Assuming the anode is the silicon substrate (p-type), it is desirable to have good hole injection efficiency from the substrate in the active region in the device's on-state. Therefore, the substrate should be highly doped (p++) in the active region. It is desirable to have poor hole injection efficiency in the termination region so that there is a minimum concentration of holes in the termination region when the switch is turned off. Various doping techniques are disclosed that cause the substrate to efficiency inject holes into the active region but inefficiently inject holes into the termination region during the on-state.Type: GrantFiled: August 4, 2016Date of Patent: January 15, 2019Assignee: PAKAL TECHNOLOGIES, LLCInventors: Richard A. Blanchard, Hidenori Akiyama, Vladimir Rodov, Woytek Tworzydlo
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Patent number: 10177248Abstract: A semiconductor device includes a semiconductor body including a base region and two semiconductor mesas separated from each other by an insulated trench gate structure extending from a first side into the base region, and including a dielectric layer separating a gate electrode from the semiconductor body. Each semiconductor mesa includes, in a cross-section perpendicular to the first side, a body region forming a pn-junction with the base region, a latch-up-safety region of the same conductivity type as the body region arranged between the body region and the first side, and having a higher doping concentration than the body region, and an emitter region between the dielectric layer and the latch-up-safety region and forming a pn-junction with the body region. At least one semiconductor mesa includes an emitter contact arranged between the emitter region and the latch-up-safety region and forming with the latch-up-safety and emitter regions an Ohmic contact.Type: GrantFiled: September 15, 2017Date of Patent: January 8, 2019Assignee: Infineon Technologies Austria AGInventors: Matteo Dainese, Erich Griebl
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Patent number: 10176994Abstract: A p-type base layer (2) is formed on a surface of an n-type silicon substrate (1). First and second n+-type buffer layers (8,9) 9 are formed on a back surface of the n-type silicon substrate (1). The first n+-type buffer layer (8) is formed by a plurality of implantations of protons at different accelerating voltages and has a plurality of peak concentrations with different depths from the back surface of the n-type silicon substrate (1). The second n+-type buffer layer (9) is formed by an implantation of a phosphorus. A position of a peak concentration of the phosphorus is shallower from the back surface of the n-type silicon substrate (1) than positions of peak concentrations of the protons. The peak concentration of the phosphorus is higher than the peak concentrations of the protons. A concentration of the protons is higher than a concentration of the phosphorus at the positions of the peak concentrations of the protons.Type: GrantFiled: March 13, 2015Date of Patent: January 8, 2019Assignee: Mitsubishi Electric CorporationInventors: Kenji Suzuki, Atsushi Narazaki, Ryu Kamibaba, Yusuke Fukada, Katsumi Nakamura
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Patent number: 10163890Abstract: A semiconductor device provided herein includes: a semiconductor substrate; an upper main electrode located above the semiconductor substrate; a sense anode electrode located above the semiconductor substrate; a first resistance layer located above the semiconductor substrate, having resistivity higher than resistivities of the upper main electrode and the sense anode electrode, and connecting the upper main electrode and the sense anode electrode; and a lower main electrode located below the semiconductor substrate. The semiconductor substrate includes a switching element and a sense diode. The switching element is connected between the upper main electrode and the lower main electrode. The sense diode includes a p-type first anode region connected to the sense anode electrode and an n-type first cathode region connected to the lower main electrode.Type: GrantFiled: January 11, 2018Date of Patent: December 25, 2018Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Masaru Senoo, Masanori Miyata
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Patent number: 10157982Abstract: A field-effect semiconductor device includes a semiconductor body having a first semiconductor region of a first conductivity type, a first side, an edge delimiting the semiconductor body in a direction substantially parallel to the first side, an active area, and a peripheral area arranged between the active area and the edge. A first metallization is arranged on the first side, and a second metallization is arranged opposite the first metallization and in Ohmic connection with the first semiconductor region. In the active area, the semiconductor body further includes: a plurality of drift portions of the first conductivity type alternating with compensation regions of a second conductivity type, the drift portions being in Ohmic connection with the first semiconductor region, the compensation regions being in Ohmic connection with the first metallization and having in a vertical direction perpendicular to the first side a vertical extension.Type: GrantFiled: August 22, 2017Date of Patent: December 18, 2018Assignee: Infineon Technologies Austria AGInventors: Daniel Tutuc, Christian Fachmann, Franz Hirler, Maximilian Treiber
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Patent number: 10153339Abstract: A semiconductor device includes a common doping region located within a semiconductor substrate of the semiconductor device. The common doping region includes a first portion. A maximal doping concentration within the first portion is higher than 1·1015 cm?3. The common doping region includes a second portion. A minimal doping concentration within the second portion is lower than 50% of the maximal doping concentration within the first portion of the common doping region. The common doping region includes a third portion. A minimal doping concentration within the third portion is more than 30% higher than the minimal doping concentration within the second portion. The second portion of the common doping region is located vertically between the first portion of the common doping region and the third portion of the common doping region.Type: GrantFiled: September 19, 2017Date of Patent: December 11, 2018Assignee: Infineon Technologies AGInventors: Stephan Voss, Alexander Breymesser, Hans-Joachim Schulze, Yvonne Gawlina-Schmidl
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Patent number: 10153269Abstract: A low dynamic resistance, low capacitance diode of a semiconductor device includes a heavily-doped n-type substrate. A lightly-doped n-type layer 1 micron to 5 microns thick is disposed on the n-type substrate. A lightly-doped p-type layer 3 microns to 8 microns thick is disposed on the n-type layer. The low dynamic resistance, low capacitance diode, of the semiconductor device includes a p-type buried layer, with a peak dopant density above 1×1017 cm?3, extending from the p-type layer through the n-type layer to the n-type substrate. The low dynamic resistance, low capacitance diode also includes an n-type region disposed in the p-type layer, extending to a top surface of the p-type layer.Type: GrantFiled: August 17, 2017Date of Patent: December 11, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Andrew D. Strachan, Alexei Sadovnikov, Gang Xue, Dening Wang
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Patent number: 10141421Abstract: A device includes a semiconductor layer of a first conductivity type, and a first and a second body region over the semiconductor layer, wherein the first and the second body regions are of a second conductivity type opposite the first conductivity type. A doped semiconductor region of the first conductivity type is disposed between and contacting the first and the second body regions. A gate dielectric layer is disposed over the first and the second body regions and the doped semiconductor region. A first and a second gate electrode are disposed over the gate dielectric layer, and overlapping the first and the second body regions, respectively. The first and the second gate electrodes are physically separated from each other by a region, and are electrically interconnected. The region between the first and the second gate electrodes overlaps the doped semiconductor region.Type: GrantFiled: June 5, 2017Date of Patent: November 27, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Wai Ng, Hsueh-Liang Chou, Ruey-Hsin Liu, Po-Chih Su
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Patent number: 10141455Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, an insulating region, and a third semiconductor region of the first conductivity type. The first semiconductor region is provided between the first electrode and the second electrode, and is in contact with the first electrode. The second semiconductor region is provided between the first semiconductor region and the second electrode. The second semiconductor region is in contact with the second electrode. The insulating region extends in a direction from the second electrode toward the first semiconductor region. The insulating region is in contact with the second electrode. The third semiconductor region is provided between the second semiconductor region and the insulating region.Type: GrantFiled: March 16, 2017Date of Patent: November 27, 2018Assignee: Kabushiki Kaisha ToshibaInventors: Tsuneo Ogura, Shinichiro Misu, Tomoko Matsudai, Norio Yasuhara
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Patent number: 10128360Abstract: A method of producing a semiconductor device is disclosed in which, after proton implantation is performed, a hydrogen-induced donor is formed by a furnace annealing process to form an n-type field stop layer. A disorder generated in a proton passage region is reduced by a laser annealing process to form an n-type disorder reduction region. As such, the n-type field stop layer and the n-type disorder reduction region are formed by the proton implantation. Therefore, it is possible to provide a stable and inexpensive semiconductor device which has low conduction resistance and can improve electrical characteristics, such as a leakage current, and a method for producing the semiconductor device.Type: GrantFiled: December 11, 2017Date of Patent: November 13, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventors: Masayuki Miyazaki, Takashi Yoshimura, Hiroshi Takishita, Hidenao Kuribayashi
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Patent number: 10128330Abstract: A semiconductor device having a novel buried junction architecture. The semiconductor device may have three terminals and a drift region between two of the terminals. The drift region includes an upper drift layer, a lower drift layer, and a buried junction layer between the upper and lower drift layers, wherein the upper and lower drift layers have a first type of doping. The buried junction layer comprises an interspersed pattern of a first material and a second material, the first material having a second type of doping opposite the first type of doping and the second material having the first type of doping and having a different doping concentration than the upper and lower drift layers.Type: GrantFiled: July 20, 2017Date of Patent: November 13, 2018Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Ralph N. Wall, Meng-Chia Lee
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Patent number: 10128359Abstract: A semiconductor device in which short circuit capability can be improved while decline in overall current capability is suppressed. In the semiconductor device, a plurality of IGBTs (insulated gate bipolar transistors) arranged in a row in one direction over the main surface of a semiconductor substrate include an IGBT located at an extreme end in the one direction and an IGBT located more centrally than the IGBT located at the extreme end. The current capability of the IGBT located at the extreme end is higher than the current capability of the IGBT located centrally.Type: GrantFiled: January 13, 2017Date of Patent: November 13, 2018Assignee: Renesas Electronics CorporationInventors: Mikio Tsujiuchi, Tetsuya Nitta
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Patent number: 10121850Abstract: Provided is a power semiconductor device comprising a gate electrode in a trench of a substrate; a body region having a first conductivity type on one side of the gate electrode; a source region having a second conductivity type adjacent to the gate electrode; a floating region having a first conductivity type on the other side of the gate electrode; an edge doped region having a first conductivity type spaced apart from the floating region and electrically connected to the source region; an edge junction isolation region having a second conductivity type between the floating region and the edge doped region; and a drift region having a second conductivity type below the floating, edge doped, and edge junction isolation regions, wherein the doping concentration of a second conductivity type in the edge junction isolation region is higher than the doping concentration of a second conductivity type in the drift region.Type: GrantFiled: June 2, 2017Date of Patent: November 6, 2018Assignee: HYUNDAI AUTRON CO., LTDInventors: Young Joon Kim, Hyuk Woo, Tae Yeop Kim, Han Sin Cho, Tae Young Park, Ju Hwan Lee
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Patent number: 10121866Abstract: Provided is a semiconductor device having an RC-IGBT structure, the semiconductor device comprising an FWD (Free Wheel Diode) region and an IGBT (Insulated Gate Bipolar Transistor) region. Provided is a semiconductor device comprising: a semiconductor substrate; a transistor section formed on the semiconductor substrate; a diode section formed on the semiconductor substrate and including a lifetime killer at a front surface side of the semiconductor substrate; a gate runner provided between the transistor section and the diode section and electrically connected to a gate of the transistor section.Type: GrantFiled: January 31, 2017Date of Patent: November 6, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventor: Tatsuya Naito
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Patent number: 10109733Abstract: In a semiconductor device, in a gate insulating film which is formed on/over an inner wall of a trench, the film thickness of a part of a gate insulating film formed so as to cover a corner of the trench is made thicker than the film thickness of a part of the gate insulating film part formed on/over a side face of the trench.Type: GrantFiled: June 19, 2017Date of Patent: October 23, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yasunori Yamashita, Koichi Arai, Kenichi Hisada
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Patent number: 10103221Abstract: The present examples relate to a power semiconductor device. The present examples also relate to a power semiconductor device that maintains a breakdown voltage and reduces a gate capacitance through improving the structure of an Injection Enhanced Gate Transistor (IEGT), and thereby reduces strength of an electric field compared to alternative technologies. Accordingly, the present examples provide a power semiconductor device with a small energy consumption and with an improved switching functionality.Type: GrantFiled: May 18, 2017Date of Patent: October 16, 2018Assignee: Magnachip Semiconductor, Ltd.Inventors: In Su Kim, Jeong Hwan Park, Seung Sik Park, Ha Yong Yang
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Patent number: 10096699Abstract: A field-stop reverse conducting insulated gate bipolar transistor and a manufacturing method therefor. The transistor comprises a terminal structure (200) and an active region (100). An underlayment of the field-stop reverse conducting insulated gate bipolar transistor is an N-type underlayment, the back surface of the underlayment is provided with an N-type electric field stop layer (1), one surface of the electric field stop layer departing from the underlayment is provided with a back-surface P-type structure (10), and the surface of the back-surface P-type structure is provided with a back-surface metal layer (12). A plurality of notches (11) which penetrate through the back-surface P-type structure (10) from the back-surface metal layer (12) to the electric field stop layer (1) are formed in the active region (100), and metals of the back-surface metal layer (12) are filled into the notches (11) to form a metal structure which extends into the electric field stop layer (1).Type: GrantFiled: June 5, 2014Date of Patent: October 9, 2018Assignee: CSMC Technologies Fab1 Co., Ltd.Inventors: Shuo Zhang, Qiang Rui, Genyi Wang, Xiaoshe Deng
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Patent number: 10096680Abstract: A silicon carbide semiconductor device, including a silicon carbide semiconductor structure, an insulated gate structure including a gate insulating film contacting the silicon carbide semiconductor structure and a gate electrode formed on the gate insulating film, an interlayer insulating film covering the insulated gate structure, a metal layer provided on the interlayer insulating film for absorbing or blocking hydrogen, and a main electrode provided on the metal layer and electrically connected to the silicon carbide semiconductor structure.Type: GrantFiled: March 24, 2017Date of Patent: October 9, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventors: Naoki Kumagai, Takashi Tsutsumi, Yoshiyuki Sakai, Yasuhiko Oonishi, Takumi Fujimoto, Kenji Fukuda, Shinsuke Harada, Mitsuo Okamoto
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Patent number: 10083957Abstract: According to one embodiment, a semiconductor device includes a first electrode, first regions, second regions, an eighth semiconductor region, a ninth semiconductor region of the second conductivity type, a tenth semiconductor region, second electrodes, and a third electrode. Each first region includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a fourth semiconductor region, and a gate electrode. The first regions and the second regions alternate in the second direction. Each of the second regions includes a fifth semiconductor region, a sixth semiconductor region, and a seventh semiconductor region. The eighth semiconductor region is provided between the first semiconductor regions and between the fifth semiconductor regions. The eighth semiconductor region is electrically connected to the first semiconductor regions. The third electrode is provided on the tenth semiconductor region with a first insulating layer interposed.Type: GrantFiled: September 8, 2017Date of Patent: September 25, 2018Assignee: Kabushiki Kaisha ToshibaInventors: Tomohiro Tamaki, Kazutoshi Nakamura, Ryohei Gejo
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Patent number: 10062761Abstract: A method for manufacturing a semiconductor device includes steps of forming a trench in a surface of a semiconductor substrate of a first conductivity type in a depth direction; forming a conductive layer in the trench, with a first insulating film interposed therebetween; dividing the conductive layer into a gate electrode and an in-trench wiring layer which face each other in the trench and filling a gap between the gate electrode and the in-trench wiring layer with a second insulating film; introducing second-conductivity-type impurities into the entire surface of the semiconductor substrate to form a channel forming region of a second conductivity type; and selectively forming a main electrode region of the first conductivity type in a portion of the channel forming region which is provided along an opening portion of the trench so as to come into contact with the opening portion.Type: GrantFiled: June 4, 2015Date of Patent: August 28, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventor: Atsushi Yoshimoto
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Patent number: 10062755Abstract: Semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In one embodiment, a termination structure is formed in the termination area and includes an array of termination cells formed in the termination area, the array of termination cells including a first termination cell at an interface to the active area to a last termination cell, each termination cell in the array of termination cells being formed in a mesa of the first semiconductor layer and having a first width; and an end termination cell being formed next to the last termination cell in the termination area, the end termination cell being formed in an end mesa of the first semiconductor layer and having a second width greater than the first width.Type: GrantFiled: January 10, 2018Date of Patent: August 28, 2018Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Hamza Yilmaz, Xiaobin Wang, Anup Bhalla, John Chen, Hong Chang
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Patent number: 10043865Abstract: A p anode layer is formed on one main surface of an n? drift layer. N+ cathode layer having an impurity concentration more than that of the n? drift layer is formed on the other main surface. An anode electrode is formed on the surface of the p anode layer. A cathode electrode is formed on the surface of the n+ cathode layer. N-type broad buffer region having a net doping concentration more than the bulk impurity concentration of a wafer and less than the n+ cathode layer and p anode layer is formed in the n? drift layer. Resistivity ?0 of the n? drift layer satisfies 0.12V0??0?0.25V0 with respect to rated voltage V0. Total amount of net doping concentration of the broad buffer region is equal to or more than 4.8×1011 atoms/cm2 and equal to or less than 1.0×1012 atoms/cm2.Type: GrantFiled: December 28, 2015Date of Patent: August 7, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventors: Michio Nemoto, Takashi Yoshimura
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Patent number: 10041993Abstract: The use of a netlist or other database containing topological information of an electrical circuit comprising a multiplicity of components which are to undergo safe operating area (SOA) checking, permits a relationship between recorded SOA errors to be established. Knowing how such errors may be interdependent can assist designers in deciding which errors should be rectified first. The relationship between the recorded errors relating to two connected components may be modified by a confidence factor based on elapsed time between the occurrence of the two recorded errors.Type: GrantFiled: September 5, 2013Date of Patent: August 7, 2018Assignee: NXP USA, Inc.Inventors: Xavier Hours, Aldric L'Hernault, Christophe Oger, Mehul Shroff
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Patent number: 10032896Abstract: The surface of an interlayer insulating film formed over an emitter coupling portion and the surface of an emitter electrode formed over the interlayer insulating film are caused to have a gentle shape, in particular, at the end of the emitter coupling portion, by forming the emitter coupling portion over a main surface of a semiconductor substrate and integrally with trench gate electrodes in order to form a spacer over the sidewall of the emitter coupling portion. Thereby, stress is dispersed, not concentrated in an acute angle portion of the emitter coupling portion when an emitter wire is coupled to the emitter electrode (emitter pad), and hence occurrence of a crack can be suppressed. Further, by forming the spacer, the concavities and convexities to be formed in the surface of the emitter electrode can be reduced, whereby the adhesiveness between the emitter electrode and the emitter wire can be improved.Type: GrantFiled: October 16, 2017Date of Patent: July 24, 2018Assignee: RENESAS ELECTRONICS COPRORATIONInventor: Hitoshi Matsuura
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Patent number: 10002807Abstract: A semiconductor device includes a semiconductor substrate on which plural gate electrodes are juxtaposed to each other, plural gate wirings formed on the semiconductor substrate, plural gate pads, a first pad, and a second pad. The adjacent gate electrodes define plural cells, and the plural cells include plural transistor cells. The plural gate electrodes are partitioned into plural types by the plural gate wirings. The plural transistor cells are partitioned into plural types according to a combination of the defined gate electrodes.Type: GrantFiled: October 21, 2013Date of Patent: June 19, 2018Assignee: DENSO CORPORATIONInventor: Yasushi Ookura
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Patent number: 9997476Abstract: A multi-die package is manufactured by attaching a first semiconductor die made of a first semiconductor material to a thermally conductive flange via a first die attach material, and attaching a second semiconductor die to the same thermally conductive flange as the first semiconductor die via a second die attach material. The second semiconductor die is made of a second semiconductor material different than the first semiconductor material. The first semiconductor die is held in place by the first die attach material during attachment of the second semiconductor die to the flange. Leads are attached to the thermally conductive flange or to an insulating member secured to the flange. The leads provide external electrical access to the first and second semiconductor dies.Type: GrantFiled: October 30, 2015Date of Patent: June 12, 2018Assignee: Infineon Technologies AGInventors: Xikun Zhang, Dejiang Chang, Bill Agar, Michael Lefevre, Alexander Komposch
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Patent number: 9997622Abstract: In a method of further enhancing the performance of a narrow active cell IE type trench gate IGBT having the width of active cells narrower than that of inactive cells, it is effective to shrink the cells so that the IE effects are enhanced. However, when the cells are shrunk simply, the switching speed is reduced due to increased gate capacitance. A cell formation area of the IE type trench gate IGBT is basically composed of first linear unit cell areas having linear active cell areas, second linear unit cell areas having linear hole collector areas and linear inactive cell areas disposed therebetween.Type: GrantFiled: February 10, 2017Date of Patent: June 12, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Hitoshi Matsuura
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Patent number: 9997593Abstract: A trench type power semiconductor device with improved breakdown voltage and UIS performance and a method for preparation the device are disclosed. The trench type power semiconductor device includes a first contact hole formed in a mesa in the active area and a second contact hole formed in a mesa in an active to termination intermediate area, where the first contact hole is deeper and wider than the second contact hole. The method comprises the steps of providing a semiconductor substrate, etching an epitaxial layer, depositing a conductive material, depositing an insulation passivation layer and etching through the insulation passivation layer.Type: GrantFiled: July 10, 2017Date of Patent: June 12, 2018Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.Inventors: Yongping Ding, Hamza Yilmaz, Xiaobin Wang, Madhur Bobde
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Patent number: 9978857Abstract: To improve the performance of a semiconductor device having an IGBT. A p+-type collector layer is formed on the back surface side of a semiconductor substrate. A back electrode is formed over the back surface of the semiconductor substrate. Within the semiconductor substrate, an n?-type drift region is formed over the p+-type collector layer, and a first IGBT cell region and a second IGBT cell region are formed on the surface side of the semiconductor substrate. An embedded insulating film is formed on the surface side of the semiconductor substrate between the first IGBT cell region and the second IGBT cell region. An interlayer insulating film is formed over the first IGBT cell region, the second IGBT cell region, and the embedded insulating film. An emitter electrode is formed over the interlayer insulating film.Type: GrantFiled: January 27, 2017Date of Patent: May 22, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Hajime Tsuyuki
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Patent number: 9966410Abstract: An image sensor circuit, comprises: a photo sensing circuit including a photo sensitive device for sensing a light signal to generate a photo sensing signal at a photo sensing output node; a charge storage device, coupled to an integration node; an integration switch coupled between the photo sensing output node and the integration node, operating according to an integration control signal; and a reset circuit coupled between a voltage supply and the integration node, operating according to a reset control signal and a read control signal, wherein the integration node includes an integration voltage. In a reset time period, the integration switch is conductive, and the reset circuit generates a reset signal on the integration node to bias the photo sensitive device through the integration switch to an active state and to charge the charge storage device such that the integration voltage is determined to be at a reset level.Type: GrantFiled: April 4, 2017Date of Patent: May 8, 2018Assignee: PixArt Imaging (Penang) SDN. BHD.Inventor: Wooi Kip Lim
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Patent number: 9960267Abstract: In a semiconductor device provided with a MOSFET part and a gate pad part defined on a semiconductor substrate which is formed by laminating a low resistance semiconductor layer and a drift layer, the gate pad part includes: the low resistance semiconductor layer; the drift layer formed on the low resistance semiconductor layer; a poly-silicon layer constituting a conductor layer and a gate pad electrode formed above the drift layer over the whole area of the gate pad part with a field insulation layer interposed therebetween; and a gate oscillation suppressing structure where a p-type diffusion region electrically connected with the a source electrode layer and a p-type impurity non-diffusion region are alternately formed on a surface of the drift layer.Type: GrantFiled: March 31, 2014Date of Patent: May 1, 2018Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventor: Nobuki Miyakoshi
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Patent number: 9960167Abstract: A method for forming a semiconductor device includes providing a substrate having a plurality of memory cells formed therein; forming an insulating layer on the substrate; forming a plurality of openings in the insulating layer and exposing a portion of the memory cells; forming a conductive portion and a metal layer in the openings; removing a portion of the metal layer to form a plurality of first metal portions and a plurality of second metal portions that the first metal portion and the conductive portion form a first connecting structure, and the second metal portion and the conductive portion form a second connecting structure; forming a passivation layer on the first connecting structures; and forming a plurality of first storage nodes and dummy nodes on the substrate and the first storage nodes and the dummy nodes are electrically connected to the second connecting structures and the first connecting structures respectively.Type: GrantFiled: August 16, 2017Date of Patent: May 1, 2018Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Chien-Ting Ho, Li-Wei Feng, Ying-Chiao Wang, Yu-Chieh Lin
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Patent number: 9960269Abstract: A semiconductor device according to one embodiment includes a semiconductor substrate having a main surface and a back surface opposite to the main surface, a drift region of a first conductivity type, a base region of a second conductivity type, a source region of the first conductivity type, and a gate electrode. The semiconductor substrate has a trench in the main surface. The gate electrode is formed in the trench. A distribution of an impurity concentration in the base region has a plurality of peak values along a direction of depth from the main surface toward the back surface, and the number of peak values is four or more.Type: GrantFiled: February 1, 2017Date of Patent: May 1, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Hiroshi Yanagigawa, Hiroyoshi Kudou
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Patent number: 9960165Abstract: Provided is a technology for further reducing a loss in a semiconductor device including a semiconductor substrate in which an IGBT region and a diode region are provided. This semiconductor device includes a semiconductor substrate in which at least one IGBT region and at least one diode region are provided. The IGBT region and the diode region are adjacent to each other in a predetermined direction in a plan view of the semiconductor substrate. In the plan view of the semiconductor substrate, a first boundary plane where the collector region and the cathode region are adjacent is shifted from a second boundary plane where the IGBT region and the diode region are adjacent on the front surface side of the semiconductor substrate either in a direction from the cathode region toward the collector region or in a direction from the collector region toward the cathode region.Type: GrantFiled: November 5, 2013Date of Patent: May 1, 2018Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Yuki Horiuchi, Satoru Kameyama
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Patent number: 9953969Abstract: A semiconductor power device having shielded gate structure in an active area and having ESD clamp diode with two poly-silicon layer process is disclosed, wherein: the shielded gate structure comprises a first poly-silicon layer to serve as a shielded electrode and a second poly-silicon layer to serve as a gate electrode, and the ESD clamp diode formed between two protruding electrodes is also formed by the first poly-silicon layer. A mask specially used to define the ESD clamp diode portion is saved.Type: GrantFiled: March 25, 2016Date of Patent: April 24, 2018Assignee: FORCE MOS TECHNOLOGY CO., LTD.Inventor: Fu-Yuan Hsieh
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Patent number: 9953971Abstract: An insulated gate bipolar transistor (IGBT) includes a gate trench, an emitter trench, and an electrically insulative layer coupled to the emitter trench and the gate trench and electrically isolating the gate trench from an electrically conductive layer. A contact opening in the electrically insulative layer extends into the emitter trench and the electrically conductive layer electrically couples with the emitter trench therethrough. A P surface doped (PSD) region and an N surface doped (NSD) region are each located between the electrically conductive layer and a plurality of semiconductor layers of the IGBT and between the gate trench and the emitter trench. The electrically conductive layer electrically couples to the plurality of semiconductor layers through the PSD region and/or the NSD region.Type: GrantFiled: April 18, 2017Date of Patent: April 24, 2018Assignee: Semiconductor Components Industries, LLCInventor: Takumi Hosoya
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Patent number: 9941362Abstract: A method of manufacturing a silicon carbide semiconductor device. The method includes providing an n-type semiconductor substrate having first and second principal surfaces, introducing an impurity from a first principal surface of the semiconductor substrate at a first position, activating the impurity to form a diffusion layer in the semiconductor substrate at a second position, implanting protons at a third position that is deeper from the first principal surface than the first position, the protons generating crystal defects in a region through which the protons pass, converting by thermal treating the protons into hydrogen induced donors to form an n-type field stop layer at a fourth position deeper from the first principal surface than the second position, reducing by the thermal treating the generated crystal defects to form an n-type crystal defect reduction region, and forming an electrode on the second principal surface after implanting the protons.Type: GrantFiled: October 26, 2016Date of Patent: April 10, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventors: Hidenao Kuribayashi, Masayuki Miyazaki
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Patent number: 9941383Abstract: Integrated circuits are presented having high voltage IGBTs with integral emitter shorts and fabrication processes using wafer bonding or grown epitaxial silicon for controlled drift region thickness and fast switching speed.Type: GrantFiled: May 31, 2016Date of Patent: April 10, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jacek Korec, John Manning Savidge Neilson, Sameer Pendharkar
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Patent number: 9941134Abstract: A method for providing a uniform recess depth between different fin gap sizes includes depositing a dielectric material between fins on a substrate. Etch lag is tuned for etching the dielectric material between narrow gaps faster than the dielectric material between wider gaps such that the dielectric material in the narrow gaps reaches a target depth. An etch block is formed in die narrow gaps. The wider gaps are etched to the target depth. The etch block is removed.Type: GrantFiled: May 1, 2017Date of Patent: April 10, 2018Assignee: International Business Machines CorporationInventors: Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo, Jay W. Strane
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Patent number: 9941395Abstract: An insulated gate semiconductor device includes a region that is provided between trenches in which a gate electrode is filled through a gate insulating film in a surface layer of a substrate, includes a p base region and an n+ emitter region, and comes into conductive contact with an emitter electrode and a p-type floating region that is electrically insulated by an insulating film which is interposed between the p-type floating region and the emitter electrode. The p-type floating region is deeper than the trench and has a lower impurity concentration than the p base region.Type: GrantFiled: April 9, 2014Date of Patent: April 10, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventor: Yuichi Onozawa
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Patent number: 9923091Abstract: An n-channel power MOS transistor having a gate electrode is formed in an element formation region defined in a semiconductor substrate. A p-type guard ring region is formed in a terminal region. A plurality of p-type column regions are formed from the bottom of the p-type base region to a further deeper position. The column region located in the outermost periphery and the p?-type guard ring region are spaced apart from each other by a distance. A gate electrode lead-out portion electrically coupled to the gate electrode is formed in the p?-type guard ring region.Type: GrantFiled: March 10, 2017Date of Patent: March 20, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Hiroyoshi Kudou, Taro Moriya
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Patent number: 9911889Abstract: Certain embodiments of the present invention may be directed to a transistor structure. The transistor structure may include a semiconductor substrate. The semiconductor substrate may include a drift region, a collector region, an emitter region, and a lightly-doped/undoped region. The lightly-doped/undoped region may be lightly-doped and/or undoped. The transistor structure may also include a heterostructure. The heterostructure forms a heterojunction with the lightly-doped/undoped region. The transistor structure may also include a collector terminal. The collector terminal is in contact with the collector region. The transistor structure may also include a gate terminal. The gate terminal is in contact with the heterostructure. The transistor structure may also include an emitter terminal. The emitter terminal is in contact with the lightly-doped/undoped region and the emitter region.Type: GrantFiled: September 8, 2017Date of Patent: March 6, 2018Assignees: QATAR UNIVERSITY, TEXAS A&M UNIVERSITY SYSTEMInventors: Aditya Chandra Sai Ratcha, Amit Verma, Reza Nekovei, Mahmoud M. Khader
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Patent number: 9911803Abstract: A semiconductor device includes a semiconductor substrate. The element region of the semiconductor substrate includes a first body region having a first conductivity type, a first drift region having a second conductivity type, and a plurality of first floating regions, each the first floating regions having the first conductivity type. The termination region includes a second drift region having the second conductivity type, and a plurality of second floating regions, each of the second floating regions having the first conductivity type. The each of the second floating regions is surrounded by the second drift region. When a depth of a center of the first drift region is taken as a reference depth, at least one of the second floating regions is placed closer to the reference depth than each of the first floating regions.Type: GrantFiled: September 22, 2014Date of Patent: March 6, 2018Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATIONInventors: Jun Saito, Sachiko Aoi, Yukihiko Watanabe, Toshimasa Yamamoto
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Patent number: 9905634Abstract: A semiconductor device having a first load terminal, a second load terminal and a semiconductor body is presented. The semiconductor body comprises an active region configured to conduct a load current between the first load terminal and the second load terminal and a junction termination region surrounding the active region.Type: GrantFiled: June 21, 2016Date of Patent: February 27, 2018Assignee: Infineon Technologies Austria AGInventors: Andre Schwagmann, Elmar Falck, Hans-Joachim Schulze
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Patent number: 9899503Abstract: In mesa regions between adjacent trenches disposed in an n?-type drift layer and in which a first gate electrode is disposed via a first gate insulating film, a p-type base region and a floating p+-type region of which a surface is partially covered by a second gate electrode via a second gate insulating film are disposed. An emitter electrode contacts the p-type base region and an n+-type emitter region, and is electrically isolated from first and second gate electrodes and the floating p+-type region by an interlayer insulating film covering the first and second gate electrodes and a portion of the floating p+-type region not covered by the second gate electrode. Thus, turn-on dV/dt controllability by the gate resistance Rg may be improved.Type: GrantFiled: August 29, 2016Date of Patent: February 20, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventors: Yusuke Kobayashi, Yuichi Onozawa, Manabu Takei, Akio Nakagawa
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Patent number: 9899478Abstract: A semiconductor device includes transistor cells that connect a first load electrode with a drift structure forming first pn junctions with body zones when a gate voltage applied to a gate electrode exceeds a first threshold voltage. First auxiliary cells in a vertical projection of and electrically connected with the first load electrode are configured to inject charge carriers into the drift structure at least in a forward biased mode of the first pn junctions. Second auxiliary cells are configured to inject charge carriers into the drift structure at high emitter efficiency when in the forward biased mode of the first pn junctions the gate voltage is below a second threshold voltage lower than the first threshold voltage and at low emitter efficiency when the gate voltage exceeds the second threshold voltage.Type: GrantFiled: June 21, 2016Date of Patent: February 20, 2018Assignee: Infineon Technologies Austria AGInventors: Roman Baburske, Johannes Georg Laven
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Patent number: 9899504Abstract: A transistor includes first and second load terminals and a semiconductor body coupled to both terminals. The semiconductor body includes: a drift region having dopants of a first conductivity type; a transistor section for conducting a forward load current and having a control head coupling the first load terminal to a first side of the drift region; and a diode section for conducting a reverse load current. A diode port couples the second load terminal to a second side of the drift region and includes: a first emitter electrically connected to the second load terminal and having dopants of the first conductivity type for injecting majority charge carriers into the drift region; and a second emitter having dopants of a second conductivity type for injecting minority charge carriers into the drift region. A pn-junction transition between the first and second emitters has a breakdown voltage of less than 10 V.Type: GrantFiled: November 22, 2016Date of Patent: February 20, 2018Assignee: Infineon Technologies AGInventors: Roman Baburske, Johannes Georg Laven, Hans-Joachim Schulze, Antonio Vellei
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Patent number: 9899474Abstract: Semiconductor devices includes a thin epitaxial layer (nanotube) formed on sidewalls of mesas formed in a semiconductor layer. In one embodiment, a semiconductor device includes a first semiconductor layer, a second semiconductor layer formed thereon and of the opposite conductivity type, and a first epitaxial layer formed on mesas of the second semiconductor layer. An electric field along a length of the first epitaxial layer is uniformly distributed.Type: GrantFiled: June 8, 2017Date of Patent: February 20, 2018Assignee: Alpha and Omega Semiconductor, Inc.Inventors: Hamza Yilmaz, Xiaobin Wang, Anup Bhalla, John Chen, Hong Chang