With Extended Latchup Current Level (e.g., Comfet Device) Patents (Class 257/139)
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Patent number: 8907374Abstract: Embodiments of the present invention provide an IGBT, which relates to the field of integrated circuit manufacturing, and may improve a problem of tail current when the IGBT is turned off. The IGBT includes a cell region on a front surface, a terminal region surrounding the cell region, an IGBT drift region of a first conductivity type, and an IGBT collector region on a back surface. The IGBT collector region is connected to the IGBT drift region and under the IGBT drift region. The IGBT drift region includes a first drift region under the cell region and a second drift region under the terminal region. The IGBT collector region includes a cell collector region of a heavily doped second conductivity type under the first drift region and a non-conductive isolation region adjacent to the cell collector region.Type: GrantFiled: December 19, 2013Date of Patent: December 9, 2014Assignee: Hauwei Technologies Co., Ltd.Inventors: Yisheng Zhu, Jinping Zhang
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Patent number: 8901661Abstract: A semiconductor device includes a source metallization and a semiconductor body. The semiconductor body includes a first field-effect structure including a source region of a first conductivity type electrically coupled to the source metallization and a second field-effect structure including a source region of the first conductivity type electrically coupled to the source metallization. A first gate electrode of the first field-effect structure is electrically coupled to a first gate driver circuit and a second gate electrode of the second field-effect structure is electrically coupled to a second gate driver circuit different from the first gate driver circuit. The first field-effect structure and the second field-effect structure share a common drain.Type: GrantFiled: June 6, 2013Date of Patent: December 2, 2014Assignee: Infineon Technologies Austria AGInventors: Anton Mauder, Franz Hirler, Joachim Weyers
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Publication number: 20140346561Abstract: In a semiconductor substrate of a semiconductor device, a drift layer, a body layer, an emitter layer, and a trench gate electrode are formed. When the semiconductor substrate is viewed in a plane manner, the semiconductor substrate is divided into a first region covered with a heat dissipation member, and a second region not covered with the heat dissipation member. A density of trench gate electrodes in the first region is equal to a density of trench gate electrodes in the second region. A value obtained by dividing an effective carrier amount of channel parts formed in the first region by an area of the first region is larger than a value obtained by dividing an effective carrier amount of channel parts formed in the second region by an area of the second region.Type: ApplicationFiled: April 25, 2014Publication date: November 27, 2014Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventor: Tadashi MISUMI
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Publication number: 20140346562Abstract: A Trench Insulated Gate Bipolar Transistor (IGBT) and a manufacture method thereof are provided by the present invention, which belongs to the field of IGBT technical field. The manufacture method includes following steps: (1) preparing a semiconductor substrate; (2) forming an epitaxial layer grow on a first side of the semiconductor substrate by epitaxial growth; (3) preparing and forming a gate and an emitter of the Trench Insulated Gate Bipolar Transistor on a second side of the semiconductor substrate; (4) thinning the epitaxial layer to form a collector region; (5) metalizing the collector region to form a collector. The cost of the manufacture method is low and the performance of the Trench IGBT formed by the manufacture method is good.Type: ApplicationFiled: December 3, 2012Publication date: November 27, 2014Inventors: Hongxiang Tang, Yongsheng Sun, Jianxin Ji, Weiqing Ma
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Publication number: 20140339600Abstract: A trench gate MOS structure is provided on one main surface of a semiconductor substrate which will be an n? drift region. An n shell region is provided in the n? drift region so that it contacts a surface of a p base region close to the n? drift region forming the trench gate MOS structure. The n shell region has a higher impurity concentration than the n? drift region. The effective dose of n-type impurities in the n shell region is equal to or less than 5.0×1012 cm?2. The n? drift region has a resistivity to prevent a depletion layer, which is spread from a p collector region on the other main surface when reverse rated voltage is applied with an emitter as positive electrode, from reaching either n shell region or the bottom of a first trench, whichever is closer to the p collector region.Type: ApplicationFiled: August 4, 2014Publication date: November 20, 2014Inventor: Koh YOSHIKAWA
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Publication number: 20140339599Abstract: A semiconductor device includes a first gate electrode that is provided on a first insulating film along one side wall of a first trench and is provided in a second trench, a shield electrode that is provided on a second insulating film along the other side wall of the first trench and is provided in a third trench, a gate runner that is an extended portion of the second trench, has a portion which is provided on the first gate electrode, and is connected to the first gate electrode, and an emitter polysilicon layer that is an extended portion of the third trench, has a portion which is provided on the shield electrode, and is connected to the shield electrode. The semiconductor device has improved turn-on characteristics with a slight increase in the number of process steps, while preventing increase in costs and reduction in yield.Type: ApplicationFiled: August 1, 2014Publication date: November 20, 2014Inventors: Yuichi ONOZAWA, Hidenori TAKAHASHI, Takashi YOSHIMURA
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Publication number: 20140332846Abstract: A transistor-type protection device includes: a semiconductor substrate; a well including a first-conductivity-type semiconductor formed in the semiconductor substrate; a source region including a second-conductivity-type semiconductor formed in the well; a gate electrode formed above the well via a gate insulating film at one side of the source region; a drain region including the second-conductivity-type semiconductor formed within the well apart at one side of the gate electrode; and a resistive breakdown region including a second-conductivity-type semiconductor region in contact with the drain region at a predetermined distance apart from the well part immediately below the gate electrode, wherein a metallurgical junction form and a impurity concentration profile of the resistive breakdown region are determined so that a region not depleted at application of a drain bias when junction breakdown occurs in the drain region or the resistive breakdown region may remain in the resistive breakdown region.Type: ApplicationFiled: July 24, 2014Publication date: November 13, 2014Inventors: Tsutomu Imoto, Kouzou Mawatari
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Publication number: 20140332845Abstract: This invention discloses an insulated gate bipolar transistor (IGBT) device formed in a semiconductor substrate. The IGBT device has a split-shielded trench gate that includes an upper gate segment and a lower shield segment. The IGBT device may further include a dummy trench filled with a dielectric layer disposed at a distance away from the split-shielded trench gate. The IGBT device further includes a body region extended between the split-shielded trench gate and the dummy trench encompassing a source region surrounding the split-shielded trench gate near a top surface of the semiconductor substrate. The IGBT device further includes a heavily doped N region disposed below the body region and above a source-dopant drift region above a bottom body-dopant collector region at a bottom surface of the semiconductor substrate. In an alternative embodiment, the IGBT may include a planar gate with a trench shield electrode.Type: ApplicationFiled: May 11, 2013Publication date: November 13, 2014Inventors: Madhur Bobde, Anup Bhalla
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Publication number: 20140332844Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device comprises a plurality of trenches each having a trench endpoint with an endpoint sidewall perpendicular to a longitudinal direction of the trench and extends vertically downward from a top surface to a trench bottom surface. The semiconductor power device further includes a trench bottom dopant region disposed below the trench bottom surface and a sidewall dopant region disposed along the endpoint sidewall wherein the sidewall dopant region extends vertically downward along the endpoint sidewall of the trench to reach the trench bottom dopant region and pick-up the trench bottom dopant region to the top surface of the semiconductor substrate.Type: ApplicationFiled: May 10, 2013Publication date: November 13, 2014Inventors: Yongping Ding, Lei Zhang, Hong Chang, Jongoh Kim, John Chen
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Publication number: 20140327039Abstract: The present invention provides a trench type power transistor device including a substrate, an epitaxial layer, a doped diffusion region, a doped source region, and a gate structure. The substrate, the doped diffusion region, and the doped source region have a first conductivity type, and the substrate has an active region and a termination region. The epitaxial layer is disposed on the substrate, and has a second conductivity type. The epitaxial layer has a through hole disposed in the active region. The doped diffusion region is disposed in the epitaxial layer at a side of the through hole, and is in contact with the substrate. The doped source region is disposed in the epitaxial layer disposed right on the doped diffusion region, and the gate structure is disposed in the through hole between the doped diffusion region and the doped source region.Type: ApplicationFiled: July 14, 2014Publication date: November 6, 2014Inventors: Yung-Fa Lin, Shou-Yi Hsu, Meng-Wei Wu, Chia-Hao Chang
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Publication number: 20140327040Abstract: Provided is a power semiconductor device including a semiconductor substrate, in which a current flows in a thickness direction of the semiconductor substrate. The semiconductor substrate includes a resistance control structure configured so that a resistance to the current becomes higher in a central portion of the semiconductor substrate than a peripheral portion of the semiconductor substrate.Type: ApplicationFiled: July 21, 2014Publication date: November 6, 2014Applicant: Mitsubishi Electric CorporationInventor: Kenji HATORI
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Patent number: 8878239Abstract: On a main surface of a semiconductor substrate, an N? semiconductor layer is formed with a dielectric portion including relatively thin and thick portions interposed therebetween. In a predetermined region of the N? semiconductor layer, an N-type impurity region and a P-type impurity region are formed. A gate electrode is formed on a surface of a portion of the P-type impurity region located between the N-type impurity region and the N? semiconductor layer. In a predetermined region of the N? semiconductor layer located at a distance from the P-type impurity region, another P-type impurity region is formed. As a depletion layer block portion, another N-type impurity region higher in impurity concentration than the N? semiconductor layer is formed from the surface of the N? semiconductor layer to the dielectric portion.Type: GrantFiled: May 3, 2013Date of Patent: November 4, 2014Assignee: Mitsubishi Electric CorporationInventor: Tomohide Terashima
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Patent number: 8878238Abstract: Methods and systems for a gate-controlled thyristor which switches between narrow-base operation in the ON state and wide-base operation in the OFF state, and which can only sustain latch-up in the narrow-base ON state.Type: GrantFiled: October 1, 2012Date of Patent: November 4, 2014Assignee: Pakal Technologies LLCInventors: Richard A. Blanchard, Hidenori Akiyama, Woytek Tworzydlo
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Publication number: 20140319578Abstract: A semiconductor body of an IGBT includes: a first base region of a second conductivity type; a source region of a first conductivity type different from the second conductivity type and forming a first pn-junction with the first base region; a drift region of the first conductivity type and forming a second pn-junction with the first base region; a collector region of the second conductivity type; at least one trench filled with a gate electrode and having a first trench portion of a first width and a second trench portion of a second width, the second width being different from the first width; and a field stop region having the first conductivity type and located between the drift region and the collector region. The field stop region includes a plurality of buried regions having the second conductivity type.Type: ApplicationFiled: April 24, 2014Publication date: October 30, 2014Inventors: Holger Huesken, Frank Dieter Pfirsch, Hans-Joachim Schulze
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Publication number: 20140319577Abstract: A semiconductor device disclosed in this specification includes a p+ contact region, an n+ source region, a p? base region, an n? drift region, a gate electrode, an insulator, a p+ electric field alleviating layer, and a p? positive hole extraction region. The electric field alleviating layer has same impurity concentration as the base region or higher, contacts a lower surface of the base region, and is formed in a same depth as the gate trench or in a position deeper than the gate trench. A positive hole extraction region extends to contact the electric field alleviating layer from a position to contact an upper surface of a semiconductor substrate or a first semiconductor region, and extracts a positive hole that is produced in the electric field alleviating layer at the avalanche breakdown to the upper surface of the semiconductor substrate.Type: ApplicationFiled: April 3, 2014Publication date: October 30, 2014Applicants: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Masahiro SUGIMOTO, Yuichi Takeuchi
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Publication number: 20140312383Abstract: A power semiconductor device may include: abase substrate including a first conductive type drift layer; a second conductive type semiconductor substrate disposed on the other surface of the base substrate; a first conductive type diffusion layer disposed in the base substrate and having an impurity concentration higher than that of the drift layer; a second conductive type well layer disposed inside of one surface of the base substrate; a trench formed from one surface of the base substrate including the well layer so as to penetrate through the diffusion layer in a depth direction; a first insulation film disposed on a surface of the base substrate; and a first electrode disposed in the trench. A peak point of an impurity doping concentration of the diffusion layer in a transverse direction may be positioned in a region contacting a side surface of the trench.Type: ApplicationFiled: July 2, 2014Publication date: October 23, 2014Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: In Hyuk SONG, Jae Hoon Park, Dong Soo Seo, Chang Su Jang
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Publication number: 20140312382Abstract: Provided are a power device having an improved field stop layer and a method of manufacturing the same. The power device includes: a first field stop layer formed of a semiconductor substrate and of a first conductive type; a second field stop layer formed on the first field stop layer and of the first conductive type, the second field stop layer having a region with an impurity concentration higher than the first field stop layer; a drift region formed on the second field stop layer and of the first conductive type, the drift region having an impurity concentration lower than the first field stop layer; a plurality of power device cells formed on the drift region; and a collector region formed below the first field stop layer, wherein the second field stop layer includes a first region having a first impurity concentration and a second region having a second impurity concentration higher than the first impurity concentration.Type: ApplicationFiled: June 26, 2014Publication date: October 23, 2014Inventors: Kyu-hyun LEE, Young-chul KIM, Kyeong-seok PARK, Bong-yong LEE, Young-chul CHOI
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Publication number: 20140299915Abstract: In a semiconductor device having a vertical semiconductor element configured to pass an electric current between an upper electrode and a lower electrode, a field stop layer includes a phosphorus/arsenic layer doped with phosphorus or arsenic and a proton layer doped with proton. The phosphorus/arsenic layer is formed from a back side of a semiconductor substrate to a predetermined depth. The proton layer is deeper than the phosphorus/arsenic layer. An impurity concentration of the proton layer peaks inside the phosphorus/arsenic layer and gradually, continuously decreases at a depth greater than the phosphorus/arsenic layer.Type: ApplicationFiled: October 9, 2012Publication date: October 9, 2014Inventors: Kenji Kouno, Shinji Amano
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Publication number: 20140299914Abstract: Semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In one embodiment, a semiconductor device is formed in a second semiconductor layer disposed on a first semiconductor layer of opposite conductivity type and having trenches formed therein where the trenches extend from the top surface to the bottom surface of the second semiconductor layer. The semiconductor device includes a first epitaxial layer formed on sidewalls of the trenches where the first epitaxial layer is substantially charge balanced with adjacent semiconductor regions. The semiconductor device further includes a first dielectric layer formed in the trenches adjacent the first epitaxial layer and a gate electrode disposed in an upper portion of at least some of the trenches above the first dielectric layer and insulated from the sidewalls of the trenches by a gate dielectric layer.Type: ApplicationFiled: April 2, 2014Publication date: October 9, 2014Applicant: Alpha and Omega Semiconductor IncorporatedInventors: Hamza Yilmaz, Xiaobin Wang, Anup Bhalla, John Chen, Hong Chang
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Publication number: 20140291723Abstract: A method of producing a seminconductor device is disclosed in which, after proton implantation is performed, a hydrogen-induced donor is formed by a furnace annealing process to form an n-type field stop layer. A disorder generated in a proton passage region is reduced by a laser annealing process to form an n-type disorder reduction region. As such, the n-type field stop layer and the n-type disorder reduction region are formed by the proton implantation. Therefore, it is possible to provide a stable and inexpensive semiconductor device which has low conduction resistance and can improve electrical characteristics, such as a leakage current, and a method for producing the semiconductor device.Type: ApplicationFiled: June 11, 2014Publication date: October 2, 2014Inventors: Masayuki MIYAZAKI, Takashi YOSHIMURA, Hiroshi TAKISHITA, Hidenao KURIBAYASHI
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Publication number: 20140291722Abstract: There is provided a power semiconductor device, including a plurality of trench gates formed to be spaced apart from each other by a predetermined distance, a current increasing part formed between the trench gates and including a first conductivity-type emitter layer and a gate oxide formed on a surface of the trench gate, and an immunity improving part formed between the trench gates and including a second conductivity-type body layer, a preventing film formed on the surface of the trench gate, and a gate oxide having a thickness less than that the gate oxide of the current increasing part.Type: ApplicationFiled: July 9, 2013Publication date: October 2, 2014Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Dong Soo SEO, Jaehoon PARK, Kee Ju UM, Chang Su JANG, In Hyuk SONG
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Patent number: 8847276Abstract: In a semiconductor device including an IGBT and a freewheeling diode (FWD), W1, W2, and W3 satisfy predetermined formulas. W1 denotes a distance from a boundary between a cathode region and a collector region to a position, where a peripheral-region-side end of the well layer is projected, on a back side of the drift layer. W2 denotes a distance from a boundary between the IGBT and the FWD in a base region to the peripheral-region-side end of the well layer. W3 denotes a distance from the boundary between the cathode region and the collector region to a position, where a boundary between the base region and the well layer is projected, on the back side.Type: GrantFiled: June 29, 2011Date of Patent: September 30, 2014Assignee: DENSO CORPORATIONInventors: Hiromitsu Tanabe, Kenji Kouno, Yukio Tsuzuki
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Publication number: 20140284657Abstract: A p anode layer (2) is formed on one main surface of an n? drift layer (1). An n+ cathode layer (3) having an impurity concentration more than that of the n? drift layer (1) is formed on the other main surface of the n? drift layer (1). An anode electrode (4) is formed on the surface of the p anode layer (2). A cathode electrode (5) is formed on the surface of the n+ cathode layer (3). An n-type broad buffer region (6) that has a net doping concentration more than the bulk impurity concentration of a wafer and less than that of the n+ cathode layer (3) and the p anode layer (2) is formed in the n? drift layer (1). The resistivity ?0 of the n? drift layer (1) satisfies 0.12V0??0?0.25V0 with respect to a rated voltage V0. The total amount of the net doping concentration of the broad buffer region (6) is equal to or more than 4.8×1011 atoms/cm2 and equal to or less than 1.0×1012 atoms/cm2.Type: ApplicationFiled: May 21, 2014Publication date: September 25, 2014Applicant: FUJI ELECTRIC CO., LTD.Inventors: Michio NEMOTO, Takashi YOSHIMURA
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Publication number: 20140284655Abstract: A semiconductor device of an embodiment is provided with a normally-off transistor having a first source connected to a source terminal, a first drain, and a first gate connected to a gate terminal and a normally-on transistor having a second source connected to the first drain, a second drain connected to a drain terminal, and a second gate connected to the source terminal. A withstand voltage between the first source and the first drain when the normally-off transistor is turned off is lower than a withstand voltage between the second source and the second gate of the normally-on transistor.Type: ApplicationFiled: February 19, 2014Publication date: September 25, 2014Applicant: Kabushiki Kaisha ToshibaInventor: Kentaro IKEDA
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Publication number: 20140284656Abstract: An MOS semiconductor device including an MOS gate structure is disclosed. The MOS semiconductor device includes a p-type well region selectively disposed on the surface layer of an n-type drift layer formed on a semiconductor substrate forming an n-type drain region; an n-type source region selectively disposed on the surface layer of the p-type well region; and a gate electrode placed, via an insulating film, on the surface of a channel formation region on the surface layer of the p-type well region sandwiched between the n-type source region and the surface layer of the n-type drain region, wherein a surface in the channel formation region has a level difference formed in the direction of the peripheral length, and all over the length, of the channel formation region.Type: ApplicationFiled: March 19, 2014Publication date: September 25, 2014Applicant: FUJI ELECTRIC CO., LTD.Inventor: Masanori INOUE
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Patent number: 8841720Abstract: A semiconductor substrate capable of detecting operating current of a MOSFET and diode current in a miniaturized MOSFET such as a trench-gate type MOSFET is provided. A semiconductor substrate includes a main current region and a current sensing region in which current smaller than main current flowing in the main current region flows. The main current region has a source electrode disposed on a main surface, the source electrode being in contact with a p-type semiconductor region (body) and an n+-type semiconductor region (source), and the current sensing region has a MOSFET current detecting electrode and a diode current detecting electrode on a main surface, the MOSFET current detecting electrode being in contact with the p-type semiconductor region (body) and the n+-type semiconductor region (source), the diode current detecting electrode being in contact with the p-type semiconductor region (body).Type: GrantFiled: March 14, 2013Date of Patent: September 23, 2014Assignee: Renesas Electronics CorporationInventor: Takayuki Hashimoto
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Patent number: 8841180Abstract: A method to form a strain-inducing semiconductor region is described. In one embodiment, formation of a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In another embodiment, a semiconductor region with a crystalline lattice of one or more species of charge-neutral lattice-forming atoms imparts a strain to a crystalline substrate, wherein the lattice constant of the semiconductor region is different from that of the crystalline substrate, and wherein all species of charge-neutral lattice-forming atoms of the semiconductor region are contained in the crystalline substrate.Type: GrantFiled: August 20, 2013Date of Patent: September 23, 2014Assignee: Intel CorporationInventors: Suman Datta, Jack T. Kavalieros, Been-Yih Jin
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Patent number: 8841699Abstract: A semiconductor device includes an IGBT forming region and a diode forming region. The IGBT forming region includes an IGBT operating section that operates as an IGBT and a thinned-out section that does not operate as an IGBT. The IGBT operating section includes a channel region, and the thinned-out section includes a first anode region. The diode forming region includes a second anode region. When an area density is defined as a value calculated by integrating a concentration profile of second conductivity type impurities in each of the channel region, the first anode region, and the second anode region in a depth direction, an area density of the channel region is higher than an area density of the first anode region and an area density of the second anode region.Type: GrantFiled: June 13, 2012Date of Patent: September 23, 2014Assignee: DENSO CORPORATIONInventors: Yukio Tsuzuki, Hiromitsu Tanabe, Kenji Kouno
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Publication number: 20140264433Abstract: A method of manufacturing an insulated gate bipolar transistor (IGBT) device comprising 1) preparing a semiconductor substrate with an epitaxial layer of a first conductivity type supported on the semiconductor substrate of a second conductivity type; 2) applying a gate trench mask to open a first trench and second trench followed by forming a gate insulation layer to pad the trench and filling the trench with a polysilicon layer to form the first trench gate and the second trench gate; 3) implanting dopants of the first conductivity type to form an upper heavily doped region in the epitaxial layer; and 4) forming a planar gate on top of the first trench gate and apply implanting masks to implant body dopants and source dopants to form a body region and a source region near a top surface of the semiconductor substrate.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Inventors: Jun Hu, Madhur Bobde, Hamza Yilmaz
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Publication number: 20140264432Abstract: A semiconductor device in a semiconductor substrate includes a first main surface and a transistor cell. The transistor cell includes a drift region of a first conductivity type, a body region of a second conductivity type between the drift region and the first main surface, an active trench in the first main surface extending to the drift region, a source region of the first conductivity in the body region adjacent to the active trench, and a body trench at the first main surface extending to the drift region and adjacent to the body region and the drift region. The active trench includes a gate insulating layer at sidewalls and a bottom side, and a gate conductive layer. The body trench includes a conductive layer and an insulating layer at sidewalls and a bottom side, and asymmetric to a perpendicular axis of the first main surface and the body trench center.Type: ApplicationFiled: March 12, 2013Publication date: September 18, 2014Inventors: Maria Cotorogea, Frank Wolter, Hans-Joachim Schulze, Franz-Josef Niedernostheide, Yvonne Gawlina-Schmidl
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Publication number: 20140252408Abstract: A reverse conducting IGBT that includes an insulated gate; a semiconductor layer having a first conductivity type drift region, a second conductivity type body region, a first conductivity type emitter region, and a second conductivity type intermediate region; and an emitter electrode provided on a surface of the semiconductor layer. The first conductivity type drift region of the semiconductor layer contacts the insulated gate. The second conductivity type body region of the semiconductor layer is provided on the drift region and contacts the insulated gate. The first conductivity type emitter region of the semiconductor layer is provided on the body region and contacts the insulated gate. The second conductivity type intermediate region of the semiconductor layer is provided on the emitter region and is interposed between the emitter region and the emitter electrode.Type: ApplicationFiled: February 18, 2014Publication date: September 11, 2014Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Yusuke YAMASHITA, Satoru MACHIDA, Jun SAITO
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Patent number: 8829563Abstract: An insulated gate bipolar device is disclosed which can include layers of different conductivity types between an emitter electrode on an emitter side and a collector electrode on a collector side in the following order: a source region of a first conductivity type, a base layer of a second conductivity type, which contacts the emitter electrode in a contact area, an enhancement layer of the first conductivity type, a floating compensation layer of the second conductivity type having a compensation layer thickness tp, a drift layer of the first conductivity type having lower doping concentration than the enhancement layer and a collector layer of the second conductivity type.Type: GrantFiled: August 23, 2013Date of Patent: September 9, 2014Assignee: ABB Technology AGInventors: Munaf Rahimo, Marco Bellini, Maxi Andenna, Friedhelm Bauer, Iulian Nistor
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Patent number: 8829562Abstract: A semiconductor device includes a trench extending into a drift zone of a semiconductor body from a first surface. The semiconductor device further includes a gate electrode in the trench and a body region adjoining a sidewall of the trench. The semiconductor device further includes a dielectric structure in the trench. The dielectric structure includes a high-k dielectric in a lower part of the trench. The high-k dielectric includes a dielectric constant higher than that of SiO2. An extension of the high-k dielectric in a vertical direction perpendicular to the first surface is limited between a bottom side of the trench and a level where a bottom side of the body region adjoins the sidewall of the trench.Type: GrantFiled: July 24, 2012Date of Patent: September 9, 2014Assignee: Infineon Technologies AGInventors: Hans-Joachim Schulze, Franz Hirler, Hans-Peter Felsl, Franz-Josef Niedernostheide
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Patent number: 8823053Abstract: The semiconductor device includes a plurality of first flat plates containing a material that absorbs an electromagnetic wave at a high frequency. Any of the first flat plates is disposed above the first connecting wire, and any other of the first flat plates is disposed above the second connecting wire.Type: GrantFiled: February 28, 2013Date of Patent: September 2, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Yoko Sakiyama, Kohei Morizuka
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Patent number: 8823052Abstract: A power semiconductor device includes a four-layer structure having layers arranged in order: (i) a cathode layer of a first conductivity type with a central area being surrounded by a lateral edge, the cathode layer being in direct electrical contact with a cathode electrode, (ii) a base layer of a second conductivity type, (iii) a drift layer of the first conductivity typehaving a lower doping concentration than the cathode layer, and (iv) an anode layer of the second conductivity type which is in electrical contact with an anode electrode. The base layer includes a first layer as a continuous layer contacting the central area of the cathode layer. A resistance reduction layer, in which the resistance at the junction between the lateral edge of the cathode and base layers is reduced, is arranged between the first layer and the cathode layer and covers the lateral edge of the cathode layer.Type: GrantFiled: June 22, 2012Date of Patent: September 2, 2014Assignee: ABB Technology AGInventor: Munaf Rahimo
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Patent number: 8823051Abstract: A diode-connected lateral transistor on a substrate of a first conductivity type includes a vertical parasitic transistor through which a parasitic substrate leakage current flows. Means for shunting at least a portion of the flow of parasitic substrate leakage current away from the vertical parasitic transistor is provided.Type: GrantFiled: May 15, 2006Date of Patent: September 2, 2014Assignee: Fairchild Semiconductor CorporationInventors: Jun Cai, Micheal Harley-Stead, Jim G. Holt
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Publication number: 20140239344Abstract: There is provided a power semiconductor device, including a first conductive type drift layer; a second conductive type body layer formed on the drift layer, a second conductive type collector layer formed below the drift layer; a first gate formed by penetrating through the body layer and a portion of the drift layer, a first conductive type emitter layer formed in the body layer and formed to be spaced apart from the first gate, a second gate covering upper portions of the body layer and the emitter layer and formed as a flat type gate on the first gate, and a segregation stop layer formed between contact surfaces of the first and second gates with the body layer, the emitter layer, and the drift layer.Type: ApplicationFiled: May 9, 2013Publication date: August 28, 2014Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Jaehoon PARK, In Hyuk SONG, Dong Soo SEO, Kwang Soo KIM, Kee Ju UM
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Publication number: 20140240027Abstract: An insulated gate turn-off (IGTO) device has a layered structure including a p+ layer (e.g., a substrate), an n-type layer, a p-type layer (which may be a p-well), n+ regions formed in the surface of the p-type layer, and insulated planar gates over the p-type layer between the n+ regions. The layered structure forms vertical NPN and PNP transistors. The p-type layer forms the base of the NPN transistor. When the gates are sufficiently positively biased, the underlying p-type layer inverts to reduce the width of the base to increase the beta of the NPN transistor. This causes the product of the betas of the NPN and PNP transistors to exceed one, and the device becomes fully conductive. When the gate voltage is removed, the base width increases such that the product of the betas is less than one, and the device shuts off. No latch-up occurs in normal operation.Type: ApplicationFiled: February 27, 2014Publication date: August 28, 2014Applicant: Pakal Technologies, LLCInventors: Richard A. Blanchard, Hidenori Akiyama, Woytek Tworzydlo, Vladimir Rodov
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Publication number: 20140240025Abstract: A lateral insulated gate turn-off (IGTO) device includes an n-type layer, a p-well formed in the n-type layer, a shallow n+ type region formed in the well, a shallow p+ type region formed in the well, a cathode electrode shorting the n+ type region to the p+ type region, at least one trenched gate extending through the n+ type region and into the well, a p+ type anode region laterally spaced from the well, and an anode electrode electrically contacting the p+ type anode region. The structure forms a lateral structure of NPN and PNP transistors, where the well forms the base of the NPN transistor. When a turn-on voltage is applied to the gate, the p-base has a reduced width, resulting in the beta of the NPN transistor increasing beyond a threshold to turn on the IGTO device by current feedback.Type: ApplicationFiled: February 27, 2014Publication date: August 28, 2014Applicant: PAKAL TECHNOLOGIES, LLCInventors: Richard A. Blanchard, Hidenori Akiyama, Woytek Tworzydlo
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Publication number: 20140231866Abstract: An IGBT has an emitter region, a top body region that is formed below the emitter region, a floating region that is formed below the top body region, a bottom body region that is formed below the floating region, a trench, a gate insulating film that covers an inner face of the trench, and a gate electrode that is arranged inside the trench. When a distribution of a concentration of p-type impurities in the top body region and the floating region, which are located below the emitter region, is viewed along a thickness direction of a semiconductor substrate, the concentration of the p-type impurities decreases as a downward distance increases from an upper end of the top body region that is located below the emitter region, and assumes a local minimum value at a predetermined depth in the floating region.Type: ApplicationFiled: September 28, 2011Publication date: August 21, 2014Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Masaru Senoo, Kyosuke Miyagi, Tsuyoshi Nishiwaki, Jun Saito
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Publication number: 20140231865Abstract: An insulated gate semiconductor device includes a region that is provided between trenches in which a gate electrode is filled through a gate insulating film in a surface layer of a substrate, includes a p base region and an n+ emitter region, and comes into conductive contact with an emitter electrode and a p-type floating region that is electrically insulated by an insulating film which is interposed between the p-type floating region and the emitter electrode. The p-type floating region is deeper than the trench and has a lower impurity concentration than the p base region.Type: ApplicationFiled: April 9, 2014Publication date: August 21, 2014Applicant: FUJI ELECTRIC CO., LTD.Inventor: Yuichi ONOZAWA
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Patent number: 8809903Abstract: A semiconductor device provides a gate electrode formed on a lateral face of a wide trench, and thereby the gate electrode is covered by a gate insulating layer and a thick insulating layer to be an inter layer. Therefore, a parasitic capacitance of the gate becomes small, and there is no potential variation of the gate since there is no floating p-layer so that a controllability of the dv/dt can be improved. In addition, the conductive layer between the gate electrodes can relax the electric field applied to the corner of the gate electrode. In consequence, compatibility of low loss and low noise and high reliability can be achieved.Type: GrantFiled: August 30, 2013Date of Patent: August 19, 2014Assignee: Hitachi, Ltd.Inventors: So Watanabe, Mutsuhiro Mori, Taiga Arai
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Patent number: 8809902Abstract: A power semiconductor diode is provided. The power semiconductor diode includes a semiconductor substrate having a first emitter region of a first conductivity type, a second emitter region of a second conductivity type, and a drift region of the first conductivity type arranged between the first emitter region and the second emitter region. The drift region forms a pn-junction with the second emitter region. A first emitter metallization is in contact with the first emitter region. The first emitter region includes a first doping region of the first conductivity type and a second doping region of the first conductivity type. The first doping region forms an ohmic contact with the first emitter metallization, and the second doping region forms a non-ohmic contact with the first emitter metallization. A second emitter metallization is in contact with the second emitter region.Type: GrantFiled: October 17, 2011Date of Patent: August 19, 2014Assignee: Infineon Technologies Austria AGInventors: Holger Huesken, Anton Mauder, Hans-Joachim Schulze, Wolfgang Roesner
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Patent number: 8809961Abstract: An electrostatic discharge (ESD) protection circuit structure includes several diffusion regions and a MOS transistor. The circuit structure includes a first diffusion region of a first type (e.g., P-type or N-type) formed in a first well of the first type, a second diffusion region of the first type formed in the first well of the first type, and a first diffusion region of a second type (e.g., N-type or P-type) formed in a first well of the second type. The first well of the second type is formed in the first well of the first type. The MOS transistor is of the second type and includes a drain formed by a second diffusion region of the second type formed in a second well of the second type bordering the first well of the first type.Type: GrantFiled: October 17, 2013Date of Patent: August 19, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Che Tsai, Jam-Wem Lee, Yi-Feng Chang
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Publication number: 20140225155Abstract: A semiconductor device includes: a first semiconductor region; a second semiconductor region, which is arranged on the first semiconductor region; a third semiconductor region, which is arranged on the second semiconductor region; a plurality of fourth semiconductor regions, each of which is arranged with being spaced from each other on the third semiconductor region; a insulation film arranged on a inner wall of a recess, which extends from upper faces of the fourth semiconductor region to pass through the third semiconductor region and the fourth semiconductor region and reaches the second semiconductor region; a control electrode, a first main electrode, a second main electrode, which is electrically connected to the third semiconductor region and the fourth semiconductor region, wherein a ratio of a width of the recess to a width of the third semiconductor region abutting on the second main electrode is 1 or more.Type: ApplicationFiled: September 25, 2013Publication date: August 14, 2014Applicant: Sanken Electric Co., Ltd.Inventor: Kazuko Ogawa
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Patent number: 8803160Abstract: A semiconductor device including a drift zone of a first conductivity type serving as a substrate layer having a front side and a back side. A first contact electrode is arranged at the front side of the drift zone. A control region is arranged at the front side and controls an injection of carriers of at least the first conductivity type into the drift zone. A second contact electrode is arranged at the backside of the drift zone. The drift zone is arranged to carry a carrier flow between the first and the second contact electrode. The drift zone includes a silicon carbide wafer with a net carrier concentration less than 1015 cm?3 and a carrier lifetime of at least 50 ns.Type: GrantFiled: December 29, 2011Date of Patent: August 12, 2014Assignees: Siced Electronics Development GmbH & Co. KG, Norstel ABInventors: Alexandre Ellison, Björn Magnusson, Asko Vehanen, Dietrich Stephani, Heinz Mitlehner, Peter Friedrichs
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Publication number: 20140217463Abstract: A bipolar semiconductor switch having a semiconductor body is provided. The semiconductor body includes a first p-type semiconductor region, a second p-type semiconductor region, and a first n-type semiconductor region forming a first pn-junction with the first p-type semiconductor region and a second pn-junction with the second p-type semiconductor region. On a shortest path through the first n-type semiconductor region between the first pn-junction and the second pn-junction a concentration of charge recombination centers and a concentration of n-dopants vary. The concentration of the charge recombination centers has a maximum at a point along the shortest path where the concentration of n-dopants is at least close to a maximum dopant concentration. Further, a manufacturing method for the bipolar semiconductor switch is provided.Type: ApplicationFiled: February 7, 2013Publication date: August 7, 2014Applicant: INFINEON TECHNOLOGIES AGInventors: Hans-Joachim Schulze, Franz-Josef Niedernostheide
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Publication number: 20140217464Abstract: In a semiconductor device, a trench gate has a bottom portion in a drift layer and a communication portion extending from a surface of a base layer to communicate with the bottom portion. A distance between adjacent bottom portions is smaller than a distance between adjacent communication portions in a x-direction. A region between adjacent trench gates is divided in a y-direction into an effective region as an electron injection source and an ineffective region which does not serve as the electron injection source. An interval L1 (>0) of the ineffective region in the y-direction, a length D1 of the communication portion in the z-direction, and a length D2 of the bottom portion in the z-direction satisfy L1?2(D1+D2). The z-direction is orthogonal to a x-y plane defined by the x-direction and the y-direction which are orthogonal to each other.Type: ApplicationFiled: September 13, 2012Publication date: August 7, 2014Applicant: DENSO CORPORATIONInventors: Yasushi Higuchi, Shigemitsu Fukatsu, Masakiyo Sumitomo
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Publication number: 20140209970Abstract: A semiconductor portion of a semiconductor device includes a semiconductor layer with a drift zone of a first conductivity type and at least one impurity zone of a second, opposite conductivity type. The impurity zone adjoins a first surface of the semiconductor portion in an element area. A connection layer directly adjoins the semiconductor layer opposite to the first surface. At a distance to the first surface an overcompensation zone is formed in an edge area that surrounds the element area. The overcompensation zone and the connection layer have opposite conductivity types. In a direction vertical to the first surface, a portion of the drift zone is arranged between the first surface and the overcompensation zone. In case of locally high current densities, the overcompensation zone injects charge carriers into the semiconductor layer that locally counter a further increase of electric field strength and reduce the risk of avalanche breakdown.Type: ApplicationFiled: January 31, 2013Publication date: July 31, 2014Inventors: Hans-Joachim Schulze, Anton Mauder, Franz Hirler
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Publication number: 20140209971Abstract: Embodiments of the present invention provide an IGBT, which relates to the field of integrated circuit manufacturing, and may improve a problem of tail current when the IGBT is turned off. The IGBT includes a cell region on a front surface, a terminal region surrounding the cell region, an IGBT drift region of a first conductivity type, and an IGBT collector region on a back surface. The IGBT collector region is connected to the IGBT drift region and under the IGBT drift region. The IGBT drift region includes a first drift region under the cell region and a second drift region under the terminal region. The IGBT collector region includes a cell collector region of a heavily doped second conductivity type under the first drift region and a non-conductive isolation region adjacent to the cell collector region.Type: ApplicationFiled: December 19, 2013Publication date: July 31, 2014Applicant: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Yisheng Zhu, Jinping Zhang