With Specified Housing Or External Terminal Patents (Class 257/150)
  • Patent number: 10438865
    Abstract: It is an object of the present invention to provide a semiconductor device that has sufficient insulation properties between a screw and a heat dissipation plate, and is smaller and less costly. A semiconductor device of the present invention includes the following: a housing containing a semiconductor element; a heat dissipation plate disposed on a bottom surface of the housing, and provided to partly extend beyond the housing to reach the outside; an electrode electrically connected to the semiconductor element, and provided to partly protrude from the housing to the outside in parallel with the heat dissipation plate; and a screw with which an exposed portion of the electrode, protruding from the housing is joined to a busbar. The heat dissipation plate has a thickness lack portion in a location of the heat dissipation plate, the location at least facing the screw, the location being on a screw side.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: October 8, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Koichi Taguchi, Yuki Hata
  • Patent number: 10381284
    Abstract: A semiconductor package includes a first electronic component disposed on a first surface of a substrate, a first conductive member disposed on the first electronic component, and a sealing member configured to cover the first electronic component and forming a hole to expose the first conductive member to an exterior of the semiconductor package. The semiconductor package also includes a second conductive member disposed on the hole and connected to the first conductive member.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: August 13, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Mi Suk Choi
  • Patent number: 9850122
    Abstract: An electronic device comprising a first substrate having a device area, a first sealing element comprising an anelastic material and a second sealing element being a metal. The first sealing means and the second sealing means are arranged such that the inner side or the outer side of the sealing is completely formed by the second sealing element providing hermiticity and the other side is substantially formed by the first sealing element providing a flexible sealing.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: December 26, 2017
    Assignee: MELEXIS TECHNOLOGIES NV
    Inventor: Appolonius Jacobus Van Der Wiel
  • Patent number: 9536816
    Abstract: An electronic device comprising a carrier having a mounting surface, at least one electronic chip mounted on the mounting surface, at least one electric connection structure mounted on the mounting surface, an encapsulant at least partially encapsulating the carrier and the at least one electronic chip, and partially encapsulating the at least one electric connection structure so that part of a surface of the at least one electric connection structure is exposed to an environment, and a mounting provision configured for mounting the electronic device at a periphery device.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: January 3, 2017
    Assignee: Infineon Technologies AG
    Inventors: Angela Kessler, Eduard Knauer, Rudolf Lehner, Wolfgang Schober, Sigrid Schultes
  • Patent number: 8994165
    Abstract: A power semiconductor device includes power semiconductor elements joined to wiring patterns of a circuit substrate, cylindrical external terminal communication sections, and wiring means for forming electrical connection between, for example, the power semiconductor elements and the cylindrical external terminal communication sections. The power semiconductor elements, the cylindrical external terminal communication sections, and the wiring means are sealed with transfer molding resin. The cylindrical external terminal communication sections are arranged on the wiring patterns so as to be substantially perpendicular to the wiring patterns, such that external terminals are insertable and connectable to the cylindrical external terminal communication sections, and such that a plurality of cylindrical external terminal communication sections among the cylindrical external terminal communication sections are arranged two-dimensionally on each of wiring patterns that act as main circuits.
    Type: Grant
    Filed: July 16, 2009
    Date of Patent: March 31, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takeshi Oi, Seiji Oka, Yoshiko Obiraki, Osamu Usui, Yasushi Nakayama
  • Patent number: 8853739
    Abstract: A pressure contact semiconductor device includes a cathode post electrode and a gate electrode formed on a top surface of a substrate, an anode post electrode formed on a bottom surface thereof, a circuit substrate, a cathode flange overlapping the cathode post electrode and connected to the circuit substrate, a cathode fin electrode overlapping the cathode flange, an anode fin electrode underlapping and the anode post electrode, a gate flange connected to both the gate electrode and the circuit substrate, a securing member having a parallel portion parallel to the circuit substrate and a perpendicular portion perpendicular to the circuit substrate, the perpendicular portion being secured to a side of the cathode fin electrode, and a spacer formed from plate material and secured at the top to the parallel portion of the securing member and at the bottom to the circuit substrate.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: October 7, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventor: Kazunori Taguchi
  • Patent number: 8610261
    Abstract: A power semiconductor device includes a power semiconductor module having cylindrical conductors which are joined to a wiring pattern so as to be substantially perpendicular to the wiring pattern and whose openings are exposed at a surface of transfer molding resin, and an insert case having a ceiling portion and peripheral walls, the ceiling portion being provided with external terminals that are fitted into, and passed through, the ceiling portion, the external terminals having outer-surface-side connecting portions at the outer surface side of the ceiling portion and inner-surface-side connecting portions at the inner surface side of the ceiling portion. The power semiconductor module is set within the insert case such that the inner-surface-side connecting portions of the external terminals are inserted into the cylindrical conductors.
    Type: Grant
    Filed: October 20, 2009
    Date of Patent: December 17, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventors: Seiji Oka, Yoshiko Obiraki, Takeshi Oi
  • Patent number: 8519433
    Abstract: The present disclosure provides a semiconductor switching device including a substrate having deposited thereon a cathode, an anode and a gate of the semiconductor switching device, and a connection means for electrically connecting the cathode in the gate of the semiconductor switching device to an external circuit unit. The connection includes a cathode-gate connection unit having a coaxial structure including a gate conductor and a cathode conductor for electrically connecting the cathode and the gate of the semiconductor switching device to the external circuit unit.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: August 27, 2013
    Assignee: ABB Research Ltd
    Inventors: Didier Cottet, Thomas Stiasny, Tobias Wikstroem
  • Patent number: 8400778
    Abstract: A multi-phase voltage regulator is disclosed where each phase is comprised of an array of high and low side transistors that are integrated onto a single substrate. Further, a system of mounting the voltage regulator onto a flip chip and lead frame is disclosed wherein the source and drain lines form an interdigital pattern.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: March 19, 2013
    Assignee: Monolithic Power Systems, Inc.
    Inventors: Michael R. Hsing, Anthonius Bakker
  • Publication number: 20120326208
    Abstract: A pressure contact semiconductor device includes a cathode post electrode and a gate electrode formed on a top surface of a substrate, an anode post electrode formed on a bottom surface thereof, a circuit substrate, a cathode flange overlapping the cathode post electrode and connected to the circuit substrate, a cathode fin electrode overlapping the cathode flange, an anode fin electrode underlapping and the anode post electrode, a gate flange connected to both the gate electrode and the circuit substrate, a securing member having a parallel portion parallel to the circuit substrate and a perpendicular portion perpendicular to the circuit substrate, the perpendicular portion being secured to a side of the cathode fin electrode, and a spacer formed from plate material and secured at the top to the parallel portion of the securing member and at the bottom to the circuit substrate.
    Type: Application
    Filed: February 13, 2012
    Publication date: December 27, 2012
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Kazunori TAGUCHI
  • Patent number: 8319333
    Abstract: In the power semiconductor module, a wiring metal plate electrically connects between power semiconductor elements joined to the circuit pattern, and between the power semiconductor elements and the circuit pattern. Cylindrical main terminals are joined, substantially perpendicularly, to the wiring metal plate and the circuit pattern, respectively. A cylindrical control terminal is joined, substantially perpendicularly, to one of the power semiconductor elements.
    Type: Grant
    Filed: October 20, 2009
    Date of Patent: November 27, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventors: Seiji Oka, Yoshiko Obiraki, Takeshi Oi
  • Patent number: 8299603
    Abstract: A power semiconductor device in which transfer molding resin seals: a metallic circuit substrate; a power semiconductor element joined to a wiring pattern; and a side surface of a cylindrical external terminal communication section provided on the wiring pattern and to which an external terminal can be inserted and connected. The cylindrical external terminal communication section is substantially perpendicular to a surface on which the wiring pattern is formed. An outer surface of a metal plate of the metallic circuit substrate and a top portion of the cylindrical external terminal communication section are exposed from the transfer molding resin. The transfer molding resin is not present within the cylindrical external terminal communication section.
    Type: Grant
    Filed: January 18, 2008
    Date of Patent: October 30, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventors: Seiji Oka, Osamu Usui, Yasushi Nakayama, Yoshiko Obiraki, Takeshi Oi
  • Patent number: 8299601
    Abstract: A power semiconductor module includes: a circuit board having a metal base plate, a high thermal conductive insulating layer, and a wiring pattern; power semiconductor elements electrically connected to the wiring pattern; tubular external terminal connection bodies provided to the wiring pattern for external terminals; and a transfer mold resin body encapsulated to expose through-holes in the metal base plate and used to fixedly attach cooling fins to the face of the metal base plate on the other side with attachment members, the face of the metal base plate on the other side, and top portions of the tubular external terminal connection bodies, to form insertion holes for the attachment members communicating with the through-holes and having a larger diameter than the through-holes, and to cover the one side and side faces of the metal base plate and the power semiconductor elements.
    Type: Grant
    Filed: August 4, 2009
    Date of Patent: October 30, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventors: Seiji Oka, Yoshiko Obiraki, Takeshi Oi
  • Patent number: 8258618
    Abstract: The power semiconductor module includes: a circuit substrate; power semiconductor elements joined to element mounting portions of the wiring pattern on the circuit substrate; the cylindrical external terminal communication section joined to the wiring pattern; circuit forming means for connecting between portions that require electrical connection therebetween; and transfer molding resin for sealing these components. The cylindrical external terminal communication section is a metal cylinder, and the cylindrical external terminal communication section has a hole filled with gel.
    Type: Grant
    Filed: October 12, 2009
    Date of Patent: September 4, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yoshiko Obiraki, Seiji Oka, Takeshi Oi
  • Patent number: 8253236
    Abstract: A power semiconductor device includes power semiconductor elements joined to wiring patterns of a circuit substrate, cylindrical external terminal communication sections, and wiring means for forming electrical connection between, for example, the power semiconductor elements and the cylindrical external terminal communication sections. The power semiconductor elements, the cylindrical external terminal communication sections, and the wiring means are sealed with transfer molding resin. The cylindrical external terminal communication sections are arranged on the wiring patterns so as to be substantially perpendicular to the wiring patterns, such that external terminals are insertable and connectable to the cylindrical external terminal communication sections, and such that a plurality of cylindrical external terminal communication sections among the cylindrical external terminal communication sections are arranged two-dimensionally on each of wiring patterns that act as main circuits.
    Type: Grant
    Filed: April 14, 2011
    Date of Patent: August 28, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takeshi Oi, Seiji Oka, Yoshiko Obiraki, Osamu Usui, Yasushi Nakayama
  • Patent number: 8222741
    Abstract: A semiconductor module having a current connection element designed for a high current carrying capability is disclosed. In one embodiment, the current connection element includes a plurality of metal layers which rest directly on one another.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: July 17, 2012
    Assignee: Infineon Technologies AG
    Inventors: Reinhold Bayerer, Guido Strotmann, Dirk Froebus, Reinhold Spanke
  • Patent number: 8198119
    Abstract: A method for fabricating an image sensor is described. A substrate is provided. Multiple photoresist patterns are formed over the substrate, and then a thermal reflow step is performed to convert the photoresist patterns into multiple microlenses arranged in an array. The focal length of the microlens increases from the center of the array toward the edge of the array.
    Type: Grant
    Filed: August 27, 2009
    Date of Patent: June 12, 2012
    Assignee: United Microelectronics Corp.
    Inventor: Cheng-Yu Hsieh
  • Patent number: 7692293
    Abstract: A semiconductor switching module includes a power semiconductor element that is embodied in planar technology. In at least one embodiment, the power semiconductor element is provided with a base layer, a copper layer, and at least one power semiconductor chip that is mounted on the copper layer, and another electrically conducting layer which covers at least one load terminal of the power semiconductor chip. According to at least one embodiment of the invention, devices are provided for safely connecting the load terminal to a load circuit. The devices are configured such that a contact area thereof presses in a planar manner onto the electrically conducting layer.
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: April 6, 2010
    Assignee: Siemens Aktiengesellschaft
    Inventors: Walter Apfelbacher, Norbert Reichenbach, Johann Seitz
  • Patent number: 7692211
    Abstract: A gate turn-off thyristor (GTO) device has a lower portion, an upper portion and a lid. The lower portion has a lower base region of a first conductivity type, and a lower emitter region of a second conductivity type disposed at or from a lower surface of the lower base region. A lower junction is formed between the lower base region and the lower emitter region. The upper portion has an upper base region of the second conductivity type, and upper emitter regions of the first conductivity type disposed at or from an upper surface of the upper base region. An upper-lower junction is formed between the lower base region and the upper base region, and upper junctions are formed between the upper base region and the upper emitter regions. The upper base region and upper emitter regions form an upper base surface with first conductive contacts to the upper base region alternating with second conductive contacts to the upper emitter regions. The lid has a layer of insulator with upper and lower surfaces.
    Type: Grant
    Filed: October 2, 2001
    Date of Patent: April 6, 2010
    Assignee: Silicon Power Corporation
    Inventors: Vic Temple, Forrest Holroyd, Sabih Al-Marayati, Deva Pattanayak
  • Patent number: 7579689
    Abstract: An integrated circuit package (1) comprising first and second dies on a laminate (5) in a resin encapsulating housing (6) comprises a digital signal processing integrated circuit (8) fabricated on the first die (2), and a digital-to-analogue converting circuit (9) fabricated on the second die (3). First external terminals (16) are selectively coupled to corresponding first input terminals (10) of the digital signal processing circuit (8) through corresponding primary input switches (19), and first output terminals (11) of the digital signal processing circuit (8) are selectively coupled through primary output switches (23) and secondary input switches (25) to second input terminals (12) of the digital-to-analogue converting circuit (9). Second output terminals (13) of the digital-to-analogue converting circuit (9) are selectively coupled to second external terminals (17) through secondary output switches (30).
    Type: Grant
    Filed: January 31, 2006
    Date of Patent: August 25, 2009
    Assignee: Mediatek Inc.
    Inventor: Noel A. McNamara
  • Patent number: 7573107
    Abstract: A power module that includes a power circuit assembly in which power components are electrically and mechanically connected without wires.
    Type: Grant
    Filed: September 23, 2005
    Date of Patent: August 11, 2009
    Assignee: International Rectifier Corporation
    Inventors: Alberto Guerra, Norman G. Connah, Mark Steers, George Pearson
  • Patent number: 7560773
    Abstract: A vertical-type semiconductor device for controlling a current flowing between electrodes opposed against each other across a semiconductor substrate, including: a semiconductor substrate having first and second surfaces opposed against each other; a first electrode formed in the first surface; a second electrode formed in the second surface through a high-resistance electrode whose resistance is Rs; and a third electrode formed along at least a part of the outer periphery of the second surface, wherein a potential difference Vs between the second and third electrodes is measured with a current I flowing between the first and second electrodes, and the current I is detected from the resistance Rs and the potential difference Vs.
    Type: Grant
    Filed: August 9, 2006
    Date of Patent: July 14, 2009
    Assignee: Mitsubishi Electric Corporation
    Inventor: Masahiro Tanaka
  • Patent number: 7470939
    Abstract: A semiconductor device is disclosed that includes a first and a second semiconductor package. Each semiconductor package includes a semiconductor element, a plurality of electrode members, and an encapsulating member. The semiconductor elements are interposed between the respective electrode members, and the electrode members are in electrical communication with and provide heat transfer for the respective semiconductor element. The encapsulating member encapsulates the respective semiconductor element between the respective electrode members, and an outer surface of each of the electrode members is exposed from the respective encapsulating member. Each semiconductor package includes a connecting terminal electrically coupled to one of the electrode members and extending outward so as to be exposed from the respective encapsulating member. The connecting terminals are electrically connected by abutment or via a conductive junction material.
    Type: Grant
    Filed: July 12, 2006
    Date of Patent: December 30, 2008
    Assignee: DENSO CORPORATION
    Inventors: Akira Mochida, Kuniaki Mamitsu, Kenichi Oohama
  • Patent number: 7449726
    Abstract: The power semiconductor apparatus includes a resin package made up of a power semiconductor element and a control semiconductor element which are mounted on a main front surface of a lead frame and sealed with mold resin, a power terminal led out of the resin package and electrically connected to the power semiconductor element, a control terminal led out of the resin package and electrically connected to the control semiconductor element and a cylindrical case which is formed in a manner separable from the resin package and encloses the resin package, wherein the power terminal and the control terminal are led out of lead insertion slots formed in the case, and a part of the power terminal which is led out of the case is bent along an end face of the case.
    Type: Grant
    Filed: December 14, 2006
    Date of Patent: November 11, 2008
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hidetoshi Nakanishi, Toshitaka Sekine, Taichi Obara
  • Patent number: 7256489
    Abstract: In a semiconductor apparatus in which a main current of a semiconductor device flows through a wiring pattern formed on an insulation circuit board, the rise in temperature of the wiring pattern is suppressed and the increase in cost of parts can be minimized. On the insulation circuit board, a copper pattern is formed. A heat spreader is soldered to the copper pattern, and the heat spreader is loaded with a semiconductor chip. An external electrode and the heat spreader are arranged to shorten the distance between the side of the external electrode and the side of the heat spreader.
    Type: Grant
    Filed: November 2, 2004
    Date of Patent: August 14, 2007
    Assignee: Kabushiki Kaisha Toyota Jidoshokki
    Inventors: Jun Ishikawa, Toshiaki Nagase, Hiroyuki Onishi, Koichi Akagawa
  • Patent number: 7091580
    Abstract: When a silicone gel is injected into a case, since the gel is liquid before curing, the gel attempts to rise along a minute gap formed between a front face of a first electrode and a rear face of a resin member due to capillary action. However, since the gap becomes larger at a cavity in the first electrode, the rising motion of the gel stops at the level of the cavity. More specifically, the gel is prevented from reaching portions of the first electrode and a second electrode for connection with external terminals. Further, since the rising motion of the gel can be prevented by the cavity, the first electrode and the second electrode can be arranged in a close relationship with each other.
    Type: Grant
    Filed: October 12, 2004
    Date of Patent: August 15, 2006
    Assignee: Kabushiki Kaisha Toyota Jidoshokki
    Inventors: Koichi Akagawa, Toshiaki Nagase, Hiroyuki Onishi, Jun Ishikawa
  • Patent number: 7034345
    Abstract: A novel architecture of high-power four-quadrant hybrid power modules based on high-current trench gate IGBTs and arrays of low-current wide-bandgap diodes is conceived. The distributed physical layout of high power density wide-bandgap devices improves the cooling inside a fully-sealed module case, thus avoiding excessive internal heat flux build up and high PN junction temperature, and benefiting the converter's reliability and efficiency. The design of multiple-in-one hybrid integrated AC-switch module at high power ratings is enabled by using hybrid AC switch cells and aluminum nitride substrate structure.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: April 25, 2006
    Assignee: The Boeing Company
    Inventors: Jie Chang, Xiukuan Jing, Anhua Wang, Jiajia Zhang
  • Patent number: 6995409
    Abstract: This power switching cell comprises: at least two power components (4–6) forming a chain (2) of components electrically linked in series by way of at least one intermediate bond (52, 70), and a dielectric substrate inside which are incorporated said at least two components (4–6). Each intermediate bond (52, 70) as well as the faces of the components linked to this intermediate bond are entirely incorporated inside said substrate, and the faces not linked to an intermediate bond (52, 70) of the components situated at the ends of said chain (2) are disposed in such a way as to be separated from one another by way of the dielectric material forming said substrate (22). This substrate is formed of a stack of parallel sheets (24–27) of dielectric material, and each of the components (4–6) following in said chain is incorporated in the thickness of a different sheet.
    Type: Grant
    Filed: June 1, 2004
    Date of Patent: February 7, 2006
    Assignee: Alstom
    Inventors: Fabrice Breit, Thierry Lebey
  • Patent number: 6933541
    Abstract: A family of emitter controlled thyristors employ plurality of control schemes for turning the thyristor an and off. In a first embodiment of the present invention a family of thyristors are disclosed all of which comprise a pair of MOS transistors, the first of which is connected in series with the thyristor and a second which provides a negative feedback to the thyristor gate. A negative voltage applied to the gate of the first MOS transistor causes the thyristor to turn on to conduct high currents. A zero to positive voltage applied to the first MOS gate causes the thyristor to turn off. The negative feedback insures that the thyristor only operates at its breakover boundaries of the latching condition with the NPN transistor portion of the thyristor operating in the active region. Under this condition, the anode voltage VA continues to increase without significant anode current increase.
    Type: Grant
    Filed: September 30, 1998
    Date of Patent: August 23, 2005
    Assignee: Virginia Tech Intellectual Properties, Inc.
    Inventor: Alex Q. Huang
  • Patent number: 6930333
    Abstract: A semiconductor device wiring structure is provided to reduce the wiring inductance and curtail the generation of interfering electromagnetic waves. A semiconductor chip having an anode electrode and a cathode electrode provided on two oppositely-facing main surfaces is sandwiched between a sheet-shaped anode wiring and a sheet-shaped cathode wiring. The anode and cathode electrodes of the semiconductor chip are connected to the anode and the cathode wirings, respectively, arranged such that the electric currents flowing there-through flow in opposite directions. A conductive substrate having a main surface with a larger width than the cathode wiring is disposed adjacent to the anode wiring. The edges of the cathode wiring protrude beyond the edges of both the anode wiring and the semiconductor chip in all locations and the dimension of the protrusion is at least one half of the distance from the edge of the cathode wiring to the metal substrate.
    Type: Grant
    Filed: July 6, 2004
    Date of Patent: August 16, 2005
    Assignee: Nissan Motor Co., Ltd.
    Inventor: Yoshinori Murakami
  • Patent number: 6914325
    Abstract: A power semiconductor module has a circuit assembly body, which includes a metal base, a ceramic substrate, and a power semiconductor chip, and is combined with a package having terminals formed integrally. The ceramic substrate of the module has a structure such that an upper circuit plate and a lower plate are joined to both sides of a ceramic plate, respectively, and the metal base and the ceramic substrate are fixed to one another using solder, thereby improving reliability and lengthening a life of a power semiconductor module by optimizing a ceramic substrate and a metal base thereof, the dimensions thereof, and material and method used for a join formed between the ceramic substrate and metal base.
    Type: Grant
    Filed: July 18, 2003
    Date of Patent: July 5, 2005
    Assignee: Fuji Electric Co. Ltd.
    Inventors: Takatoshi Kobayashi, Tadashi Miyasaka, Katsumi Yamada, Akira Morozumi
  • Patent number: 6885079
    Abstract: An electronic device supported on a semiconductor substrate. The semiconductor device includes a diffusion area in the substrate and a polysilicon layer extending over the substrate and contacting the diffusion area. The electronic device further includes a conductive contact covering and contacting both the polysilicon layer and the diffusion area. Therefore, the semiconductor device disclosed in this invention includes poly-to-diffusion connection for a semiconductor device that has a diffusion are and a polysilicon area. The semiconductor device further includes a contact that covers both the diffusion area and the polysilicon area with a contact filling material forming the connection between these two areas.
    Type: Grant
    Filed: October 14, 2003
    Date of Patent: April 26, 2005
    Inventor: Jeng-Jye Shau
  • Publication number: 20040262628
    Abstract: A semiconductor device includes a superlattice that, in turn, includes a plurality of stacked groups of layers. The device may also include regions for causing transport of charge carriers through the superlattice in a parallel direction relative to the stacked groups of layers. Each group of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. Moreover, the energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Accordingly, the superlattice may have a higher charge carrier mobility in the parallel direction than would otherwise be present.
    Type: Application
    Filed: November 19, 2003
    Publication date: December 30, 2004
    Applicant: RJ Mears, LLC
    Inventors: Robert J. Mears, Jean Augustin Chan Sow Fook Yiptong, Marek Hytha, Scott A. Kreps, Ilija Dukovski
  • Publication number: 20040188706
    Abstract: A novel architecture of high-power four-quadrant hybrid power modules based on high-current trench gate IGBTs and arrays of low-current wide-bandgap diodes is conceived. The distributed physical layout of high power density wide-bandgap devices improves the cooling inside a fully-sealed module case, thus avoiding excessive internal heat flux build up and high PN junction temperature, and benefiting the converter's reliability and efficiency. The design of multiple-in-one hybrid integrated AC-switch module at high power ratings is enabled by using hybrid AC switch cells and aluminum nitride substrate structure.
    Type: Application
    Filed: March 27, 2003
    Publication date: September 30, 2004
    Inventors: Jie Chang, X. Jing, Anhua Wang, Jiajia Zhang
  • Patent number: 6787815
    Abstract: A switching device for switching a plurality of RF signal lines to deliver a selected one of the RF signals to a receiver has an isolation D/U characteristic as high as 40 dB or higher. The switching device includes a mounting board made of dielectric and a matrix switch mounted thereon and implemented by one or more of SWIC. The RF signal lines in the switching device has no crossing point therebetween on either side of the mounting board to achieve the high isolation D/U ratio or lower cross-talk.
    Type: Grant
    Filed: January 14, 2003
    Date of Patent: September 7, 2004
    Assignee: NEC Compound Semiconductor Devices, Ltd.
    Inventors: Toshio Suda, Hidenori Itoh
  • Patent number: 6624448
    Abstract: A semiconductor device having a supporting member that reduces a resonance phenomenon. A pair of reinforcing members is fixed on a gate drive substrate with spacers interposed there between and upright portions of the pair of reinforcing members are fastened with screws on a side wall of a cathode flange. A spacer is fixed on the gate drive substrate and a projection of the spacer is inserted in an engaging member fixed on the bottom of the cathode fin electrode and thus fixed on the bottom of the cathode fin electrode. The pair of upright portions as the first and second supporting points and the projection of the spacer as the third supporting point stably support the gate drive substrate on the cathode fin electrode without freedom of rotation at the three positions arranged to surround an opening.
    Type: Grant
    Filed: April 2, 2001
    Date of Patent: September 23, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kazunori Taguchi, Kazuhiro Morishita, Kenji Oota
  • Patent number: 6611006
    Abstract: A power component formed in an N-type silicon substrate, the lower and upper surfaces of which respectively include a first and a second P-type region that do not extend to the component periphery, a high voltage being capable of existing between the first and second regions and having to be withstood by the junctions between the first and second regions and the substrate. A deep insulating region that does not join the first region is provided at the lower periphery of the component, the lower surface of the substrate between said deep insulating region and the first region being coated with an insulating layer, the height of the deep insulating region being greater than that of a possible soldering upward extension formed during the soldering of the lower surface on a heat sink.
    Type: Grant
    Filed: May 15, 2001
    Date of Patent: August 26, 2003
    Assignee: STMicroelectronics S.A.
    Inventor: Mathieu Roy
  • Patent number: 6605870
    Abstract: A pressure-contact type semiconductor device comprises a plurality of semiconductor elements (IGBTs) which are in pressure contact with one another, and in which first main electrodes are electrically connected to a first common main power source plate (pressure-contact type emitter electrode plate), and second main electrodes are electrically connected to a second common main power source plate (pressure-contact type collector electrode). The pressure-contact type semiconductor device also includes a common control signal board which is constituted by a printed circuit board or a multi-layered printed circuit board, and extends over spaces between rows of semiconductor elements, thereby forming a path for sending a control signal.
    Type: Grant
    Filed: February 1, 2001
    Date of Patent: August 12, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Eitaro Miyake, Satoshi Yanagisawa
  • Publication number: 20030062935
    Abstract: A switching circuit includes an insulating substrate including two signal transmission lines; a switching diode mounted, in series between the two signal transmission lines, on the insulating substrate, wherein an anode terminal and a cathode terminal are connected to the two signal transmission lines, and the switching diode is turned on or off; and a conductive pattern formed, below the switching diode, on a mounting face of the insulating substrate on which the switching diode is mounted, wherein the conductive pattern is grounded. There are stray capacitances between the anode terminal and the conductive pattern and between the cathode terminal and the conductive pattern.
    Type: Application
    Filed: September 27, 2002
    Publication date: April 3, 2003
    Applicant: Alps Electric Co., Ltd.
    Inventor: Toshiharu Yoneda
  • Publication number: 20030062535
    Abstract: A turn-off high power semiconductor device with the inner pnpn-layer structure of a Gate-Commutated Thyristor and a first gate on the cathode side has an additional second gate on the anode side, said second gate contacting the n-doped base layer and having a second gate contact. A second gate lead which is of rotationally symmetrical design and is disposed concentrically with respect to the anode contact is in contact with said second gate contact. Said second gate lead is brought out of the component and electrically insulated from the anode contact.
    Type: Application
    Filed: September 27, 2002
    Publication date: April 3, 2003
    Inventors: Eric Carroll, Oscar Apeldoorn, Peter Streit, Andre Weber
  • Publication number: 20020153532
    Abstract: A power semiconductor module comprises a metal base, plural wiring substrates provided on said the base, a first wiring substrate of the wiring substrates having a power circuit portion including a power semiconductor device, and substrate containing portions having a resin portion in which one of the wiring substrates is contained. The one of the wiring substrates is positioned in self-alignment on the metal substrate on the basis of an inner wall of the resin portion of the substrate-containing portion.
    Type: Application
    Filed: June 19, 2002
    Publication date: October 24, 2002
    Inventors: Yukio Sonobe, Akihiro Tamba, Kazuji Yamada, Ryuichi Saito, Masataka Sasaki, Tatsuya Shigemura, Kazuhiro Suzuki, Shigeki Sekine
  • Patent number: 6445013
    Abstract: A first cathode flange (14) provided with branch-like protrusions (14d) extending towards substantially its outer periphery and a gate flange (15) provided with branch-like protrusions (15c) extending towards substantially its outer periphery are connected to a cathode electrode (7a) and a gate electrode (7b), respectively, formed on one surface of a gate drive substrate (7). With this structure, a gate commutated turn-off semiconductor device which eliminates the necessity of a gate spacer and a cathode spacer and allows reduction in time and cost required for manufacture can be achieved.
    Type: Grant
    Filed: April 13, 2000
    Date of Patent: September 3, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Kazunori Taguchi
  • Publication number: 20020109151
    Abstract: An integrated device in emitter-switching configuration is described. The device is integrated in a chip of semiconductor material of a first conductivity type which has a first surface and a second surface opposite to each other. The device comprises a first transistor having a base region, an emitter region and a collector region, a second transistor having a not drivable terminal for collecting charges which is connected with the emitter terminal of the first transistor, a quenching element of the first transistor which discharges current therefrom when the second transistor is turned off. The quenching element comprises at least one Zener diode made in polysilicon which is coupled with the base terminal of the first transistor and with the other not drivable terminal of the second transistor.
    Type: Application
    Filed: December 21, 2001
    Publication date: August 15, 2002
    Applicant: STMicroelectronics S.r.l.
    Inventor: Sergio Tommaso Spampinato
  • Patent number: 6323547
    Abstract: In a GCT device which controls large current at the operating frequency of 1 kHz or more, a ring-shaped gate terminal (10) is made of a magnetic material with the maximum permeability of 15,000 or less in the CGS Gaussian system of units. Further, in the outer end portion of an outer plane portion (10O) of the ring-shaped gate terminal (10), a plurality of slits extending diametrically are provided along the circumference to be coupled to mounting holes (10b).
    Type: Grant
    Filed: December 18, 1998
    Date of Patent: November 27, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toshinobu Kawamura, Katsumi Satoh, Mikio Bessho
  • Patent number: 6166402
    Abstract: A double circular gate conductor 9 comprises a first circular gate conductor 7 connected to a gate electrode 2a, a second circular gate conductor 8, and a connecting conductor which connects the first circular gate conductor 7 and the second circular gate conductor 8, and is configured so as to equalize the voltage drop due to self-inductance or mutual inductance between the first circular gate conductor 7, second circular gate conductor 8 and cathode post electrode 4. In this manner it is possible to guarantee more or less uniform parallel inductance over the surface of the element.
    Type: Grant
    Filed: June 18, 1999
    Date of Patent: December 26, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuya Kodani, Toshiaki Matsumoto, Masayuki Tobita
  • Patent number: 6128200
    Abstract: A butt-joint CPU mounting structure includes a connector having two opposite faces. Each face has a receiving slot disposed therein adapted to respectively and receivingly engage with a CPU module and an edge of a main board of a computer thereby connecting the CPU module to the main board. The receiving slots are arranged in alignment with each other whereby the CPU module is substantially coplanar with the main board. A CPU holder includes two support members each defining a channel for receiving opposite side flanges of the connector. Bolts are used to secure the support members to the side flanges of the connector. The CPU module is received between the two support members whereby opposite edges of the CPU module are engaged and supported by the support members. A connection member is connected between the two support members for strengthening the mechanical structure thereof. The support members are provided with bolt holes through which bolts extend for engaging with a housing of the computer.
    Type: Grant
    Filed: February 18, 1999
    Date of Patent: October 3, 2000
    Inventor: Ho-Kang Chu
  • Patent number: 5821618
    Abstract: A semiconductor component includes an insulating housing. A plurality of sheet-metal mounting plates are disposed in one and the same plane and are electrically separated from one another in the housing. Semiconductor switches of a rectifier bridge are electrically conductively secured to the mounting plates. Sheet-metal connection leads are electrically connected to the semiconductor switches. At least one sheet-metal connection lead is electrically connected to the mounting plates.
    Type: Grant
    Filed: August 14, 1995
    Date of Patent: October 13, 1998
    Assignee: Siemens Aktiengesellschaft
    Inventors: Alfons Graf, Peter Huber, Xaver Schloegel, Peter Sommer
  • Patent number: 5777351
    Abstract: A compression bonded type semiconductor element having a ring-shaped gate terminal in the form of an annular metal disk projecting through the side of an insulating cylinder. The ring-shaped gate terminal includes an inner circumferential planar portion which is disposed so as to be slidable on an annular ring gate electrode. The annular ring gate electrode is in contact with a gate electrode formed on a semiconductor substrate, and the ring gate electrode is pressed against the gate electrode via the ring-shaped gate terminal by an elastic body.
    Type: Grant
    Filed: January 7, 1997
    Date of Patent: July 7, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kazunori Taguchi, Yuzuru Konishi
  • Patent number: 5739556
    Abstract: In a pressure contact housing for semiconductor components, the gate electrode contact ring 4 is provided with spiral recesses 5. The latter can absorb axial movements produced during the assembly of the housing, without loading the material. A good and durable electrical contact between the gate electrode and the gate electrode contact ring is obtained thereby.
    Type: Grant
    Filed: February 1, 1996
    Date of Patent: April 14, 1998
    Assignee: Asea Brown Boveri AG
    Inventor: Fabio Bolgiani
  • Patent number: 5652467
    Abstract: An auxiliary cathode lead is contacted to a cathode buffer electrode which contacts to an unit GTO arranged at the most remote region from a gate pressure contacting portion of a GTO pellet and the push-into effect of the auxiliary cathode current during the turn-off can be remarkably performed. Without inviting bad affects such as the increase in "on" voltage, it is proposed a package structure of a semiconductor which the unit GTO arranged remote from a gate is easily to perform the turn-off. The maximum turn-off current can be heightened, it can easily correspond to the increase in the diameter of the pellet according to the large current of the unit element. Further, a condenser of a snubber circuit as a protection circuit of the unit GTO in a power inverter can be small, and the snubber loss can be lessened.
    Type: Grant
    Filed: July 27, 1995
    Date of Patent: July 29, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Hidekatsu Onose, Shuroku Sakurada