Abstract: A thin-film transistor substrate and a display apparatus including the same includes a first thin-film transistor on a substrate. The first thin-film transistor includes a first semiconductor layer having a first channel area, a first source area, and a first drain area; a first lower gate electrode between the substrate and the first semiconductor layer; a first upper gate electrode on the first semiconductor layer and overlapping the first channel area; and a first electrode layer on the first upper gate electrode and electrically connected to at least one of the first source area and the first drain area. The first lower gate electrode overlaps the first channel area and the first drain area.

Abstract: The present disclosure addresses thermal issues in a multi gate finger field-effect transistor (FET) by providing a multi-gate finger FET arrangement where the respective distances between the multiple gate fingers are modulated along the device, such that the distances between the gate fingers in or towards the middle of the device are greater than the distances between the gate fingers at the or towards the edge of the device. By providing the greater distances between gate fingers located in or towards the middle of the device then improved thermal management properties are obtained, and the device as a whole is maintained cooler than would otherwise be the case, with associated improvements in device lifetimes.

Abstract: A method includes performing an epitaxy to grow a semiconductor layer, which includes a top portion over a semiconductor region. The semiconductor region is between two insulation regions that are in a substrate. The method further includes recessing the insulation regions to expose portions of sidewalls of the semiconductor region, and etching a portion of the semiconductor region, wherein the etched portion of the semiconductor region is under and contacting a bottom surface of the semiconductor layer, wherein the semiconductor layer is spaced apart from an underlying region by an air gap. A gate dielectric and a gate electrode are formed over the semiconductor layer.

Abstract: A method includes performing an epitaxy to grow a semiconductor layer, which includes a top portion over a semiconductor region. The semiconductor region is between two insulation regions that are in a substrate. The method further includes recessing the insulation regions to expose portions of sidewalls of the semiconductor region, and etching a portion of the semiconductor region, wherein the etched portion of the semiconductor region is under and contacting a bottom surface of the semiconductor layer, wherein the semiconductor layer is spaced apart from an underlying region by an air gap. A gate dielectric and a gate electrode are formed over the semiconductor layer.

Abstract: Apparatuses and methods for modulating current/voltage response using multiple semi-conductive channel regions (SCR) produced from different integrated semiconductor structures are provided. In particular, embodiments include systems and methods for controlling current or mitigating electromagnetic or radiation interference effects using combined integrated functions of a lateral double-diffused metal-oxide semiconductor field effect transistor (LDMOSFET) and junction field effect transistor (JFET) disposed in proximity of a LDMOSFET's SCR within a certain orientation forming a second SCR.

Abstract: A gate dielectric material and a gate conductor portion are formed on a single-crystal semiconductor material of a substrate. A dielectric structure is then formed surrounding the gate conductor portion and thereafter a stressor layer is formed on the dielectric structure. A controlled spalling process is then performed and thereafter a material removal process can be used to expose a surface of the single-crystal semiconductor material. A source region and a drain region are then formed on the exposed surface of the single-crystal semiconductor material, which exposed surface is opposite the surface including the gate dielectric.

Abstract: A semiconductor device includes a substrate including a first active region, a second active region and a field region between the first and second active regions, and a gate structure formed on the substrate to cross the first active region, the second active region and the field region. The gate structure includes a p type metal gate electrode and an n-type metal gate electrode directly contacting each other, the p-type metal gate electrode extends from the first active region less than half way toward the second active region.

Abstract: A highly reliable semiconductor device that includes a transistor including an oxide semiconductor is provided. In a semiconductor device which includes a bottom-gate transistor including an oxide semiconductor film, the spin density of the oxide semiconductor film is lower than or equal to 1×1018 spins/cm3, preferably lower than or equal to 1×1017 spins/cm3, further preferably lower than or equal to 1×1016 spins/cm3. The conductivity of the oxide semiconductor film is lower than or equal to 1×103 S/cm, preferably lower than or equal to 1×102 S/cm, further preferably lower than or equal to 1×101 S/cm.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a gate, a channel layer, a gate insulation layer, a source, a drain and a silicon-aluminum-oxide layer. The gate is disposed on a substrate. The channel layer is disposed on the substrate. The channel layer overlaps the gate. The gate insulation layer is disposed between the gate and the channel layer. The source and the drain are disposed on two sides of the channel layer. The silicon-aluminum-oxide layer is disposed on the substrate and covers the source, the drain and the channel layer.

Abstract: An LCD device includes dual gate transistors provided to an output portion of the shift register for outputting a gate voltage. As such, the charge/discharge time of the output portion is reduced so the response time of liquid crystal is improved.

Abstract: A semiconductor substrate of a semiconductor device includes a body region of a first conductivity type, a drift region of a second conductivity type coming into contact with a lower surface of the body region, a gate electrode that is provided in a gate trench passing through the body region and extending to the drift region and faces the body region, and a gate insulator that is provided between the gate electrode and a wall surface of the gate trench. An inverted U-shaped section is formed in a lower surface of the gate insulator, and a floating region of the first conductivity type is formed in the inverted U-shaped section. The floating region protrudes under a portion that is located at a lowermost portion in the lower surface of the gate insulator.

Abstract: According to an embodiment of the disclosed technology, a manufacture method of an organic thin film transistor array substrate is provided. The method comprises: forming a first pixel electrode, a source electrode, a drain electrode and a data line in a first patterning process; forming an organic semiconductor island and a gate insulating island in a second patterning process; forming a data pad region in a third patterning process; and forming a second pixel electrode, a gate electrode and a gate line in a fourth patterning process.

Abstract: The present disclosure provides a semiconductor switching device including a substrate having deposited thereon a cathode, an anode and a gate of the semiconductor switching device, and a connection means for electrically connecting the cathode in the gate of the semiconductor switching device to an external circuit unit. The connection includes a cathode-gate connection unit having a coaxial structure including a gate conductor and a cathode conductor for electrically connecting the cathode and the gate of the semiconductor switching device to the external circuit unit.

Abstract: A structure and method of fabricating the structure. The structure includes a first region of a semiconductor substrate separated from a second region of the semiconductor substrate by trench isolation formed in the substrate; a first stressed layer over the first region; a second stressed layer over second region; the first stressed layer and second stressed layer separated by a gap; and a passivation layer on the first and second stressed layers, the passivation layer extending over and sealing the gap.

Abstract: Provided is a crystalline silicon thin film semiconductor device which is capable of reducing off-state leakage current and has excellent current rising characteristics. The thin film transistor includes a semiconductor layer formed of an amorphous silicon layer and a crystalline silicon layer. A drain electrode is provided in direct contact with the crystalline silicon layer of the semiconductor layer, to thereby improve the current rising characteristics.

Abstract: A semiconductor device and a method of manufacturing the same are provided. A multi-component high-k interface layer containing elements of the substrate is formed from a ultra-thin high-k dielectric material in a single-layer structure of atoms by rapid annealing in the manufacturing of a CMOS transistor by the replacement gate process, and a high-k gate dielectric layer with a higher dielectric constant and a metal gate layer are formed thereon. The EOT of the device is effectively decreased, and the diffusion of atoms in the high-k gate dielectric layer from an upper level thereof is effectively prevented by the optimized high-k interface layer at high-temperature treatment. Thus, the present invention may also avoid the growth of the interface layers and the degradation of carrier mobility.

Abstract: Disclosed herein is a field effect transistor (FET), device including a FET, and a method of making the same. In embodiments of the disclosure, a semiconductor-on-insulator (SOI) substrate is provided. The SOI substrate includes a body having a first conductivity type formed in the semiconductor layer of the SOI substrate, the body including a first body region connecting a second body region to a third body region; and a source and a drain, each having a second conductivity type, disposed on opposite sides of the first body region. A first gate electrode having a second work function is disposed above the first body region; and a second gate electrode having a first work function disposed above the second and third body regions. A first gate dielectric layer may be disposed vertically between the first body region and the first gate electrode, and a second gate dielectric layer may be disposed vertically between the second and third body regions and the second gate electrode.

Abstract: An etchant composition that allows simplification and optimization of semiconductor manufacturing process is presented, along with a method of patterning a conductive layer using the etchant and a method of manufacturing a flat panel display using the etchant. The etchant includes nitric acid, phosphoric acid, acetic acid, and an acetate compound in addition to water.

Abstract: An apparatus and method for storing information are provided, including using a transistor having a channel, a gate oxide layer, a gate electrode, and a modifiable gate stack layer. The on-resistance of the transistor is changed by causing a non-charge-storage based physical change in the modifiable gate stack layer, to store information.

Abstract: An integrated circuit includes a first field effect transistor of a first carrier type and a second field effect transistor of a second, different carrier type. In a conductive state, a first channel of the first field effect transistor is oriented to one of a first set of equivalent crystal planes of a semiconductor substrate and a second channel of the second field effect transistor is oriented to at least one of a second, different set of equivalent crystal planes. The first set of equivalent crystal planes is parallel to a main surface of the semiconductor substrate and the second set of equivalent crystal planes is perpendicular to the main surface.

Abstract: A method of manufacturing a local recess channel transistor in a semiconductor device. A hard mask layer is formed on a semiconductor substrate that exposes a portion of the substrate. The exposed portion of the substrate is etched using the hard mask layer as an etch mask to form a recess trench. A trench spacer is formed on the substrate along a portion of sidewalls of the recess trench. The substrate along a lower portion of the recess trench is exposed after the trench spacer is formed. The exposed portion of the substrate along the lower portion of the recess trench is doped with a channel impurity to form a local channel impurity doped region surrounding the lower portion of the recess trench. A portion of the local channel impurity doped region surrounding the lower portion of the recess trench is doped with a Vth adjusting impurity to form a Vth adjusting impurity doped region inside the local channel impurity doped region. The width of the lower portion of the recess trench is expanded.

Abstract: An electrically programmable device with embedded EEPROM and method for making thereof. The method includes providing a substrate including a first device region and a second device region, growing a first gate oxide layer in the first device region and the second device region, and forming a first diffusion region in the first device region and a second diffusion region and a third diffusion region in the second device region. Additionally, the method includes implanting a first plurality of ions to form a fourth diffusion region in the first device region and a fifth diffusion region in the second device region. The fourth diffusion region overlaps with the first diffusion region.

Abstract: A semiconductor switching module includes a power semiconductor element that is embodied in planar technology. In at least one embodiment, the power semiconductor element is provided with a base layer, a copper layer, and at least one power semiconductor chip that is mounted on the copper layer, and another electrically conducting layer which covers at least one load terminal of the power semiconductor chip. According to at least one embodiment of the invention, devices are provided for safely connecting the load terminal to a load circuit. The devices are configured such that a contact area thereof presses in a planar manner onto the electrically conducting layer.

Abstract: A semiconductor power device includes a semiconductor body with a plurality of gate trenches formed therein. Disposed within each gate trench is a spacer gate that extends along at least a portion of the sidewalls of the gate trench but not along at least a portion of the bottom surface of the trench. The spacer gate of each gate trench may also include a layer of silicide along outer surfaces thereof. The semiconductor body may include a channel region and each gate trench may extend through the channel region and into the semiconductor body. Formed at the bottom of each gate trench within the semiconductor body may be a tip implant of the same conductivity as the semiconductor body. In addition, a deep body implant of the same conductivity as the channel region may be formed at the base of the channel region.

Abstract: A method of manufacturing a local recess channel transistor in a semiconductor device. A hard mask layer is formed on a semiconductor substrate that exposes a portion of the substrate. The exposed portion of the substrate is etched using the hard mask layer as an etch mask to form a recess trench. A trench spacer is formed on the substrate along a portion of sidewalls of the recess trench. The substrate along a lower portion of the recess trench is exposed after the trench spacer is formed. The exposed portion of the substrate along the lower portion of the recess trench is doped with a channel impurity to form a local channel impurity doped region surrounding the lower portion of the recess trench. A portion of the local channel impurity doped region surrounding the lower portion of the recess trench is doped with a Vth adjusting impurity to form a Vth adjusting impurity doped region inside the local channel impurity doped region. The width of the lower portion of the recess trench is expanded.

Abstract: A vertical-type semiconductor device for controlling a current flowing between electrodes opposed against each other across a semiconductor substrate, including: a semiconductor substrate having first and second surfaces opposed against each other; a first electrode formed in the first surface; a second electrode formed in the second surface through a high-resistance electrode whose resistance is Rs; and a third electrode formed along at least a part of the outer periphery of the second surface, wherein a potential difference Vs between the second and third electrodes is measured with a current I flowing between the first and second electrodes, and the current I is detected from the resistance Rs and the potential difference Vs.

Abstract: To provide a thin film integrated circuit at low cost and with thin thickness, which is applicable to mass production unlike the conventional glass substrate or the single crystalline silicon substrate, and a structure and a process of a thin film integrated circuit device or an IC chip having the thin film integrated circuit. A manufacturing method of a semiconductor device includes the steps of forming a first insulating film over one surface of a silicon substrate, forming a layer having at least two thin film integrated circuits over the first insulating film, forming a resin layer so as to cover the layer having the thin film integrated circuit, forming a film so as to cover the resin layer, grinding a backside of one surface of the silicon substrate which is formed with the layer having the thin film integrated circuit, and polishing the ground surface of the silicon substrate.

Abstract: The power semiconductor apparatus includes a resin package made up of a power semiconductor element and a control semiconductor element which are mounted on a main front surface of a lead frame and sealed with mold resin, a power terminal led out of the resin package and electrically connected to the power semiconductor element, a control terminal led out of the resin package and electrically connected to the control semiconductor element and a cylindrical case which is formed in a manner separable from the resin package and encloses the resin package, wherein the power terminal and the control terminal are led out of lead insertion slots formed in the case, and a part of the power terminal which is led out of the case is bent along an end face of the case.

Abstract: A process for forming a conductive gate structure for a sub-0.25 MOSFET technology, has been developed. The process features a conductive gate structure defined from a composite polysilicon or amorphous layer, which in turn is obtained via a dual deposition procedure. The first, or underlying silicon layer of the composite silicon layer, is deposited using a first silane flow rate which results in a silicon layer offering good performance characteristics but comprised with large silicon bumps. The second or overlying silicon layer of the composite silicon layer, is next deposited using a second silane flow rate, with the second silane flow greater than the silane flow used for the underlying silicon layer. The second silicon layer is formed with silicon bumps smaller in size than the silicon bumps of the first silicon layer.

Abstract: A dual-gate transistor includes a first gate formed on a substrate, a first dielectric layer covering the first gate and the substrate, a semiconductor layer formed on the first dielectric layer, first and second electrodes formed on the semiconductor layer and spaced with an interval in order to separate each other, a second dielectric layer covering the first and second electrodes, and a second gate formed on the second dielectric layer, in which at least one of the first and second gates is non-overlapped with the second electrode.

Abstract: The purpose of the present invention is to provide a small-sized switch attaining high isolation of not less than 80 dB, maintaining low insertion loss also in high frequencies not less than 60 GHz. A semiconductor switch according to the present invention utilizes FETs a gate electrode, a source electrode, and a drain electrode of each of which are formed on a semiconductor. The source electrode and the drain electrode are connected with the earth as well as are disposed in parallel to each other, and the gate electrode is formed between the source electrode and the drain electrode, and both the ends of the gate electrode are connected to the first input-output terminal 1 and the second input-output terminal.

Abstract: A switching semiconductor device includes a first compound layer formed on a single crystal substrate which includes silicon carbide or sapphire, and including a general formula InxGa1-xN, where 0?x?1; a second compound layer formed on the first compound layer, and including a general formula InyALzGa1-y-zN, where 0?y?1 and 0<z?1; and a gate electrode formed on the second compound layer. The gate electrode is electrically connected to a resistance element formed on a first interlayer insulating film that covers the gate electrode, through a metal wiring formed on a second interlayer insulating film that covers the first interlayer insulating film.

Abstract: An aspect of the present invention includes a first conductive type semiconductor region; a gate electrode formed on the first conductive type semiconductor region; a channel region formed immediately below the gate electrode in the first conductive type semiconductor region; and a second conductive type first diffusion layer constituting source/drain regions formed at opposite sides of the channel region in the first conductive type semiconductor region, the gate electrode being formed of polycrystalline silicon-germanium, in which a germanium concentration is continuously increased from a drain region side to a source region side, and an impurity concentration immediately below the gate electrode in the first conductive type semiconductor region being continuously increased from the source region side to the drain region side in accordance with the germanium concentration in the gate electrode.

Abstract: An aspect of the present invention includes a first conductive type semiconductor region; a gate electrode formed on the first conductive type semiconductor region; a channel region formed immediately below the gate electrode in the first conductive type semiconductor region; and a second conductive type first diffusion layer constituting source/drain regions formed at opposite sides of the channel region in the first conductive type semiconductor region, the gate electrode being formed of polycrystalline silicon-germanium, in which a germanium concentration is continuously increased from a drain region side to a source region side, and an impurity concentration immediately below the gate electrode in the first conductive type semiconductor region being continuously increased from the source region side to the drain region side in accordance with the germanium concentration in the gate electrode.

Abstract: The present invention relates to a method of manufacturing a semiconductor device having an excellent gettering effect. In this method, when phosphorus is added to a poly-Si film, which has been crystallized by the addition of a metal, to subject the resultant poly-Si film to the heat treatment to carry out gettering therefor, the device is performed for the shape of the island-like insulating film on the poly-Si film which is employed when implanting phosphorus. Thereby, the area of the boundary surface between the region to which phosphorus has been added and the region to which no phosphorus has been added is increased to enhance gettering efficiency.

Abstract: A low control voltage switch utilizing a plurality of field effect transistors (FETs) having a total of six gates to allow the switch to operate at a low control voltage without the need to increase device periphery or die size. Feed-forward capacitors connected between the gate and source of an uppermost FET and the gate and drain of a lowermost FET are used to reduce signal distortion and improve the linearity and harmonic noise rejection characteristics of the FETs within the switch and thus lower the harmonics of the switch.

Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Abstract: An insulating film (12) is formed on a substrate (11), and an aperture (121) is formed in the prescribed position on the surface of the insulating film (12) perpendicular to such surface, and an amorphous silicon film (13) having a prescribed thickness is formed on the insulating film (12). Subsequently, the amorphous silicon film (13) is changed to a polycrystalline silicon film (13) by a solid-phase growth through a heat treatment. The polycrystalline silicon film (13) is irradiated by a laser under a prescribed condition, and the polycrystalline silicon inside the bottom part of the aperture (121) is maintained in an unmelted state while other parts of the polycrystalline silicon film are completely melted, so that the unmelted polycrystalline silicon can be used as a crystal nucleus for crystal growth, and the area around the aperture (121) in the polycrystalline silicon film is changed to a silicon film in a substantially single crystal state.

Abstract: An aspect of the present invention includes a first conductive type semiconductor region formed in a semiconductor substrate, a gate electrode formed on the first conductive type semiconductor region, a channel region formed immediately below the gate electrode in the first conductive type semiconductor region, and a second conductive type first diffusion layers constituting source/drain regions formed at opposite sides of the channel region in the first conductive type semiconductor region, the gate electrode being formed of polycrystalline silicon-germanium, in which the germanium concentration of at least one of the source side and the drain side is higher than that of the central portion.

Abstract: A novel and very useful method for forming a crystal silicon film by introducing a metal element which promotes crystallization of silicon to an amorphous silicon film and for eliminating or reducing the metal element existing within the crystal silicon film thus obtained is provided. The method for fabricating a semiconductor device comprises steps of intentionally introducing the metal element which promotes crystallization of silicon to the amorphous silicon film and crystallizing the amorphous silicon film by a first heat treatment to obtain the crystal silicon film; eliminating or reducing the metal element existing within the crystal silicon film by implementing a second heat treatment within an oxidizing atmosphere; eliminating a thermal oxide film formed in the previous step; and forming another thermal oxide film on the surface of the region from which the thermal oxide film has been eliminated by implementing another thermal oxidation.

Abstract: A turn-off high power semiconductor device with the inner pnpn-layer structure of a Gate-Commutated Thyristor and a first gate on the cathode side has an additional second gate on the anode side, said second gate contacting the n-doped base layer and having a second gate contact. A second gate lead which is of rotationally symmetrical design and is disposed concentrically with respect to the anode contact is in contact with said second gate contact. Said second gate lead is brought out of the component and electrically insulated from the anode contact.

Abstract: An electrode wiring structure is disclosed which realizes a semiconductor apparatus as a power semiconductor module with the current path set as shortest as possible and uniformly. The semiconductor apparatus includes: a plurality of semiconductor devices mounted in one array or more on a substrate; a main current electrode mounted along the array(s) of the semiconductor devices, and commonly connected to each of the plurality of semiconductor devices through the substrate. The substrate is connected to the main current electrode through a plurality of wires arranged along the array(s) at equal or substantially equal distances.

Abstract: A novel and very useful method for forming a crystal silicon film by introducing a metal element which promotes crystallization of silicon to an amorphous silicon film and for eliminating or reducing the metal element existing within the crystal silicon film thus obtained is provided. The method for fabricating a semiconductor device comprises steps of intentionally introducing the metal element which promotes crystallization of silicon to the amorphous silicon film and crystallizing the amorphous silicon film by a first heat treatment to obtain the crystal silicon film; eliminating or reducing the metal element existing within the crystal silicon film by implementing a second heat treatment within an oxidizing atmosphere; eliminating a thermal oxide film formed in the previous step; and forming another thermal oxide film on the surface of the region from which the thermal oxide film has been eliminated by implementing another thermal oxidation.

Abstract: The present invention provides semiconductor devices having at least one silicon region in a silicon carbide wafer in which is fabricated a low voltage semiconductor device such as for example, MOSFET devices, BiCMOS devices, Bipolar devices, etc., and on the same chip, at least one silicon carbide region in which is fabricated a high voltage (i.e., >1000V) semiconductor device using techniques well known in the art, such as for example, LDMOSFET, UMOSFET, DMOSFET, IGBT, MESFET, and JFET devices.

Abstract: A thin film transistor having an improved reliability and a method of manufacturing the same are provided, which can produce a high quality thin film transistor device and array. The manufacturing method includes the steps of: forming a poly-Si island on a substrate; depositing a silicon oxide layer to cover the substrate and the poly-Si island, and then depositing a silicon nitride layer on the silicon oxide layer; forming a metal layer on the silicon nitride layer, and then patterning the metal layer to form a gate; using the gate as a mask and etching the silicon nitride layer to remove a portion of the silicon nitride layer, which is not covered by the gate; forming source/drain regions in the poly-Si layer on both sides of the gate, and then depositing an interlayer to cover the silicon oxide layer and the gate; and forming contact holes in the interlayer and the silicon oxide layer above the source/drain regions, and then filling conductive plugs in the contact holes.

Abstract: This invention relates to a pressure-contact type semiconductor device (1) having a ring-shaped gate terminal, and aims at overcoming such a technical problem that a gate current is not uniformly supplied to a semiconductor substrate (4) due to a connection structure for the device (1) and an external gate driver (2). For this purpose, a ring-shaped gate terminal (10) is structured as a resistor whose resistivity is at least 0.1 m&OHgr;·cm in the present invention. Thus, a voltage drop by the aforementioned resistor enlarges in a concentrated part of the gate current, and it follows that the gate current is shunted to another non-concentrated part. The present invention is utilizable as a high-power element in a power applied device.

Abstract: A double circular gate conductor 9 comprises a first circular gate conductor 7 connected to a gate electrode 2a, a second circular gate conductor 8, and a connecting conductor which connects the first circular gate conductor 7 and the second circular gate conductor 8, and is configured so as to equalize the voltage drop due to self-inductance or mutual inductance between the first circular gate conductor 7, second circular gate conductor 8 and cathode post electrode 4. In this manner it is possible to guarantee more or less uniform parallel inductance over the surface of the element.

Abstract: An MCT is formed as a four-layer device, using alternating cells of: (a) P diffusions in an N.sup.- wafer having lower N.sup.+ and P.sup.+ layers with N.sup.+ cathode regions in the P diffusions, and (b) shallow P.sup.+ diverter cells. A cathode electrode is connected to the N.sup.+ cathodes, but not to the P diffusions containing the N.sup.+ cathode regions. The alternating cells are arranged in checkerboard fashion with the cells of any given row having a narrow spacing to define a narrow turn-off channel and the rows being more widely spaced to define a conduction channel having a reduced inherent JFET resistance.

Abstract: In a surface of a silicon substrate of one conductivity type, there are formed a plurality of depressions or recesses, gate regions of opposite conductivity type are formed at bottoms of respective recesses, gate electrodes are provided on respective gate regions, and an electrically conductive block is joined to the surface of the semiconductor substrate. Between the surface of the semiconductor substrate and the electrically conductive block a contact region having a high impurity concentration and/or an electrically conductive material layer may be provided in order to improve electrical and mechanical properties of the contact between the semiconductor substrate and the electrically conductive block. The gate region can have a high impurity concentration and a distance between a channel region and the electrically conductive block can be very small.

Abstract: The power thyristor of this invention has a cellular emitter structure. Each cell also has a FET assisted turn-on gate integrated into the cell. A turn-on gate voltage of one polarity is applied to a FET gate element that overlies the surface of the cell and to the turn-on gate integrated into the cell. When this voltage is so applied, a channel underlying the FET gate element becomes conductive, which allows the integrated turn-on gate to provide drive to the upper base-upper emitter junction of the thyristor cell thereby turning the thyristor cell on.