With Lattice Constant Mismatch (e.g., With Buffer Layer To Accommodate Mismatch) Patents (Class 257/190)
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Patent number: 9748453Abstract: A semiconductor light emitting device includes a substrate formed of a first material; and a convex portion protruding from the substrate and including: a first layer formed of the first material as that of the substrate; and a second layer formed of a second material different from the first material and disposed on the first layer. A second height of the second layer is greater than a first height of the first layer.Type: GrantFiled: May 4, 2016Date of Patent: August 29, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong Hak Kim, Tan Sakong, Eun Deok Sim, Jeong Wook Lee, Jin Young Lim, Byoung Kyun Kim
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Patent number: 9741765Abstract: Provided is a monolithic integration of resistive memory with complementary metal oxide semiconductor using integrated circuit foundry processes. A memory device is provided that includes a substrate comprising one or more complementary metal-oxide semiconductor devices, a first insulator layer formed on the substrate; and a monolithic stack. The monolithic stack includes multiple layers fabricated as part of a monolithic process over the first insulator layer. The multiple layers include a first metal layer, a second insulator layer, and a second metal layer. A resistive memory device structure is formed within the second insulator layer and within a thermal budget of the one or more complementary metal-oxide semiconductor devices. The resistive memory device structure is implemented as a pillar device or as a via device. Further, the first metal layer is coupled to the second metal layer.Type: GrantFiled: December 31, 2014Date of Patent: August 22, 2017Assignee: CROSSBAR, INC.Inventors: Sundar Narayanan, Steve Maxwell, Natividad Vasquez, Jr., Harry Yue Gee
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Patent number: 9735155Abstract: A bulk SiGe FinFET which includes: a plurality of SiGe fins and a bulk semiconductor substrate, the SiGe fins extending from the bulk semiconductor substrate; the SiGe fins having a top portion and a bottom portion, a part of the bottom portion being doped to form a punchthrough stop; the bulk semiconductor substrate having a top portion in contact with the SiGe fins and comprising a gradient of germanium and silicon, and a bottom portion of silicon in contact with the top portion such that the gradient has a composition of SiGe at the top portion in contact with the SiGe fins that is the same composition of SiGe as in the SiGe fins, the proportion of germanium atoms in the gradient gradually decreasing and the proportion of silicon atoms in the gradient gradually increasing in the gradient until the top portion contacts the bottom portion.Type: GrantFiled: December 14, 2015Date of Patent: August 15, 2017Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Juntao Li, Shogo Mochizuki
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Patent number: 9735058Abstract: A performance optimized CMOS FET structure and methods of manufacture are disclosed. The method includes forming source and drain regions for a first type device and a second type device. The method further includes lowering the source and drain regions for the first type device, while protecting the source and drain regions for the second type device. The method further includes performing silicide processes to form silicide regions on the lowered source and drain regions for the first type device and the source and drain regions for the second type device.Type: GrantFiled: July 15, 2016Date of Patent: August 15, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Paul Chang, Katsunori Onishi, Jian Yu
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Patent number: 9735160Abstract: A method of forming a semiconductor device that includes forming an at least partially relaxed semiconductor material, and forming a plurality of fin trenches in the partially relaxed semiconductor material. At least a portion of the plurality of fin trenches is filled with a first strained semiconductor material that is formed using epitaxial deposition. A remaining portion of the at least partially relaxed semiconductor material is removed to provide a plurality of fin structure of the first strained semiconductor material.Type: GrantFiled: May 4, 2016Date of Patent: August 15, 2017Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
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Patent number: 9722097Abstract: A semiconductor device is provided. The semiconductor device includes a substrate; a well region disposed in the substrate; an isolation structure surrounding an active region in the well region; a source region disposed in the well region; a drain region disposed in the well region; a second conductive type first doped region disposed in the well region and disposed along a periphery of the active region; a second conductive type second doped region disposed in the well region and under the source region, the drain region and the second conductive type first doped region, wherein the second conductive type second doped region is in direct contact with the second conductive type first doped region; a source electrode; a drain electrode and a gate electrode. The present disclosure also provides a method for manufacturing the semiconductor device.Type: GrantFiled: September 16, 2015Date of Patent: August 1, 2017Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Karuna Nidhi, Federico Agustin Altolaguirre, Ming-Dou Ker, Geeng-Lih Lin
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Patent number: 9711416Abstract: A semiconductor fin including a single crystalline semiconductor material is formed on a dielectric layer. A semiconductor shell including an epitaxial semiconductor material is formed on all physically exposed surfaces of the semiconductor fin by selective epitaxy, which deposits the semiconductor material only on semiconductor surfaces and not on dielectric surfaces. The epitaxial semiconductor material can be different from the single crystalline semiconductor material, and the semiconductor shell can be bilaterally strained due to lattice mismatch. A fin field effect transistor including a strained channel can be formed. Further, the semiconductor shell can advantageously alter properties of the source and drain regions, for example, by allowing incorporation of more dopants or by facilitating a metallization process.Type: GrantFiled: July 11, 2016Date of Patent: July 18, 2017Assignee: International Business Machines CorporationInventors: Kevin K. Chan, Young-Hee Kim, Masaharu Kobayashi, Jinghong Li, Dae-Gyu Park
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Patent number: 9711417Abstract: A semiconductor fin including a single crystalline semiconductor material is formed on a dielectric layer. A semiconductor shell including an epitaxial semiconductor material is formed on all physically exposed surfaces of the semiconductor fin by selective epitaxy, which deposits the semiconductor material only on semiconductor surfaces and not on dielectric surfaces. The epitaxial semiconductor material can be different from the single crystalline semiconductor material, and the semiconductor shell can be bilaterally strained due to lattice mismatch. A fin field effect transistor including a strained channel can be formed. Further, the semiconductor shell can advantageously alter properties of the source and drain regions, for example, by allowing incorporation of more dopants or by facilitating a metallization process.Type: GrantFiled: July 11, 2016Date of Patent: July 18, 2017Assignee: International Business Machines CorporationInventors: Kevin K. Chan, Young-Hee Kim, Masaharu Kobayashi, Jinghong Li, Dae-Gyu Park
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Patent number: 9711591Abstract: Methods of forming hetero-layers with reduced surface roughness and bulk defect density on non-native surfaces and the devices formed thereby are described. In one embodiment, the method includes providing a substrate having a top surface with a lattice constant and depositing a first layer on the top surface of the substrate. The first layer has a top surface with a lattice constant that is different from the first lattice constant of the top surface of the substrate. The first layer is annealed and polished to form a polished surface. A second layer is then deposited above the polished surface.Type: GrantFiled: December 28, 2011Date of Patent: July 18, 2017Assignee: Intel CorporationInventors: Niloy Mukherjee, Matthew V. Metz, James M. Powers, Van H. Le, Benjamin Chu-Kung, Mark R. Lemay, Marko Radosavljevic, Niti Goel, Loren Chow, Peter G. Tolchinsky, Jack T. Kavalieros, Robert S. Chau
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Patent number: 9711683Abstract: The present application discloses a semiconductor device comprising a crystalline substrate having a first region and a second region, a nuclei structure on the first region, a first crystalline buffer layer on the nuclei structure, a void between the second region and the first crystalline buffer layer, a second crystalline buffer layer on the first crystalline buffer layer, an intermediate layer located between the first crystalline buffer layer and the second crystalline buffer layer, and a semiconductor device layer on the second crystalline buffer layer.Type: GrantFiled: September 26, 2014Date of Patent: July 18, 2017Assignee: EPISTAR CORPORATIONInventors: Heng-Kuang Lin, Ya-Yu Yang
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Patent number: 9711506Abstract: A method of fabricating a semiconductor device includes preparing a substrate including a first region and a second region, sequentially forming a first semiconductor layer and a second semiconductor layer on the first and second regions, patterning the first and second semiconductor layers to form a lower semiconductor pattern and an upper semiconductor pattern on each of the first and second regions, selectively removing the lower semiconductor pattern on the second region to form a gap region, and forming gate electrodes at the first and second regions, respectively.Type: GrantFiled: August 29, 2016Date of Patent: July 18, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Junggil Yang, Sangsu Kim, TaeYong Kwon, Sung Gi Hur
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Patent number: 9704881Abstract: A method of manufacturing a semiconductor device is provided including providing a semiconductor substrate with a semiconductor layer, forming a first gate electrode over the semiconductor layer, forming a second gate electrode over the semiconductor layer, forming a mask layer between the first and second gate electrodes, etching a cavity into the semiconductor layer between the first and second gate electrodes using the mask layer as an etching mask, and forming a semiconductor material in the etched cavities.Type: GrantFiled: September 21, 2015Date of Patent: July 11, 2017Assignee: GLOBALFOUNDRIES Inc.Inventor: Naseer Babu Pazhedan
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Patent number: 9704977Abstract: Energy-filtered cold electron devices use electron energy filtering through discrete energy levels of quantum wells or quantum dots that are formed through band bending of tunneling barrier conduction band. These devices can obtain low effective electron temperatures of less than or equal to 45K at room temperature, steep electrical current turn-on/turn-off capabilities with a steepness of less than or equal to 10 mV/decade at room temperature, subthreshold swings of less than or equal to 10 mV/decade at room temperature, and/or supply voltages of less than or equal to 0.1 V.Type: GrantFiled: February 3, 2015Date of Patent: July 11, 2017Assignee: BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEMInventors: Seong Jin Koh, Pradeep Bhadrachalam, Liang-Chieh Ma
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Patent number: 9698266Abstract: A method for forming a semiconductor device comprises forming a first buffer layer with a first melting point on a substrate. A second buffer layer is formed on the first buffer layer. The second buffer layer has a second melting point that is greater than the first melting point. Annealing process is performed that increases a temperature of the first buffer layer such that the first buffer layer partially liquefies and causes a strain in the second buffer layer to be substantially reduced.Type: GrantFiled: March 9, 2016Date of Patent: July 4, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
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Patent number: 9691848Abstract: Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped Ge etch suppression layer (e.g., p-type SiGe) disposed there between to suppress etch of the Ge-rich device layer during removal of a sacrificial semiconductor layer richer in Si than the device layer. Rates of dissolution of Ge in wet etchants, such as aqueous hydroxide chemistries, may be dramatically decreased with the introduction of a buried p-type doped semiconductor layer into a semiconductor film stack, improving selectivity of etchant to the Ge-rich device layers.Type: GrantFiled: October 25, 2016Date of Patent: June 27, 2017Assignee: Intel CorporationInventors: Willy Rachmady, Van H. Le, Ravi Pillarisetty, Jessica S. Kachian, Marc C. French, Aaron A. Budrevich
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Patent number: 9685589Abstract: An optoelectronic component includes a layer structure which has a first gallium nitride layer and an aluminum-containing nitride intermediate layer. In this case, the aluminum-containing nitride intermediate layer adjoins the first gallium nitride layer. The layer structure has an undoped second gallium nitride layer which adjoins the aluminum-containing nitride intermediate layer.Type: GrantFiled: September 25, 2013Date of Patent: June 20, 2017Assignee: OSRAM Opto Semiconductors GmbHInventors: Werner Bergbauer, Philipp Drechsel, Peter Stauss, Patrick Rode
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Patent number: 9679899Abstract: Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include compressive-strained SiGe on a silicon substrate, while the nFETs include tensile-strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type and p-type FinFETs are separated by electrically insulating regions formed by a damascene process. During formation of the insulating regions, the SiGe substrate supporting the n-type devices is permitted to relax elastically, thereby limiting defect formation in the crystal lattice of the SiGe substrate.Type: GrantFiled: August 24, 2015Date of Patent: June 13, 2017Assignee: STMicroelectronics, Inc.Inventors: Nicolas Loubet, Pierre Morin, Yann Mignot
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Patent number: 9673377Abstract: A compound semiconductor device includes: a flexible part; a first nitride semiconductor layer above a surface of the flexible part, the first nitride semiconductor layer including a first polar plane and a second polar plane intersecting the surface; a second nitride semiconductor layer in contact with the first nitride semiconductor layer on the first polar plane, a lattice constant of the second nitride semiconductor layer being different from that of the first nitride semiconductor layer; a third nitride semiconductor layer in contact with the first nitride semiconductor layer on the second polar plane, a lattice constant of the third nitride semiconductor layer being different from that of the first nitride semiconductor layer; a first ohmic electrode above an interface between the first nitride semiconductor layer and the second nitride semiconductor layer; and a second ohmic electrode above an interface between the first nitride semiconductor layer and the third nitride semiconductor layer.Type: GrantFiled: February 1, 2016Date of Patent: June 6, 2017Assignee: FUJITSU LIMITEDInventor: Naoya Okamoto
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Patent number: 9660140Abstract: An ultraviolet LED having increased light extraction efficiency includes: a single crystal sapphire substrate on which an array of protruding portions are formed; an AlN crystal buffer layer formed on the sapphire substrate; and an ultraviolet light emitting layer, in contact with the buffer layer, formed into a layered stack including an n-type conductive layer, a recombination layer, and a p-type conductive layer, in order from the buffer layer. The buffer layer includes a pillar array section and an integration section wherein pillars in the array are connected with one another. Each pillar extends from a protruding portion of the sapphire substrate, in a direction normal to one surface thereof. The pillars are separated from one another in the plane of the surface by a gap G. Light emitted from the ultraviolet light emitting layer is extracted to the outside through the pillar array section and the sapphire substrate.Type: GrantFiled: October 15, 2013Date of Patent: May 23, 2017Assignee: RIKENInventor: Hideki Hirayama
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Patent number: 9653603Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a recess in the substrate; forming a buffer layer in the recess; forming an epitaxial layer on the buffer layer; and removing part of the epitaxial layer, part of the buffer layer, and part of the substrate to form fin-shaped structures.Type: GrantFiled: April 26, 2016Date of Patent: May 16, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Li-Wei Feng, Shih-Hung Tsai, Yi-Fan Li, Kun-Hsin Chen, Tong-Jyun Huang, Jyh-Shyang Jenq, Nan-Yuan Huang
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Patent number: 9647067Abstract: Present embodiments provide for a FinFET and fabrication method thereof. The fabrication method includes two selective etching processes to form the channel. The FinFET includes a substrate, a shallow trench isolation (STI) layer, a buffer layer, an III-V group material, a high-K dielectric layer and a conductor material. The STI is formed on the substrate with a trench. The buffer layer is formed on the substrate in the trench. The III-V group material is formed on the buffer layer in vertical stacked bowl shape. The high-K dielectric layer is formed on the STI layer and surrounding the III-V group material. The conductor material is formed surrounding the high-K dielectric layer as a gate electrode.Type: GrantFiled: September 20, 2016Date of Patent: May 9, 2017Assignee: ZING SEMICONDUCTOR CORPORATIONInventor: Deyuan Xiao
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Patent number: 9640632Abstract: A semiconductor device having improved heat dissipation is disclosed. The semiconductor device includes a semi-insulating substrate and epitaxial layers disposed on the semi-insulating substrate wherein the epitaxial layers include a plurality of heat conductive vias that are disposed through the epitaxial layers with the plurality of heat conductive vias being spaced along a plurality of finger axes that are aligned generally parallel across a surface of the epitaxial layers. The semiconductor device further includes an electrode having a plurality of electrically conductive fingers that are disposed along the plurality of finger axes such that the electrically conductive fingers are in contact with the first plurality of heat conductive vias.Type: GrantFiled: July 13, 2015Date of Patent: May 2, 2017Assignee: Qorvo US, Inc.Inventor: Andrew P. Ritenour
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Patent number: 9634007Abstract: Trench-confined selective epitaxial growth process in which epitaxial growth of a semiconductor device layer proceeds within the confines of a trench. In embodiments, a trench is fabricated to include a pristine, planar semiconductor seeding surface disposed at the bottom of the trench. Semiconductor regions around the seeding surface may be recessed relative to the seeding surface with Isolation dielectric disposed there on to surround the semiconductor seeding layer and form the trench. In embodiments to form the trench, a sacrificial hardmask fin may be covered in dielectric which is then planarized to expose the hardmask fin, which is then removed to expose the seeding surface. A semiconductor device layer is formed from the seeding surface through selective heteroepitaxy. In embodiments, non-planar devices are formed from the semiconductor device layer by recessing a top surface of the isolation dielectric.Type: GrantFiled: June 11, 2014Date of Patent: April 25, 2017Assignee: Intel CorporationInventors: Ravi Pillarisetty, Seung Hoon Sung, Niti Goel, Jack T. Kavalieros, Sansaptak Dasgupta, Van H. Le, Willy Rachmady, Marko Radosavljevic, Gilbert Dewey, Han Wui Then, Niloy Mukherjee, Matthew V. Metz, Robert S. Chau
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Patent number: 9634123Abstract: A method includes forming a fin on a semiconductor substrate. An isolation structure is formed adjacent the fin. A silicon alloy material is formed on a portion of the fin extending above the isolation structure. A thermal process is performed to define a silicon alloy fin portion from the silicon alloy material and the fin and to define a first insulating layer separating the fin from the substrate.Type: GrantFiled: April 2, 2015Date of Patent: April 25, 2017Assignee: GLOBALFOUNDRIES Inc.Inventor: Ajey Poovannummoottil Jacob
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Patent number: 9634172Abstract: The disclosure describes multi-junction solar cell structures that include two or more graded interlayers.Type: GrantFiled: September 12, 2014Date of Patent: April 25, 2017Assignee: SolAero Technologies Corp.Inventors: Yong Lin, Paul Sharps, Arthur Cornfeld, Pravin Patel, Mark A. Stan, Benjamin Cho
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Patent number: 9634119Abstract: A method includes providing a gate structure over a semiconductor substrate and forming a source/drain region associated with the gate structure by etching an opening in the semiconductor substrate, performing a first epitaxial growth process while an entirety of a sidewall of the opening is exposed to grow a first epitaxy material in the opening. The first epitaxial growth process is free of a first dopant impurity. A second epitaxial growth process is performed after first epitaxial growth process to grow a second epitaxy material on the first epitaxy material. The second epitaxy material has the first dopant impurity at a first concentration. Further, a third epitaxial growth process is performed after the second epitaxial growth process that includes introducing the first dopant impurity at a second concentration, the second concentration greater than the first concentration.Type: GrantFiled: June 19, 2015Date of Patent: April 25, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen Chu Hsiao, Ju Wen Hsiao, Ying Min Chou, Hsiang Hsiang Ko, Ying-Lang Wang
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Patent number: 9634093Abstract: A method for fabricating a semiconductor device includes forming a first mask on a substrate, forming a first side wall of a fin by performing a first etching of the substrate using the first mask, forming a second mask on the substrate, the second mask being different from the first mask, and forming a second side wall of the fin by performing a second etching of the substrate using the second mask.Type: GrantFiled: May 11, 2016Date of Patent: April 25, 2017Assignees: SAMSUNG ELECTRONICS CO., LTD., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATIONInventors: Min-Chul Sun, Byung-Gook Park
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Patent number: 9627534Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate, an ILD layer on the semiconductor substrate, a gate in the ILD layer, an offset liner on a sidewall of the gate, a spacer on the offset liner, a dense oxide film on the spacer, a contact etch stop layer on the dense oxide film, and a contact plug adjacent to the contact etch stop layer. The semiconductor device further includes a source region in the semiconductor substrate and a drain region spaced apart from the source region. A channel is located between the source region and the drain region.Type: GrantFiled: November 20, 2015Date of Patent: April 18, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kuang-Hsiu Chen, Yi-Liang Ye, Chueh-Yang Liu, Yu-Ren Wang
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Patent number: 9627482Abstract: A method for fabricating a semiconductor device may include receiving a gated substrate comprising a substrate with a channel layer and a gate structure formed thereon, over-etching the channel layer to expose an extension region below the gate structure, epitaxially growing a halo layer on the exposed extension region using a first in-situ dopant and epitaxially growing a source or drain on the halo layer using a second in-situ dopant, wherein the first in-situ dopant and the second in-situ dopant are of opposite doping polarity. Using an opposite doping polarity may provide an energy band barrier for the semiconductor device and reduce leakage current. A corresponding apparatus is also disclosed herein.Type: GrantFiled: April 7, 2016Date of Patent: April 18, 2017Assignee: International Business Machines CorporationInventors: Cheng-Wei Cheng, Pranita Kerber, Young-Hee Kim, Effendi Leobandung, Yanning Sun
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Patent number: 9627276Abstract: A method includes forming one or more fin structures on a substrate, the one or more fin structures comprising a first material comprising a first lattice structure and the substrate comprising a second material comprising a second lattice structure. Forming the one or more fin structures on the substrate includes forming one or more trenches in the substrate, and growing the first material in the one or more trenches. The first lattice structure is different from the second lattice structure. The one or more fin structures are self-aligned by the one or more trenches.Type: GrantFiled: December 28, 2015Date of Patent: April 18, 2017Assignee: International Business Machines CorporationInventor: Effendi Leobandung
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Patent number: 9627489Abstract: A semiconductor device includes a first semiconductor layer on a substrate, a second semiconductor layer containing an n-type dopant, on the first semiconductor layer, a third semiconductor layer having a resistance greater than a resistance of the second semiconductor layer, on the second semiconductor layer, a fourth semiconductor layer containing a nitride semiconductor, on the third semiconductor layer, and a fifth semiconductor layer containing a nitride semiconductor having a band gap greater than a band gap of the fourth semiconductor layer, on the fourth semiconductor layer.Type: GrantFiled: August 20, 2015Date of Patent: April 18, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Hung Hung, Yasuhiro Isobe, Kohei Oasa, Akira Yoshioka
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Patent number: 9601623Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.Type: GrantFiled: May 8, 2015Date of Patent: March 21, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Anthony J. Lochtefeld, Thomas A. Langdo, Richard Hammond, Matthew T. Currie, Eugene A. Fitzgerald
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Patent number: 9595585Abstract: A method of manufacturing a semiconductor device includes forming a PMOS region and an NMOS region in a semiconductor substrate, forming dummy gate structures in the PMOS and NMOS regions, and forming a gate hard mask layer overlying top portions and sidewalls of the dummy gate structures. The method includes forming silicon carbon regions embedded in the semiconductor substrate on both sides of the dummy gate structure in the NMOS region, removing the hard mask layer on top of the dummy gate in the NMOS region, and forming silicon germanium regions embedded in the semiconductor substrate on both sides of the dummy gate structure in the PMOS region. After forming the silicon carbon regions and the silicon germanium regions, while retaining the hard mask layer on top of the dummy gates in the PMOS region, performing ion implant to form source/drain regions in the NMOS region and the PMOS region.Type: GrantFiled: September 19, 2014Date of Patent: March 14, 2017Assignees: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) CorporationInventor: Gang Mao
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Patent number: 9590087Abstract: A transistor includes a source, a drain spaced apart from the source, and a heterostructure body having a two-dimensional charge carrier gas channel for connecting the source and the drain. The transistor further includes a semiconductor field plate disposed between the source and the drain. The semiconductor field plate is configured to at least partly counterbalance charges in the drain when the transistor is in an off state in which the channel is interrupted and a blocking voltage is applied to the drain. The counterbalance charge provided by the semiconductor field plate is evenly distributed over a plane or volume of the semiconductor field plate. Various semiconductor field plate configurations and corresponding manufacturing methods are described herein.Type: GrantFiled: November 13, 2014Date of Patent: March 7, 2017Assignee: Infineon Technologies Austria AGInventors: Wolfgang Werner, Frank Kahlmann, Franz Hirler
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Patent number: 9590041Abstract: A semiconductor structure includes a semiconductor substrate, a dielectric structure formed on the semiconductor substrate and including at least a recess formed therein, a fin formed in the recess, and a dislocation region formed in the fin. The semiconductor substrate includes a first semiconductor material. The fin includes the first semiconductor material and a second semiconductor material. A lattice constant of the second semiconductor material is different from a lattice constant of the first semiconductor material. A topmost portion of the dislocation region is higher than an opening of the recess.Type: GrantFiled: December 6, 2015Date of Patent: March 7, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yu-Ru Yang, Huai-Tzu Chiang, Sheng-Hao Lin, Shih-Hsien Huang, Chien-Hung Chen, Chun-Yuan Wu, Cheng-Tzung Tsai
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Patent number: 9590107Abstract: Embodiments of the invention provide methods for forming III-V gate-all-around field effect transistors on silicon substrates that utilize Aspect-Ratio Trapping to reduce or eliminate dislocation defects associated with lattice mismatches. A field dielectric material defining a trench is formed on a crystalline silicon substrate. A channel feature comprising III-V material is subsequently formed inside the trench. Source/drain features are then formed at both ends of the channel feature inside the trench. Lastly, gate dielectric layers and a gate feature are formed surrounding a portion of the channel feature.Type: GrantFiled: June 25, 2015Date of Patent: March 7, 2017Assignee: International Business Machines CorporationInventors: Guy M. Cohen, Sanghoon Lee
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Patent number: 9590090Abstract: A method of forming a channel of a gate structure is provided. A first epitaxial channel layer is formed within a first trench of the gate structure. A dry etching process is performed on the first epitaxial channel layer to form a second trench. A second epitaxial channel layer is formed within the second trench.Type: GrantFiled: January 8, 2014Date of Patent: March 7, 2017Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Ching-Feng Fu, De-Fang Chen, Chun-Hung Lee, Huan-Just Lin, Hui-Cheng Chang
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Patent number: 9583627Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least a fin-shaped structure thereon and the fin-shaped structure includes a top portion and a bottom portion; forming a gate structure on the fin-shaped structure; forming a cap layer on the top portion of the fin-shaped structure not covered by the gate structure; performing an annealing process to drive germanium from the cap layer to the top portion of the fin-shaped structure; removing the cap layer; and forming an epitaxial layer around the top portion of the fin-shaped structure.Type: GrantFiled: July 7, 2015Date of Patent: February 28, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yu-Cheng Tung, En-Chiuan Liou
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Patent number: 9583599Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a fin using double trench epitaxy. The fin may be composed of a III-V semiconductor material and may be grown on a silicon, silicon germanium, or germanium substrate. A double trench aspect ratio trapping (ART) epitaxy method may trap crystalline defects within a lower trench (i.e. a defective region) and may permit formation of a fin free of patterning defects in an upper trench (i.e. a fin mold). Crystalline defects within the defective region may be trapped via conventional aspect ratio trapping or three-sided aspect ratio trapping. Fin patterning defects may be avoided by utilizing a fin mold to grow an epitaxial fin and selectively removing dielectric material adjacent to a fin region.Type: GrantFiled: April 22, 2015Date of Patent: February 28, 2017Assignee: International Business Machines CorporationInventors: Veeraraghavan S. Basker, Pouya Hashemi, Shogo Mochizuki, Alexander Reznicek
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Patent number: 9577093Abstract: According to an exemplary embodiment, a method of forming a semiconductor device is provided. The method includes: providing a vertical structure over a substrate; forming an etch stop layer over the vertical structure; forming an oxide layer over the etch stop layer; performing chemical mechanical polishing on the oxide layer and stopping on the etch stop layer; etching back the oxide layer and the etch stop layer to expose a sidewall of the vertical structure and to form an isolation layer; oxidizing the sidewall of the vertical structure and doping oxygen into the isolation layer by using a cluster oxygen doping treatment.Type: GrantFiled: October 7, 2015Date of Patent: February 21, 2017Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Cheng-Tung Lin, Teng-Chun Tsai, Li-Ting Wang, De-Fang Chen, Bing-Hung Chen, Huang-Yi Huang, Hui-Cheng Chang, Huan-Just Lin, Ming-Hsing Tsai
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Patent number: 9576794Abstract: In some aspects, methods for forming a germanium thin film using a cyclical deposition process are provided. In some embodiments, the germanium thin film is formed on a substrate in a reaction chamber, and the process includes one or more deposition cycles of alternately and sequentially contacting the substrate with a vapor phase germanium precursor and a nitrogen reactant. In some embodiments, the process is repeated until a germanium thin film of desired thickness has been formed.Type: GrantFiled: December 15, 2015Date of Patent: February 21, 2017Assignee: ASM IP HOLDING B.V.Inventor: Raija H. Matero
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Patent number: 9570403Abstract: A first trench having a first aspect ratio and a second trench having a second aspect ratio that is greater than the first trench are provided into a material stack of a semiconductor substrate and a dielectric material. An epitaxial semiconductor material having a different lattice constant than the substrate is then grown within each of the first and second trenches. The semiconductor material which is epitaxially formed in the first trench has an upper semiconductor material portion that is entirely defect free, while the semiconductor material which is epitaxially formed in the second trench has defects that randomly propagate to the topmost surface of the semiconductor material. At least one semiconductor device is then formed on each epitaxially grown semiconductor material. The at least one semiconductor device located on the epitaxially grown semiconductor material formed in the second trench is a physical unclonable function device.Type: GrantFiled: June 10, 2016Date of Patent: February 14, 2017Assignee: International Business Machines CorporationInventors: Qing Cao, Kangguo Cheng, Fei Liu
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Patent number: 9564491Abstract: According to one embodiment, a semiconductor device includes an n-type semiconductor layer, a first electrode, and a nitride semiconductor layer. The n-type semiconductor layer includes diamond. The nitride semiconductor layer is provided between the n-type semiconductor layer and the first electrode. The nitride semiconductor layer includes AlxGa1?xN (0?x?1) and is of n-type.Type: GrantFiled: December 9, 2015Date of Patent: February 7, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Mariko Suzuki, Tadashi Sakai
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Patent number: 9559102Abstract: A semiconductor device includes first and second active regions. Each active region includes a plurality of fin protrusions and a recessed area disposed between the fin protrusions. A plurality of gate structures are disposed on each of the plurality of fin protrusions. A semiconductor layer is disposed in each recessed area. A distance between the gate structures of the first active region is the same as a distance between the gate structures of the second active region, and a height difference between a bottom surface of the semiconductor layer of the first recessed area and a top surface of each of the fin protrusions of the first active region is smaller than a height difference between a bottom surface of the semiconductor layer of the recessed area of the second active region and a top surface of each of the fin protrusions of the second active region.Type: GrantFiled: December 21, 2015Date of Patent: January 31, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yoonhae Kim, Myungil Kang, Sooyeon Jeong
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Patent number: 9559099Abstract: A FinFET device comprises an isolation region in a substrate, wherein the isolation region comprises a plurality of non-vertical sidewalls, a first V-shaped groove, a second V-shaped groove and a third V-shaped groove formed in the substrate, a first cloak-shaped active region over the first V-shaped groove, wherein a top surface of the first cloak-shaped active region comprises a first slope, a second cloak-shaped active region over the second V-shaped groove, wherein a top surface of the second cloak-shaped active region is triangular in shape and a third cloak-shaped active region over the third V-shaped groove, wherein a top surface of the third cloak-shaped active region comprises a second slope.Type: GrantFiled: June 3, 2014Date of Patent: January 31, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Jing Lee, You-Ru Lin, Cheng-Tien Wan, Cheng-Hsien Wu, Chih-Hsin Ko
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Patent number: 9548431Abstract: In various embodiments, an illumination device features an ultraviolet (UV) light-emitting device at least partially surrounded by an encapsulant and having a rigid lens. Downward forces is applied while the encapsulant is at least partially cured to substantially prevent partial or full detachment of the rigid lens from the light-emitting device, and/or substantially suppress formation of bubbles between the light-emitting device and the rigid lens.Type: GrantFiled: February 16, 2016Date of Patent: January 17, 2017Assignee: CRYSTAL IS, INC.Inventors: Masato Toita, Jianfeng Chen, Yuxin Li, Yuting Wang, Hironori Ishii, Ken Kitamura
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Patent number: 9544499Abstract: Disclosed is a system apparatus and device for facilitating the backup of network edge devices, such as video cameras, and methods of operation thereof. A monitoring circuit(s) may detect inoperable electrical power condition(s) (IEPC) on the power-line of a network edge device. Upon detection of an IEPC a backup power source may provide electrical power to the edge device. Upon detection of a connectivity fault between the edge device and its packet sink, a packet sink emulator may emulate a packet sink of the edge device. The disclosed system apparatus and device may be implemented as a SoC (System on Chip).Type: GrantFiled: March 22, 2015Date of Patent: January 10, 2017Assignee: ENERGY RE-CONNECT LTD.Inventor: Roni Herzel
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Patent number: 9530655Abstract: A CMP slurry composition which provides for a high Ge- or SiGe-to-dielectric material selectivity a low rate of Ge or SiGe recess formation includes an oxidant and a germanium removal rate enhancer including at least one of a methylpyridine compound and a methylpyridine derivative compound. In some examples, the slurry composition also includes an etching inhibitor. In some cases, the slurry composition may include an abrasive, a surfactant, an organic complexant, a chelating agent, an organic or inorganic acid, an organic or inorganic base, a corrosion inhibitor, or a buffer. The slurry composition may be distributed onto a surface of a polishing pad disposed on a platen that is configured to rotate. Additionally, a workpiece carrier configured to house a substrate may bring the substrate into contact with the rotating polishing pad and thereby polish the substrate utilizing the slurry composition.Type: GrantFiled: September 8, 2014Date of Patent: December 27, 2016Assignees: Taiwan Semiconductor Manufacting Company, Ltd., UWIZ Technology Co., Ltd.Inventors: Chia-Jung Hsu, Yun-Lung Ho, Neng-Kuo Chen, Song-Yuan Chang, Teng-Chun Tsai
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Patent number: 9525031Abstract: Some embodiments of the present disclosure relate to an epitaxially grown replacement channel region within a transistor, which mitigates the variations within the channel of the transistor due to fluctuations in the manufacturing processes. The replacement channel region is formed by recessing source/drain and channel regions of the semiconductor substrate, and epitaxially growing a replacement channel region within the recess, which comprises epitaxially growing a lower epitaxial channel region over a bottom surface of the recess, and epitaxially growing an upper epitaxial channel region over a bottom surface of the recess. The lower epitaxial channel region retards dopant back diffusion from the upper epitaxial channel region, resulting in a steep retrograde dopant profile within the replacement channel region. The upper epitaxial channel region increases carrier mobility within the channel.Type: GrantFiled: March 13, 2014Date of Patent: December 20, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Hsing Yu, Ken-Ichi Goto, Chia-Wen Liu, Yeh Hsu
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Patent number: 9520498Abstract: A device comprises a substrate comprising silicon, a fin structure comprising a lower portion formed of silicon and enclosed by an isolation region, a middle portion formed of silicon-germanium-carbon, wherein the middle portion is enclosed by an oxide layer, an upper portion formed of silicon, wherein the upper portion comprises a channel and a silicon-carbon layer formed between the middle portion and the upper portion, a first source/drain region comprising a first silicon-phosphorus region and a first silicon-carbon layer formed underlying the first silicon-phosphorus region and a second source/drain region comprising a second silicon-phosphorus region and a second silicon-carbon layer formed underlying the second silicon-phosphorus region.Type: GrantFiled: March 17, 2014Date of Patent: December 13, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Cheng Ching, Guan-Lin Chen, Chao Hsiung Wang, Chi-Wen Liu