Abstract: A method for controlling the exposure of an active pixel array electronic still camera includes the steps of: integrating photocurrent in each pixel during an integration time period; collecting overflow charge from all pixels in the array during the integration time period; developing an overflow signal as a function of the overflow charge; and terminating the integration time period when the overflow signal exceeds a preset threshold level selected to represent a desired reference exposure level.

Abstract: In an image pickup apparatus capable of executing image pickup and focus detection using the phase difference scheme by a solid-state image pickup element, accurate and quick focus detection using the phase difference scheme is realized. In addition, an image pickup apparatus capable of obtaining a high-quality image signal even in an image pickup mode is provided. Each pixel unit of an image pickup element includes first and second photoelectric conversion units for photoelectrically converting light components that have passed through different regions in the exit pupil of an image pickup optical system and is arranged such that the first sensitivity distribution by the first photoelectric conversion unit and the second sensitivity distribution by the second photoelectric conversion unit overlap in a region between the photoelectric conversion units.

Abstract: A monolithic photodetector including a photodiode, a precharge MOS transistor, a control MOS transistor, a read MOS transistor, and a transfer MOS transistor, the photodiode and the transfer transistor being formed in a same substrate of a first conductivity type, the photodiode including a first region of the second conductivity type formed under a second region of the first conductivity type more heavily doped than the first region, and above a third region of the first conductivity type more heavily doped than the substrate, the first region being the source of the second conductivity type of the transfer transistor, the second and third regions being connected to the substrate and being at a fixed voltage.

Abstract: A fabrication method for providing isolation between adjacent regions of an integrated circuit includes providing a guard layer over field edges that are the interfaces between field oxide regions and diffusion regions in which dopant is introduced. The guard layer will inhibit introduction of dopant along the field-edge, so that a substantially dopant-free transition strip is formed. The transition strip inhibits current leakage from the active region to the field oxide region. In one embodiment, the active region is an active area diode, such as used to form an Active Pixel Sensor (APS) pixel. The guard layer is biased so as to further inhibit current leakage during circuit operation. In another embodiment, the method is used in the fabrication of transistors for APS pixels having an overlay photodiode structure.

Abstract: A barrier area is located adjacent a horizontal transfer area and spaced from a field insulating area. The barrier area includes an insulating layer and a conductor extending from the horizontal transfer layer over the surface of a semiconductor substrate, a barrier layer of a second conductivity type formed under the surface of the semiconductor substrate and adjacent a first impurity layer of a first conductivity type of the horizontal transfer area, and a second impurity layer extending from the horizontal transfer area and formed under the barrier layer. A discharge area is located between the barrier area and the field insulating area.

Abstract: A CMOS imager having an improved signal to noise ratio and improved dynamic range is disclosed. The CMOS imager provides improved charge storage by fabricating a storage capacitor in parallel with the photocollection area of the imager. The storage capacitor may be a flat plate capacitor formed over the pixel,a stacked capacitor or a trench imager formed in the photosensor. The CMOS imager thus exhibits a better signal-to-noise ratio and improved dynamic range. Also disclosed are processes for forming the CMOS imager.

Abstract: An electric charge detector includes an N-type semiconductor substrate 10 and a P-type well region 9 formed on the semiconductor substrate 10. An N-type well region 2 is formed on the P-type well region 9. A potential-change detection means is connected to the N-type well region 2 to detect a variation in surface potential of the N-type well region 2. The P-type diffused layer 11 is formed on a surface of the N-type well region 2.

Abstract: A solid-state imaging device includes a second conductive type impurity region formed in a first conductive type semiconductor substrate in an area corresponding to a pixel area, a high-resistivity semiconductor layer of the first conductive type formed on the semiconductor substrate including the impurity region, and an ion-implanted region of the first conductive type formed in at least one of the semiconductor substrate and the high-resistivity semiconductor layer in a peripheral area other than the pixel area. A method of fabricating the solid-state imaging device is also disclosed.

Abstract: In a solid-state image pickup device, a transfer register 10 is provided with an overflow control gate OFCG and an overflow drain OFD, and the gate electrode 12A of the overflow control gate OFCG is formed so as to be superposed on the lower-layer electrodes St1, 13 of the transfer register 10 side the overflow drain OFD side.

Abstract: IT-CCD has a number of photoelectric conversion elements disposed in a pixel shift layout in a plurality of rows and columns, a plurality of vertical transfer CCDs for transferring signal charges accumulated in the photoelectric conversion elements toward a horizontal transfer CCD in a zigzag way, and readout gate regions for controlling for corresponding photoelectric conversion elements to read the signal charges accumulated in the photoelectric conversion elements to the vertical transfer CCDs. In manufacturing such IT-CCD, for twos of a plurality of photoelectric conversion element columns, a vertical transfer CCD is provided in an area in plan view between the two photoelectric conversion element columns, and a plurality of charge transfer stages constituting a adjusting portion are formed downstream of the downstream ends of the vertical transfer CCDs.

Abstract: A charge coupled device has an n-type charge accumulating layer equal to or less than 5 micron in width, and the unit cells suffer from reduction of signal charge accumulated therein and an increased pulse height of a pulse signal for a substrate shutter, wherein at least one p-type local impurity region is formed in such a manner as to form a p-n junction together with the n-type charge accumulating layer and the n-type semiconductor substrate, thereby increasing the amount of signal charge accumulated in each unit cell without sacrifice of the pulse height of the pulse signal for the substrate shutter.

Abstract: A storage pixel sensor disposed on a semiconductor substrate comprises a capacitive storage element having a first terminal connected to a fixed potential and a second terminal. A photodiode has an anode connected to a first potential and a cathode. A semiconductor reset switch has a first terminal connected to the cathode and a second terminal connected to a reset potential. A semiconductor transfer switch has a first terminal connected to the cathode and a second terminal connected to the second terminal of the capacitive storage element. A semiconductor amplifier has an input connected to the capacitive storage element and an output. The semiconductor reset switch and the semiconductor transfer switch each have a control element connected to a control circuit for selectively activating the semiconductor reset switch and the semiconductor transfer switch.

Abstract: A back thinned CCD has at least first and second parallel n− signal channel segments and a p++ channel stop region between the signal channels.

Abstract: A charge-coupled device (CCD) image sensor that preserves defect gettering characteristics having a vertical overflow drain (VOD) for blooming protection is provided in a structure that provides low voltage electronic shuttering. This structure reduces the electronic shutter voltage to ease the demands on off-chip support circuitry required to operate the CCD image sensor. The invention provides an improved pixel structure to reduce this voltage. Prior art difficulties are avoided by providing uniform, n-type layers of varying doping levels underneath the entire area of the CCD device. Combined with a lightly doped n-type substrate these layers provide low voltage electronic shutter operation.

Abstract: An improved light responsive semiconductor switch with shorted load protection capable of successfully interrupting a load overcurrent. The switch is includes an output transistor which is triggered by a photovoltaic element to connect a load to a power source thereof, and an overcurrent sensor which provides an overcurrent signal upon seeing an overcurrent condition in the load. A shunt transistor is connected in series with a current limiting resistive element across the photovoltaic element to define a shunt path of flowing the current from the photovoltaic element through the current limiting resistive element away from the output transistor. A latch circuit is included to be energized by the photovoltaic element and to provide an interruption signal once the overcurrent signal is received and hold the interruption signal.

Abstract: Provided is a blooming control structure for an imager and a corresponding fabrication method. The structure is produced in a semiconductor substrate in which is configured an electrical charge collection region. The electrical charge collection region is configured to accumulate electrical charge that is photogenerated in the substrate, up to a characteristic charge collection capacity. A blooming drain region is configured in the substrate laterally spaced from the charge collection region. The blooming drain region includes an extended path of a conductivity type and level that are selected for conducting charge in excess of the characteristic charge collection capacity away from the charge collection region. A blooming barrier region is configured in the substrate to be adjacent to and laterally spacing the charge collection and blooming drain regions by a blooming barrier width. This barrier width corresponds to an acute blooming barrier impurity implantation angle with the substrate.

Abstract: To improve such a fact that a signal electric charge from a sensor unit in an MOS imaging device can not be completely read out by a low read-out voltage. To this end, in an arrangement in which a plurality of unit pixels each of which has a sensor unit (S) with a photoelectric conversion region (20) as well as an insulating gate transistor MOS for reading out a signal electric charge from the sensor unit (S) are disposed, a photoelectric conversion region of the sensor unit (S) is so constructed as to form a single potential dip for the signal electric charge and a gate electrode (18) of the insulating gate transistor (MOS) is formed into a pattern in which the middle portion in a channel width direction thereof is positioned above the central portion of the potential dip or its vicinity.

Abstract: A lateral PNP transistor (LPNP) (102) having the low resistance base buried N+ region (114) removed from below the emitter region (118). This leaves a high resistance n-well (116) below the emitter. The resistance from the center of the emitter region (118) to the N+ buried region (114) is greater than the resistance at the periphery of the emitter region (118) to the N+ buried region (114). Debiasing will occur in the center of the emitter region (118) where the parasitic base current is generated. Thus, the ratio of parasitic current to active collector current and peak beta will improve.

Abstract: The image sensing device includes an image sensing area 22 having an antiblooming drain structure; and a frame memory area 24 coupled to the image sensing area 22 for storing charge from the image sensing area, wherein during charge integration, the antiblooming drain is biased at a first level, and during charge transfer to memory, the antiblooming drain is biased at a second level such that the image sensing area 22 will have a higher charge capacity than during the charge integration.

Abstract: A photosensitive device includes an array of active pixel sensor devices, each APS device being formed in an isolated cell of silicon. Each cell has an insulating barrier around it, and sits upon an insulating layer formed on an underlying substrate. A semiconductor connector making vertical contact between the pinning layer and the body of each APS device preferably replaces at least some portion of the insulating barrier adjacent to each cell. The semiconductor connector may be a single vertical connection for each cell or it may be an elongated strip connecting multiple APS devices. It may extend only to the underlying insulating layer or it may extend through the insulating layer to the substrate, with the substrate acting to interconnect and ground the pinning layer and the body of each APS device. The invention also includes the method of making the photosensitive device.

Abstract: A pixel circuit construction for image sensing includes a photosensor, an amplifier, a selector switch and, and a reset switch. The amplifier may be a single polycrystalline silicon (channel) transistor for high gain. The selector switch may also be a single polycrystalline silicon (channel) transistor for high conductivity. The reset switch may a single amorphous crystalline silicon (channel) transistor for low leakage current. The photosensor and amplifier may be connected to a shared bias line or may be connected to separate bias and drive lines, respectively. The selector and reset switches may be connected to a shared data line or may be connected to separate data and reset lines, respectively. Laser crystallization and rehydrogenation techniques are well suited to obtaining devices described herein. Gate line and drive voltage line synchronization is provided.

Abstract: P-type ion implantation is done in N well 15, so as to form a charge drain control layer 17 and form a photodiode N well 16 and OFD drain 5, the result being that, even if there is variation in the potential of the photodiode N well 16 making up the photodiode, because the variation in the potential of the charge drain control layer 17 is in the same direction as the potential of the photodiode N well 16, so that variation does not occur in the maximum amount of electrical charge that can be accumulated, the result being that there is no variation in the signal in the saturation condition.

Abstract: A CMOS imager having an improved signal to noise ratio and improved dynamic range is disclosed. The CMOS imager provides improved charge storage by fabricating a storage capacitor in parallel with the photocollection area of the imager. The storage capacitor may be a flat plate capacitor formed over the pixel, a stacked capacitor or a trench imager formed in the photosensor. The CMOS imager thus exhibits a better signal-to-noise ratio and improved dynamic range. Also disclosed are processes for forming the CMOS imager.

Abstract: In a CCD type solid state image pickup device including a semiconductor substrate having photo/electro conversion portions and a first insulating layer formed on the semiconductor substrate, a plurality of charge transfer electrodes are formed on the first insulating layer and are a double structure formed by a first conductive layer and a second conductive layer having a lower resistance value than the first conductive layer. A second insulating layer is interposed between two adjacent ones of the charge transfer electrodes.

Abstract: A photoelectric conversion device comprises a semiconductor substrate, a same-dopant-type semiconductor layer, a photodiode having a charge-accumulation region, a JFET (which has a gate region, a source region, a channel region, and a drain region, the drain region electrically connected to the substrate 100), a transfer gate for transferring a charge from the photodiode to the gate region, and a reset drain having a charge-drain region for draining excess charges generated by the photodiode, the reset drain also controlling the electric potential of the gate region. Two overflow-control regions are included, one at the boundary between the charge-accumulation region and the charge-drain region within the device, one at the boundary between the charge-accumulation region and the charge-drain region of an adjacent device.

Abstract: A charge coupled device includes a substrate, a photoelectric conversion region, a hole accumulation region, a vertical charge coupled region, and a buried transmission gate region. The substrate includes a surface with a light receiving region and a charge transmission region. The photoelectric conversion region is provided in a substrate beneath the light receiving and charge transmission regions, and the photoelectric conversion region generates a photoelectric signal responsive to light received at the light receiving region of the substrate surface. The hole accumulation region is provided in the substrate between the photoelectric conversion region and the light receiving region of the substrate surface. The vertical charge coupled region is provided in the substrate between the photoelectric conversion region and the charge transmission region of the substrate surface. The buried transmission gate region is provided between the vertical charge coupled region and the photoelectric conversion region.

Abstract: Circuitry provides an electronic shutter capability to photo-receiving circuitry for the purpose of disabling integration of a photo-generating charge on an integration capacitor until a reading device reads the integrated signal from the integrating capacitor. With an input from a shutter control line of a high logic voltage, the shutter discontinues charging of the integrating capacitor until the integration capacitor is selectively connected to a read line. Upon receipt of a low logic voltage signal from the shutter control line, the shutter allows the integration capacitor to integrate a photo-receiving charge. The electronic shutter therefore provides well controlled integration time via shutter control. Another advantage is that the integration time is completely independent of the cell reading rate.

Abstract: Methods of operation of an active pixel sensor cell to provide electronic shuttering and elimination of image lag are disclosed. An active pixel sensor has a photodiode, a bipolar transistor, a pass MOS transistor, and a parasitic MOS transistor. The first method of operation of the active pixel sensor will vary the time the integration time of the active pixel sensor by adjusting the time of a resetting pulse to the anode of the photodiode to eliminate any accumulated charge relative to the integration time. The second method will place the anode of the photodiode in a sleep mode by resetting the anode of the photodiode for a period of time. The relative time of the sleep mode to the integration time will determine the electronic shuttering. The third method to eliminate the image-lag overlaps the read period and the sleep time, and brings the reset biasing voltage source to a lower level to extract all the minority carriers from the base of the bipolar transistor.

Abstract: A pixel circuit construction for image sensing includes a photosensor, an amplifier, a selector switch and, and a reset switch. The amplifier may be a single polycrystalline silicon (channel) transistor for high gain. The selector switch may also be a single polycrystalline silicon (channel) transistor for high conductivity. The reset switch may a single amorphous crystalline silicon (channel) transistor for low leakage current. The photosensor and amplifier may be connected to a shared bias line or may be connected to separate bias and drive lines, respectively. The selector and reset switches may be connected to a shared data line or may be connected to separate data and reset lines, respectively. Laser crystallization and rehydrogenation techniques are well suited to obtaining devices described herein. Threshold response is provided.

Abstract: A self aligned, lateral-overflow drain antiblooming structure that is insensitive to drain bias voltages and therefore has improved insensitivity to process variations. The length of the antiblooming barrier regions are easily adjusted and determined by photolithography. The self aligned, lateral-overflow drain (LOD) antiblooming structure results in a design that saves space, and hence, improves overall sensor performance. In this structure, an antiblooming potential barrier is provided that is smaller (in volts) than the barriers that separate the pixels from one another so that excess charge will flow preferentially into the LOD as opposed to the adjacent pixels.

Abstract: A solid-state imaging device provided here comprises a p-type semiconductor substrate, a p-type impurity layer formed thereon, a light-intercepting part formed inside said impurity layer for storing signal charges produced through incident light, and a n-type drain part formed in a region of the substrate excluding the light-intercepting part for discharging excess charges of the light-intercepting part. As a result, sensitivity characteristics on the long wavelength side can be improved, and miniaturization can be facilitated. An n-type buried drain part for discharging charges is formed under a transfer part via a p-type impurity layer. The readout side between the light-intercepting part and the transfer part is separated by a p-type readout control part which is installed to control threshold voltage (Vt), and the non-readout side is separated by a channel stopper.

Abstract: A pixel circuit construction for image sensing includes a photosensor, an amplifier, a selector switch and, and a reset switch. The amplifier may be a single polycrystalline silicon (channel) transistor for high gain. The selector switch may also be a single polycrystalline silicon (channel) transistor for high conductivity. The reset switch may a single amorphous crystalline silicon (channel) transistor for low leakage current. The photosensor and amplifier may be connected to a shared bias line or may be connected to separate bias and drive lines, respectively. The selector and reset switches may be connected to a shared data line or may be connected to separate data and reset lines, respectively. Laser crystallization and rehydrogenation techniques are well suited to obtaining devices described herein. Linearization of output response is provided.

Abstract: A solid state imaging device of the present invention includes a photoelectric convert part, a vertical charge transfer part, a horizontal charge transfer part, an unnecessary charge expelling region. A channel region of the horizontal charge transfer part and the unnecessary charge expelling region have an identical impurity profile. The channel region of the horizontal charge transfer part is applied to a first voltage to be depleted and the unnecessary charge expelling region is applied to a second voltage to be in non-depleted state.

Abstract: An active pixel sensor architecture comprising a semiconductor substrate having a plurality of pixels formed, thereon, incorporating microlens and lightshields into the pixel architecture. Each of the pixels further comprising: a photodetector region upon which incident light will form photoelectrons to be collected as a signal charge; a device for transferring the signal charge from the photodetector region to a charge storage region that is covered by a light shield; a sense node that is an input to an amplifier; the sense node being operatively connected to the signal storage region. The pixel architecture facilitates symmetrical design of pixels which allows for incorporation of light shield and microlens technology into the design.

Abstract: A monolithic three dimensional charged coupled device (3D-CCD) which utilizes the entire bulk of the semiconductor for charge generation, storage, and transfer. The 3D-CCD provides a vast improvement of current CCD architectures that use only the surface of the semiconductor substrate. The 3D-CCD is capable of developing a strong E-field throughout the depth of the semiconductor by using deep (buried) parallel (bulk) electrodes in the substrate material. Using backside illumination, the 3D-CCD architecture enables a single device to image photon energies from the visible, to the ultra-violet and soft x-ray, and out to higher energy x-rays of 30 keV and beyond. The buried or bulk electrodes are electrically connected to the surface electrodes, and an E-field parallel to the surface is established with the pixel in which the bulk electrodes are located. This E-field attracts charge to the bulk electrodes independent of depth and confines it within the pixel in which it is generated.

Abstract: A charge coupled device includes a substrate, a photoelectric conversion region, a hole accumulation region, a vertical charge coupled region, and a buried transmission gate region. The substrate includes a surface with a light receiving region and a charge transmission region. The photoelectric conversion region is provided in a substrate beneath the light receiving and charge transmission regions, and the photoelectric conversion region generates a photoelectric signal responsive to light received at the light receiving region of the substrate surface. The hole accumulation region is provided in the substrate between the photoelectric conversion region and the light receiving region of the substrate surface. The vertical charge coupled region is provided in the substrate between the photoelectric conversion region and the charge transmission region of the substrate surface. The buried transmission gate region is provided between the vertical charge coupled region and the photoelectric conversion region.

Abstract: It is an object of the present invention to provide a solid-state image sensing device with a vertical shutter structure allowing the size of the solid-state image sensing device with ease. An electric-charge exhausting unit is provided on the same side of a sensor array comprising a plurality of sensor units arranged to form a straight line as an electric-charge transferring unit wherein the electric-charge exhausting unit comprising an electric-charge exhaust drain having a shape resembling an island and an electric-charge exhausting gate with a bent shape surrounding the electric-charge exhaust drain is provided in such a way that the electric-charge exhausting unit is in contact with a first region of a read gate, and only one electric-charge exhausting unit is provided for each pair of sensor units adjacent to each other.

Abstract: A pixelated image sensor having comprising a partially pinned photodiode which is formed a semiconductor of a first conductivity type formed on a surface of the sensor with at least one photodiode formed, within the semiconductor near the surface, the photodiode being formed from a second conductivity type opposite the first conductivity type; a pinning layer formed on the surface over at least a portion of the photodiode creating a pinned photodiode region, the pinning layer being formed from the first conductivity type; and an unpinned region formed near the surface in an area outside the portion used to form the pinning layer, the unpinned region is formed as a floating region that is employed as a capacitor. The partially pinned photodiode is useful in expanding the fill factor of photodetectors employing photodiode technology.

Abstract: A two-dimensional image sensor comprises a matrix array of photodiodes and multiple vertical shift registers horizontally divided into an imaging part and a memory part. During a vertical blanking period, the imaging part receives charge packets from the photodiodes and shifts the charge packets via the memory part to a matrix array of storage cells. During a subsequent horizontal blanking period, the charge packets are restored from the storage cells to the memory part and shifted downwards by the distance of a row so that the charge packets of bottom row are shifted our into a horizontal register. Remaining charge packets are then withdrawn from the memory part to the storage cells and stored therein during a subsequent horizontal scan period. During this horizontal scan period, the memory part is maintained at such a voltage that no dark currents substantially exist and the charge packets in the horizontal register are sequentially delivered to external circuitry.

Abstract: A solid-state imaging device of a vertical overflow drain system according to the present invention includes a first conductive type semiconductor substrate, a second conductive type semiconductor well region formed on the first conductive type semiconductor substrate, and a first conductive type, second conductive type or intrinsic high-resistance semiconductor region formed on the second conductive semiconductor well region and having a lower concentration as compared with the second conductive semiconductor well region and a width enough for infrared ray to be sufficiently absorbed. A light receiving portion is formed on a surface of the first conductive type, second conductive type or intrinsic high-resistance semiconductor region.

Abstract: A photosensitive device includes an array of active pixel sensor devices, each APS device being formed in an isolated cell of silicon. Each cell has an insulating barrier around it, and sits upon an insulating layer formed on an underlying substrate. A semiconductor connector making vertical contact between the pinning layer and the body of each APS device preferably replaces at least some portion of the insulating barrier adjacent to each cell. The semiconductor connector may be a single vertical connection for each cell or it may be an elongated strip connecting multiple APS devices. It may extend only to the underlying insulating layer or it may extend through the insulating layer to the substrate, with the substrate acting to interconnect and ground the pinning layer and the body of each APS device. The invention also includes the method of making the photosensitive device.

Abstract: The lateral overflow drain for charge coupled devices includes: a semiconductor region 70 of a first conductivity type having a trench 92; a drain region 24 of a second conductivity type below the trench 92; a gate 20 in the trench 92 overlying and separated from a portion of the semiconductor region 70; and a virtual gate 30 of the first conductivity type in the semiconductor region 70 adjacent the trench 92.

Abstract: In an active pixel sensor having a plurality of pixels, each of the pixels having a photodetector for accumulating charge from incident light, a transfer gate for removing charge from the photodetector, a floating diffusion that acts as a sense node to an amplifier input, and a drain the improvement comprising the provision of a reset mechanism for each pixel by application of a potential adjacent the floating diffusion such that the area between the floating diffusion and the drain becomes depleted.

Abstract: A solid-state imaging device provided here comprises a p-type semiconductor substrate, a p-type impurity layer formed thereon, a light-intercepting part formed inside said impurity layer for storing signal charges produced through incident light, and a n-type drain part formed in a region of the substrate excluding the light-intercepting part for discharging excess charges of the light-intercepting part. As a result, sensitivity characteristics on the long wavelength side can be improved, and miniaturization can be facilitated. An n-type buried drain part for discharging charges is formed under a transfer part via a p-type impurity layer. The readout side between the light-intercepting part and the transfer part is separated by a p-type readout control part which is installed to control threshold voltage (Vt), and the non-readout side is separated by a channel stopper.

Abstract: A semiconductor device and a method of inspecting the same are described. The semiconductor device does not need voltage adjustment of an external driver circuit, since it contains a voltage generator to inspect and memorize the best value of voltage by controlling from outside. The voltage generator has a plurality of capacitors whose electrodes of one side are connected to a common node, a potential changing circuit to change the potential to which the other electrodes of these capacitors are connected respectively, and a buffer amplifier whose input power is the voltage generated in the common node. The output power of the buffer amplifier is connected to a semiconductor integrated circuit. The potential changing circuit is provided to change the potential to which the electrode of each capacitor is connected to a source potential or to a ground potential depending on the connection of the fuse connected between the source and each of the capacitors.

Abstract: A charge-coupled device image sensor includes a substrate, a buried channel region of a first conductivity type, formed in the substrate to a predetermined depth, for transferring signal charges, a first high concentration impurity region of a second conductivity type, formed in the substrate adjacent to the buried channel region, forming a channel stop, a first surface channel region of the second conductivity type, formed on the buried channel region, for transferring dark current charges, a second high concentration impurity region of the first conductivity type, formed on the first high concentration impurity region, for removing dark current charges from the surface channel region, and a second surface channel region of the second conductivity type formed to a predetermined depth in the substrate between the second high concentration impurity region and the first surface channel region.

Abstract: There is disclosed a solid-state imager for preventing an unwanted potential barrier in the overflow control gate when ions are implanted into the sensor portion. The imager is capable of easily controlling the amount of overflow. The sensor portion takes the hole accumulation diode (HAD) sensor structure. A potential barrier is created in the overflow control gate by ion implantation. A potential difference created between the overflow control gate and the sensor portion is determined by the amount of ions implanted. A DC voltage V.sub.D applied to the overflow drain is variable. The potential difference is adjusted by varying the DC voltage V.sub.D. Thus, elements of the imager are uniform in potential barrier.

Abstract: A CCD pixel 10 has an antiblooming structure including a lateral overflow drain 36 of one conductivity. The drain 36 is mounted on one side by a heavy dope channel stop region. The rest of drain 36 is bounded by a heavily doped container region 38 that is formed in the same opening that is used to form LOD 36.

Abstract: A solid state imaging device and method of operating the same includes an imaging section for converting incident light into a signal charge which is temporarily stored in a storage section before being read out. A vertical transfer register extends from an imaging section to a storage section. A transfer clock pulse is applied to a portion of the vertical transfer register disposed in the storage section such that the potential of the vertical transfer register in the storage section is deeper than that in the imaging section. Excess charge is transferred to a smear drain section. According to an alternate feature, the potential of the vertical transfer register within either the imaging section or the storage section is maintained constant. A further feature makes use of two drain regions disposed at respective distal ends of the imaging section and the storage section.

Abstract: A synchronously gated high speed CCD imager system having a predetermined frame time includes: a CCD interline transfer array including a plurality of photoelectric collection quantum wells for collecting photoelectrons from an object; a plurality of storage wells associated with the collection wells; an anti-blooming circuit for diverting photoelectrons from accumulating in the collection wells; and switching means for transferring the photoelectrons accumulated in the collection wells to the storage wells and enabling the anti-blooming circuit during synchronized portions of the frame time to divert photoelectrons from accumulating in the collection wells and for disabling the anti-blooming circuit to enable the collection wells to collect photoelectrons during another portion of the frame time.