Abstract: A semiconductor device includes: a substrate; a buffer layer including GaN formed on the substrate, wherein: surfaces of the buffer layer are c facets of Ga atoms; a channel layer including GaN or InGaN formed on the buffer layer,wherein: surfaces of the channel layer are c facets of Ga or In atoms; an electron donor layer including AlGaN formed on the channel layer, wherein: surfaces of the electron donor layer are c facets of Al or Ga atoms; a source electrode and a drain electrode formed on the electron donor layer; a cap layer including GaN or InGaAlN formed between the source electrode and the drain electrode, wherein: surfaces of the cap layer are c facets of Ga or In atoms and at least a portion of the cap layer is in contact with the electron donor layer; and a gate electrode formed at least a portion of which is in contact with the cap layer.

Abstract: In a semiconductor device, a wiring pattern groove is formed in a surface portion of a silicon oxide film provided above a semiconductor substrate. A wiring layer is buried into the wiring pattern groove with a barrier metal film interposed therebetween. The barrier metal film is selectively removed from each sidewall portion of the wiring pattern groove. In other words, the barrier metal film is left only on the bottom of the wiring pattern groove. Thus, a damascene wiring layer having a hollow section whose dielectric constant is low between each sidewall of the wiring pattern groove and each side of the wiring layer can be formed in the semiconductor device.

Abstract: An organic device including a substrate or a dielectric layer; a photoresist layer formed on the substrate or dielectric layer, wherein the photoresist layer is provided with a plurality of microgrooves having an alignment direction; an organic semiconducting layer having alignment formed on the photoresist layer, wherein the organic semiconducting layer aligns according to the alignment direction of the microgrooves of the photoresist layer; and an electrode.

Abstract: An organic device including a substrate or a dielectric layer; a photoresist layer formed on the substrate or dielectric layer, wherein the photoresist layer is provided with a plurality of microgrooves having an alignment direction; an organic semiconducting layer having alignment formed on the photoresist layer, wherein the organic semiconducting layer aligns according to the alignment direction of the microgrooves of the photoresist layer; and an electrode.

Abstract: A high electron mobility transistor is constructed with a substrate, a lattice-matching buffer layer formed on the substrate, and a heavily doped p-type barrier layer formed on the buffer layer. A spacer layer is formed on the barrier layer, and a channel layer is formed on the spacer layer. The channel layer may be of uniform composition, or may be made from two or more sublayers. A Schottky layer is formed over the channel layer, and source and drain contacts are formed on the Schottky layer. The substrate may be gallium arsenide, indium phosphide, or other suitable material, and the various semiconductor layers formed over the substrate contain indium. The transistor's transition frequency of the transistor is above 200 GHz.

Abstract: A method of fabricating a semiconductor transistor device comprises the steps as follows. Provide a semiconductor substrate with a gate dielectric layer thereover and a lower gate electrode structure formed over the gate dielectric layer with the lower gate electrode structure having a lower gate top. Form a planarizing layer over the gate dielectric layer leaving the gate top of the lower gate electrode structure exposed. Form an upper gate structure over the lower gate electrode structure to form a T-shaped gate electrode with an exposed lower surface of the upper gate surface and exposed vertical sidewalls of the gate electrode. Remove the planarizing layer. Form source/drain extensions in the substrate protected from the short channel effect. Form sidewall spacers adjacent to the exposed lower surface of the upper gate and the exposed vertical sidewalls of the T-shaped gate electrode. Form source/drain regions in the substrate.

Abstract: A method for fabricating a junction field effect transistor (JFET) with a double dose gate structure. A trench is etched in the surface of a semiconductor substrate, followed by a low dose implant to form a first gate region. An anneal may or may not be performed after the low dose implant. A gate definition spacer is then formed on the wall the trench to establish the lateral extent of a second, high dose implant gate region. After the second implant, the gate is annealed. The double dose gate structure produced by the superposition of two different and overlapping regions provides an additional degree of flexibility in determining the ultimate gate region doping profile. A further step comprises using the gate definition spacer to define the walls of a second etched trench that is used to remove a portion of the p-n junction, thereby further reducing the junction capacitance.

Abstract: A confocal three dimensional inspection system, and process for use thereof, allows for rapid inspecting of bumps and other three dimensional (3D) features on wafers, other semiconductor substrates and other large format micro topographies. The sensor eliminates out of focus light using a confocal principal to create a narrow depth response in the micron range.

Abstract: An integrated circuit including a field effect transistor (FET) is provided in which the gate conducter has an even number of fingers disposed between alternating source and drain regions of a substrate. The fingers are disposed in a pattern over an area of the substrate having a length in a horizontal direction, the area equaling the length multiplied by a width in a vertical direction that is occupied by an odd number of the fingers.

Abstract: A gate structure which includes a semiconductor substrate having a channel region, a gate insulator adjacent the channel region of the semiconductor substrate and a conductible gate adjacent the gate insulator. A primary insulation layer is adjacent the semiconductor substrate, the primary insulation layer having an opening where the gate insulator contacts the semiconductor substrate and an isolation dielectric layer adjacent the primary insulation layer, the isolation dielectric layer having an opening where the conductible gate is located and the isolation dielectric layer having a silicon oxynitride material.

Abstract: A GaAs-based semiconductor field-effect transistor in which electrons flowing from a source electrode to a drain electrode are controlled by a signal supplied to a gate electrode. The transistor includes an active layer made of a GaAs-based semiconductor material. A source electrode and a drain electrode are formed on the active layer. A gate electrode is formed on the active layer between the source electrode and the drain electrode. The thickness of an oxide layer of the GaAs-based semiconductor material on the active layer is approximately equal to the lattice constant of the GaAs-based semiconductor material. The thickness of the oxide layer is preferably about 4 through 6 Å, and, more preferably, about 5 Å.

Abstract: A method of forming a high fMAX deep submicron MOSFET, comprising the following steps of. A substrate having a MOSFET formed thereon is provided. The MOSFET having a source and a drain and including a silicide portion over a gate electrode. A first ILD layer is formed over the substrate and the MOSFET. The first ILD layer is planarized to expose the silicide portion over the gate electrode. A metal gate portion is formed over the planarized first ILD layer and over the silicide portion over the gate electrode. The metal gate portion having a width substantially greater than the width of the silicide portion over the gate electrode. A second ILD layer is formed over the metal gate portion and the first ILD layer. A first metal contact is formed through the second ILD layer contacting the metal gate portion, and a second metal contact is formed through the second and first ILD layers contacting the drain completing the formation of the high fMAX deep submicron MOSFET.

Abstract: A fuse for use in an integrated circuit includes a dielectric layer into which a trench or void is etched defined by a top opening and a bottom floor. The trench includes at least one undercut which forms an overhang in the dielectric layer partially shielding the bottom floor. A second or barrier layer deposited onto the dielectric layer is interrupted or non-continuous at the undercut. A third, or electrically conductive layer, is electrically continuous over the fuse. A weak spot in the third layer exists in the lack of structural support by the second layer at the interruption. A further weak spot in the third layer exists in the electrical isolation of the conductor layer, i.e. no leakage current through the barrier layer, at the interruption.

Abstract: A confocal three dimensional inspection system, and process for use thereof, allows for inspecting of bumps and other three dimensional (3D) features on wafers and other semiconductor substrates. The sensor eliminates out of focus light using a confocal principal to improve depth response.

Abstract: A dielectric film 4 made of a high dielectric material with a relative permittivity of 8 or more is laid between a field plate section 9 and a channel layer 2. Tantalum oxide (Ta2O5), for example, may be used as the high dielectric material.

Abstract: A gate electrode is in Schottky contact with the surface of a semiconductor substrate and extends in a first direction. A drain electrode is disposed on one side of the gate electrode, spaced apart from the gate electrode by some distance, and is in ohmic contact with the semiconductor substrate. A source electrode is constituted of a main part, an overhanging part and a shielding part. The main part is in ohmic contact with the semiconductor substrate in the region across the gate electrode from the drain electrode. The shielding part is disposed between the gate electrode and the drain electrode and extends in the first direction. The overhanging part passes over the gate electrode and connects the shielding part with main part. The size of the overhanging part along the first direction is smaller than the side of the shielding part.

Abstract: A plurality of p anode regions are formed at one surface of an n− substrate. A trench is formed in each p anode region. An ohmic junction region is formed between an anode metallic electrode and the p anode region. The p anode region has a minimum impurity concentration at a portion near the ohmic junction region which enables ohmic contact. A cathode metallic electrode is formed at the other surface of the n− substrate with an n+ cathode region interposed. Accordingly, a semiconductor device which has an improved withstand voltage and in which the reverse recovery current is reduced can be obtained.

Abstract: A semiconductor switching device of mirror logic includes two FETs having a gate width of 600 &mgr;m, a common input terminal, two control terminal and two output terminals. The resistors connecting the control terminals and the gate electrodes of FETs are placed underneath a pad metal layer extending from the common input terminal. Both FETs extend into the space between the control terminals and the output terminals. The device can be housed in the same package as the device of non-mirror logic.

Abstract: A field effect transistor includes a semiconductor substrate with a channel layer being formed on its surface, a source electrode and a drain electrode formed at a distance on said semiconductor substrate, and a gate electrode placed between the source electrode and the drain electrode and making a Schottky junction with the channel layer. The gate electrode is provided with an overhanging field plate section and between the field plate section and the channel layer, there is laid a dielectric film. When the relative permittivity and the film thickness of the dielectric film are denoted by ∈ and t (nm), respectively, the following condition is satisfied 5≦∈<8, and 100<t<350.

Abstract: As an outside box mark for automatic overlay measurement formed on a semiconductor substrate, a # shape is formed by laying two vertical lines formed by word lines over two parallel lines formed of bit lines. Thereby, a misalignment value in the word line direction and a misalignment value in the bit line direction are measured simultaneously by using one box mark. When forming capacity contacts between wiring lines of a #-shaped structure formed of word lines and bit lines, it is conducted by using a box mark for automatic overlay measurement. As a result, it becomes possible to shorten the time required for measuring the misalignment values in the X direction (word lines) and Y direction (bit lines) and analyzing the measurement result.

Abstract: An LDMOS device (10, 20, 50, 60) that is made with minimal feature size fabrication methods, but overcomes potential problems of misaligned Dwells (13). The Dwell (13) is slightly overstated so that its n-type dopant is implanted past the source edge of the gate region (18), which permits the n-type region of the Dwell to diffuse under the gate region (18) an sufficient distance to eliminate misalignment effects.

Abstract: A new method is provided for the creation of openings in a layer of dielectric while at the same time forming a dielectric that forms the dielectric of MIM capacitors. Under the first embodiment of the invention a layer of insulation, such as SixNy or SiON or TaN and TiN, is deposited over the surface of a semiconductor substrate, points of electrical contact have been provided in this semiconductor surface. A layer of IMD is deposited over the layer of insulation, an opening is created in the layer of IMD that aligns with and overlays a contact point over which a MIM capacitor is to be created. Under the second embodiment of the invention, a stack of three layers of a first layer of TaN followed by SiOx or SixNy followed by a second layer of TaN is used as the dielectric layer for the capacitor whereby the first layer of TaN is used as an etch stop for an opening that is etched for the creation of the upper plate of the capacitor.

Abstract: A thin film transistor includes a substrate, a gate electrode on the substrate, a gate insulating layer on the substrate and covering the gate electrode, an active layer on the gate insulating layer, an ohmic contact layer on the active layer and not overlapping the gate electrode, and a source electrode and a drain electrode connected to the ohmic contact layer. Each of the source electrode and the drain electrode has a double-layered structure of a first metal layer having tensile stress and a second metal layer having compressive stress.

Abstract: A transistor structure with a degradation-stop layer that prevents degradation of underlying semiconductor layers while minimizing any increase in the gate leakage current is disclosed. In one embodiment, a transistor structure includes: a substrate; a channel layer formed of a charge transport material over the substrate; a Schottky barrier layer formed of an aluminum-containing material over the channel layer; a degradation-stop layer formed of a substantially aluminum-free material over the Schottky barrier layer; and a source, a drain and a gate. The source and the drain being formed over or alloyed through the degradation-stop layer, and a lower portion of the gate extends down through an exposed portion of the degradation-stop layer and is in physical and electrical contact with the Schottky barrier layer.

Abstract: A semiconductor component (1a) has a highly-doped substrate (4) of a first type of doping into which a highly-doped layer (15) of a second type of doping is introduced in some areas to form a pn Zener junction (16), and a low-doped area (17) of the second type of doping extends from this highly-doped layer (15) in the substrate (4) into an epitaxial layer (5) as far as the substrate (4) of the epitaxial layer (5). A Schottky metal (11) at least partially covering the low-doped, diffused area (17) is applied to the side of the epitaxial layer (5) facing away from the substrate (4) to form a Schottky junction (18) between this area (17) and the Schottky metal (11) and another Schottky junction (13) between the Schottky metal and the epitaxial layer (5). Due to the series connection of the oppositely polarized Zener diode and Schottky diode, a low temperature coefficient is achieved.

Abstract: A thin film transistor includes a thin film transistor layer having a source region, a channel region and a drain region. In one implementation, a gate of the transistor is disposed laterally proximate the thin film channel region and comprises an annulus which laterally encircles the laterally proximate thin film channel region. In another implementation, a channel region of a thin film transistor extends elevationally away from a substrate. Source and drain regions are operatively associated with the channel region and are elevationally spaced therealong and apart from one another. A gate is disposed over the substrate and laterally proximate the channel region.

Abstract: To enhance a drain current voltage characteristics of a compound semiconductor field effect transistor, an n-GaAs substrate is used. After forming an n.sup.- -GaAs layer and an i-AlGaAs layer successively on the substrate, an n-type transistor is formed on these layers. Subsequently, on the rear side of the n-GaAs substrate, an ohmic electrode is formed, to connect with a drain electrode on a surface side. In the structure, when a drain current is increased, at a drain side electron also flows toward the substrate, so that the current concentration on a drain region is relaxed. Thereby, the drain current voltage characteristics can be improved.

Abstract: A composite-layer semiconductor device includes a gate above a host substrate, an n++ contact layer above the gate, and source and drain ohmic contacts applied to the n++ contact layer. The source and drain ohmic contacts define a central gate location which is recessed through the n++ contact layer toward the gate. The source and drain ohmic contacts create a barrier to chemical etching so that a current path below the central gate location can be incrementally recessed in repeated steps to precisely tailor the operating mode of the device for depletion or enhancement applications. The composite-layer semiconductor device is fabricated by depositing a gate on an n++ contact layer above a semi-insulating substrate. The semi-insulating substrate and gate are flipped onto an epoxy layer on the host substrate so that the gate is secured to the epoxy layer and the semi-insulating substrate presents an exposed backside. A portion of the exposed backside is removed.

Abstract: A semiconductor device includes a gate structure formed on a substrate in which an LDD structure is formed, wherein gate structure includes a Schottky electrode making a Schottky contact with a channel region in the substrate, a low-resistance layer provided above the Schottky electrode, and a stress-relaxation layer interposed between the Schottky electrode and the stress-relaxation layer. The low-resistance layer and said stress-relaxation layer form an overhang structure with respect to the Schottky electrode.

Abstract: A compound semiconductor transistor has a structure in which a first insulating film is formed only under a overhang of a gate electrode an upper part of which is formed widely, and a second insulating film for threshold voltage adjustment is formed on the side of a gate electrode and the first insulating film.

Abstract: A MOSFET wherein the formation of a channel in a channel formation region is controlled by a voltage applied to an insulated gate, comprising: a semiconductor substrate; a first semiconductor layer (drain region) of a first conductivity type formed on a surface of the semiconductor substrate; a second semiconductor layer (body region) of a second conductivity type provided within the first semiconductor layer, where a part thereof forms the channel formation region; a third semiconductor layer (source region) of the first conductivity type provided selectively in the second semiconductor layer; and a body contact region in electrical contact with the second semiconductor layer. The body contact region is formed in an area that is separated from an active region by a non-active region. With this structure, parasitic bipolar transistors operate simultaneously throughout the entire device so that a uniform breakdown current is generated, thus preventing element destruction due to current concentrations.

Abstract: The formation of lightly doped regions under a gate of a transistor that has a reduced gate oxide is disclosed. In one embodiment, a method includes four steps. In the first step, a gate is formed over a semiconductor substrate. In the second step, the gate oxide is etched to reduce the length of the gate oxide. In the third step, a first ion implantation is applied, at an angle other than perpendicular to the substrate. Finally, in the fourth step, a second ion implantation is applied, perpendicular to the substrate.

Abstract: A method is provided for fabricating a transistor gate conductor having opposed sidewall surfaces upon which dielectric spacers are formed such that the spacer profile substantially tapers toward the adjacent gate conductor sidewall surface as it approaches the base of the gate conductor. More particularly, formation of the sidewall spacers involves anisotropically etching a dielectric material deposited across a semiconductor topography in the presence of a passivant source to form a passivant upon portions of the dielectric material. The passivant primarily accumulates upon the upper portion of lateral surfaces of the dielectric material. An isotropic etch which occurs at the same rate in all directions is used to etch portions of the dielectric material not completely covered by the passivant. The resulting spacers have a varying thickness which decreases from top to bottom.

Abstract: A semiconductor device includes a self-aligned refractory metal constituent in a recess in a semiconductor substrate and having the same plane pattern as a bottom surface of the recess. The width of the constituent is determined by the plane pattern of the recess and, accordingly, the pattern width of the constituent is easily controlled by the plane pattern of the recess.

Abstract: A silicon carbide MESFET (10) is formed to have a source (21) and a drain (22) that are self-aligned to a gate (16) of the MESFET (10). The gate (16) is formed to have a T-shaped structure with a gate-to-source spacer (18) and gate-to-drain spacer (19) along each side of a base of the gate (16). The gate (16) is used as a mask for implanting dopants to form the source (21) and drain (22). A laser annealing is performed after the implantation to activate the dopants. Because the laser annealing is a low temperature operation, the gate (16) is not detrimentally affected during the annealing.

Abstract: A conductive layer made of n-type GaAs is formed on a semi-insulating substrate made of GaAs. A pair of contact regions made of n.sup.+ -type GaAs are formed on the conductive layer. A source electrode is formed on the left-hand contact region, while a drain electrode is formed on the right-hand contact region. A gate recessed region is formed in the region of the conductive layer located between the pair of contact regions so that a gate electrode is formed on the gate recessed region. A depressed portion is formed in the gate recessed region of the conductive layer. The wall face of the depressed portion closer to the gate electrode is flush with or protruding from the side face of the gate electrode facing the drain electrode.

Abstract: In a semiconductor device, a gate electrode is formed by sequentially forming a Schottky metal film, a barrier metal film, and a low-resistance metal film from the lower side. The Schottky metal film or barrier metal film has a gap in a lower gate vertical portion. The gap is closed at its upper and lower portions. The overlaying low-resistance metal film does not extend into the lower gate vertical portion. A method for this semiconductor device is also disclosed.

Abstract: A method of fabricating a field effect transistor with a spike-gate structure including forming a semiconductor layer on a semi-insulating substrate, and forming a recess having a spike shape in which a portion of a gate electrode projects into the semiconductor layer, in the semiconductor layer. The formation of the recess includes forming a narrow damaged layer in the semiconductor layer by one of focused ion beamion implantation and ion implantation; and wet-etching the semiconductor layer utilizing accelerated etching of the damaged layer, thereby forming a recess having a spike groove. As described above, without performing the complicated processes as in the prior art fabricating method shown in FIGS. 12(a)-12(i), by performing one FIB implantation process, an FET with a spike-gate structure can be fabricated by using simpler and fewer processes.

Abstract: A method of improving the performance of a traveling wave field-effect transistor operated at frequencies in the microwave range or above the microwave range comprising the steps of forming a depletion region beneath a gate electrode wherein, in a plane transverse to the direction of signal propagation, a depletion region edge has a first end portion located between the gate electrode and a drain electrode and a second end portion located between the gate electrode and a source electrode; and separating the depletion region edge from the drain electrode. Further improvements in the operation of the TWFET include adjusting the first end portion of the depletion region edge to be closer to the gate electrode relative to the distance between the second end portion of the depletion region edge and the gate electrode, controlling an effective conductivity of a semiconductor of the traveling-wave field effect transistor, and setting the length of the gate electode at about one micron.

Abstract: A field effect transistor includes an active layer having a surface; a source electrode and a drain electrode disposed on the surface of the active layer; a first gate electrode disposed on the surface of the active layer between the source electrode and the drain electrode, having a T-shaped cross section, and a lower layer and an upper layer, the lower layer contacting the active layer, and the upper layer being disposed on the lower layer and having a lower resistivity than the lower layer, and being longer than the lower layer in the direction parallel to the gate length; and a second gate electrode disposed on the surface of the active layer between the first gate electrode and the drain electrode, having a rectangular cross section and a single layer. The gate resistance of the first gate electrode is reduced, whereby efficiency is improved and noise is reduced.

Abstract: A semiconductor device has an active layer formed on a semiconductor substrate with different types of junctions, a source region, a drain region, a T-shaped gate electrode in which the cross-sectional area of the upper surface is larger than that of the lower surface, a first dielectric layer covering at least the exposed surface of the active layer, and the gate electrode, and a second dielectric layer enclosing the first dielectric layer. In the device, when the specific inductive capacities of the first and second dielectric layers are .epsilon.(1) and .epsilon.(2) respectively .epsilon.(1)<.epsilon.(2) and the water absorption ratio of the first dielectric layer is greater than the water absorption ratio of the second dielectric layer.

Abstract: The present invention is a sidewall connector providing a conductive path linking at least two conductive regions. The sidewall connector has a top portion comprising surface. A conductive member contacts the top portion, connecting the rail to a conductive region or to an external conductor. An etch stop layer located on a conductive region can be used to protect the conductive region during the directional etch to form the sidewall connector. A conductive bridge is then used to link exposed portions of the conductive region and the conductive sidewall rail, the conductive bridge extending across the thickness of the etch stop layer. A "T" connector is formed by the process, starting with a pair of intersecting sidewalls wherein the two sidewalls have top edges at different heights where they intersect. The connector is used to form a strap for a DRAM cell.

Abstract: On a semi-insulating substrate is formed a conductive layer and an undoped layer. On specified regions of the conductive layer are formed ohmic electrodes, each serving as a source electrode or a drain electrode, via a pair of square contact regions. The circumferential edges of the contact regions are undercut beneath the ohmic electrodes. Between the pair of contact regions on the conductive layer is formed a gate electrode by self alignment using the ohmic electrodes as a mask. The gate electrode has extended in the direction of gate width and the extended portion serves as a withdrawn portion of the gate electrode. Upper electrodes are formed by self alignment in the same process in which the gate electrode is formed.

Abstract: A method of fabricating a self-aligned FET having a semi-insulating substrate of GaAs or InP with a conductive channel formed either by doping the surface or an epitaxially grown channel by molecular beam epitaxy or metalorganic vapor phase epitaxy in the substrate adjacent the surface. Forming a high temperature stable LaB.sub.6 /TiWN "T-shaped" Schottky gate contact on the substrate surface, which is used for source and drain ohmic region implants into the substrate adjacent to the surface and self-aligned to the "T-shaped" gate, with source and drain ohmic contacts also self-aligned with respect to the gate.

Abstract: A high power output semiconductor device having a plurality of FET elements on a semi-insulating semiconductor substrate including a first conductivity type semiconductor layer on the semi-insulating semiconductor substrate, a plurality of source and drain electrodes alternatingly arranged on the semiconductor layer, a plurality of gate electrodes respectively disposed in gate recesses formed by etching respective surface regions of the semiconductor layer between each adjacent source and drain electrodes. The gate recess has a asymmetrical two-stage recess structure having a second bottom surface only at the source side of the recess at a depth between a first bottom surface in contact with the gate electrode and the upper surface of the semiconductor layer and is not in contact with the gate electrode.

Abstract: A monolithic-microwave-integrated-circuit (MMIC) metal-semiconductor-field-effect (MESFET) transistor (40) or other type of field-effect transistor has a double-recessed channel region (32,42) with a gate recess (42) formed in a channel recess (32). The channel recess (32) is offset toward the drain (16) as far as possible without shorting the channel recess (32) to the drain (16) to increase the transistor breakdown voltage. The gate recess (42) is offset toward the source (14) as far as possible without causing the gate-source capacitance to increase, thereby reducing the transistor source resistance.

Abstract: A field effect transistor (10) has an active layer (16) formed in a substrate (12). A gate (20) is disposed on an elevated platform (18) formed from the active layer (16). The elevated platform (18) raises the bottom surface (21) of the gate (20) relative to the top surface (34, 36) of the active region (13) on either side of the gate (20). A fabrication method for the transistor (10) forms the elevated platform (18) by etching the active region surface (44) on both sides of the gate (20) so that the bottom surface (21) of the gate (20) is elevated relative to the top surface (34) of the surrounding active region (13). The gate (20) itself and/or a patterned photoresist layer (116) may be used as a mask for performing this etch.

Abstract: In a recessed structure MESFET, an active layer (n-type layer) 2 is provided on a high resistance GaAs substrate 1, a pair of contact layers (n.sup.+ -type layers) 31, 32 is provided on the active layer 2, a source electrode 6 is provided on one contact layer 31, a drain electrode 7 is provided on the other contact layer 32 and a gate electrode 5 is provided on the active layer 2 to achieve a recessed structure. A semiconductor layer 4 having a lower impurity density than that of the contact layer 31, 32 is formed at the recess edge portion at at least drain side to alleviate the concentration of the electric field and current there to suppress the generation of electron-holes pairs by collision ionization to reduce the damage to the crystal lattice by non-luminescence recombination of the electron-holes thus preventing the degradation of the FET characteristics.

Abstract: A field effect transistor with improved operation speed and reduced noise includes a drain electrode disposed on a channel layer with a contact layer interposed therebetween, a source electrode, and a gate electrode disposed between the drain and source electrodes. A resonant tunneling diode is disposed between the source electrode and the channel region for supplying hot electrons to the channel layer beneath the gate electrode.

Abstract: A dual gate field effect transistor including first and second gates comprises a conductive region, wherein a potential difference between a second gate electrode section and the conductive region is larger than that between the second gate electrode section and a channel operation region.