Abstract: A static induction thyristor has a first semiconductor area having a high impurity concentration of a first conductivity type. A second semiconductor area having low impurity concentration is formed adjacent to the first semiconductor area. A third semiconductor area having a high impurity concentration of a second conductivity type which is the conductivity type opposite to the first conductivity type is formed on a part of a surface of the second semiconductor area so located as to form a fourth semiconductor area located within the third semiconductor area. A fifth semiconductor area having a high impurity concentration of the first conductivity type is formed on the part of the surface of the second semiconductor area in spaced relation to the forth semiconductor area.

Abstract: In a method of making a semiconductor device, an active layer and a heavily doped cap layer are formed in turn on a semiconductor substrate, a first electrode is formed on the cap layer, a mask of a two-layer structure is formed on the cap layer, with the mask having an insulating film pattern having a non-inverted tapered opening, and a resist pattern having an inverted tapered opening and continuous with the non-inverted tapered opening, these openings being separated by a predetermined distance from the first electrode, and then a recess is formed, by performing an isotropic etching of the heavily doped layer exposed in the openings, with the recess having a bottom surface and a side wall surface rising from an edge of the bottom surface toward the upper edge with a constant radium off curvature. An oblique vapor deposition is then performed to form a second electrode to cover the bottom surface and the part of the side wall surface.

Abstract: A compound semiconductor device such as HEMTs (High Electron Mobility Transistors), metal semiconductor field effect transistors, and the like includes a compound semiconductor substrate having an active region, an insulating film provided over the semiconductor substrate, source and drain electrodes provided on the active region, and a gate electrode located between the source and drain electrodes. In the structure, the gate electrode has a lower electrode portion for providing a Schottky barrier contact with the active region through an opening of the insulating film, and an upper electrode portion provided on the insulating film to extend toward only the drain electrode.

Abstract: A field-effect transistor of a recessed structure having an etch stopper layer is disclosed. The etch stopper layer is composed of gallium phosphide or aluminium arsenide. The etch stopper layer protects an underlying semiconductor active layer of a metal-semiconductor field-effect transistor or an underlying donor layer of a two-dimensional electron gas field-effect transistor during etching the cap layer for forming a recess receiving a gate electrode. In case of etch stopper layer of aluminium arsenide, the etch stopper layer can be etched by ultrapure water.

Abstract: A method for producing a T-shaped gate electrode of a semiconductor device including forming an insulating film on a semiconductor substrate, etching away a prescribed region of the insulating film, depositing a metal film having a prescribed thickness, forming a first photoresist film and removing the photoresist film except where the insulating film has been removed, forming a second photoresist film, patterning the second photoresist film to expose the metal film along a sidewall of the insulating film, etching away a portion of the metal film using the first and second photoresist films as a mask, depositing a gate metal and removing the first and second photoresist films and overlying gate metal by lift-off, and etching away the metal films remaining on the semiconductor substrate and the insulating film. Thereby, a T-shaped gate electrode with shortened length is formed.

Abstract: A compound semiconductor device includes a first semiconductor layer, a second semiconductor layer providing source and drain regions, and a composite layer consisting of a bottom SiN layer, and SiON layer and a top SiN layer on the second semiconductor layer. A gate electrode has a perpendicular portion extending through an opening in the composite layer and an enlarged region above the top SiN layer to support the electrode at a position closer to the source region than the drain region, and the bottom SiN layer and the SiON layer are recessed so as to be spaced from the gate electrode.

Abstract: A multistage amplifier device including an amplifier at the first stage or each of active elements of amplifiers at plural stages containing the first stage and excluding the last stage which is formed of FETs 1a and 1b including a gate having a self-alignment structure, and amplifiers at the remaining subsequent stages which are formed of FETs 1c and 1d including a gate electrode on an operating layer sandwiched between source and drain high impurity density regions, one edge portion at a source side of the gate electrode being overlapped through an insulating layer with the source high impurity density region while the other edge portion at a drain side of the gate electrode does not expand to the drain high impurity density region.

Abstract: A semiconductor device includes a semiconductor substrate, an active layer formed on the semiconductor substrate, source and drain electrodes respectively formed on the active layer, a gate electrode formed on the active layer between the source and drain electrodes and including a gate contact portion which makes contact with the active layer and has a thickness greater than those of the source and drain electrodes and an overgate portion which is connected to the gate contact portion and extends over at least a portion of one of the source and drain electrodes, a first insulator layer formed on the active layer and covering the source and drain electrodes and the gate contact portion, a first contact hole in the first insulator layer through which the overgate portion connects to the one of the source and drain electrodes, a second insulator layer formed on the first insulator layer and covering the overgate portion, a second contact hole in the second insulator layer at a position above the overgate portio

Abstract: A method of producing a MESFET, and the MESFET formed by the method, which includes forming a refractory metal gate structure on an active layer formed in or on a semiconductor substrate. Source and drain regions are formed adjacent the gate structure. An insulating film is deposited over the partly formed structure to form a film portion on the semiconductor substrate which is separated from further film portions formed over the source and drain regions. A flattening resist is deposited over the insulating film and etched to expose only the film portion on the gate structure, while the gate structure itself and the resist protects the film portions on the source and drain regions. The film portion over the gate structure can thus be removed without damage to the gate structure or the remainder of the insulting film. A low resistance metal is patterned and deposited over the gate structure and overlies, in part, at least a part of the insulating film which remains over the source and drain regions.

Abstract: A self-aligned, under-gated TFT device (10). A base layer (14) is formed. A conductive layer (16) is formed overlying the base layer (14). A dielectric layer (18) is formed overlying the conductive layer (16). A sacrificial layer (20) is formed overlying the dielectric layer (18). The layers (16, 18, and 20) are etched to form a "pillar" region. A dielectric layer (22) and a planar layer (24), which both overlie the "pillar" region, are etched back to form a substantially planar surface and expose a top portion of the sacrificial layer (20). The sacrificial layer (20) is removed and a conductive layer (28) is formed overlying conductive region (16) and planar layer (22). Conductive layer (28) is used to form a self-aligned TFT device (10) via the formation of a source region (33) and a drain region (34) adjacent an aligned plug region (32).

Abstract: A channel layer, donor layer, Schottky layer, and cap layer are formed on a substrate. A source and drain are formed on the cap layer. A gate is formed on the cap layer, or at the bottom of a recess which is formed through the cap layer and partially extends into the Schottky layer. The donor and Schottky layers are formed of a semiconductive material which includes an oxidizable component such as aluminum. A passivation or stop layer of a lattice-matched, non-oxidizable material is formed underlying the source, drain, and gate, and sealingly overlying the donor layer. The stop layer may be formed between the Schottky layer and the donor layer, or constitute a superlattice in combination with the Schottky layer consisting of alternating stop and Schottky sublayers. Alternatively, the stop layer may sealingly overlie the Schottky layer, and further constitute the cap layer.