Abstract: A microelectronic device comprises a stack structure, at least one staircase structure, contact structures, and support structures. The stack structure comprises vertically alternating conductive structures and insulating structures arranged in tiers, each of the tiers individually comprising one of the conductive structures and one of the insulating structures. The at least one staircase structure is within the stack structure and has steps comprising edges of at least some of the tiers. The contact structures are on the steps of the at least one staircase structure. The support structures horizontally alternate with the contact structures in a first horizontal direction and vertically extend through the stack structure. The support structures have oblong horizontal cross-sectional shapes. Additional microelectronic devices, memory devices, and electronic systems are also described.

Abstract: A three-dimensional semiconductor memory device includes a peripheral logic structure on a semiconductor substrate. A horizontal semiconductor layer is on the peripheral logic structure and includes a cell array region and a connection region. Electrode structures extend in a first direction on the horizontal semiconductor layer and are spaced apart in a second direction intersecting the first direction. A pair of the electrode structures adjacent to each other are symmetrically disposed to define a contact region partially exposing the horizontal semiconductor layer. A through via structure is on the contact region and connects the electrode structures to the peripheral logic structure. Each of the electrode structures includes a plurality of gate insulation regions extending along the first direction on the connection region. The gate insulation regions have different lengths from each other in the first direction.

Abstract: A 3D flash memory device includes a substrate having a substantial planar surface. A plurality of active columns of semiconducting material is disposed above the substrate. Each of the plurality of active columns extends along a first direction orthogonal to the planar surface of the substrate. The plurality of active columns is arranged in a two-dimensional array. Each of the plurality of active columns may comprise multiple local bit lines and multiple local source lines extending along the first direction. Multiple channel regions are disposed between the multiple local bit lines and multiple local source lines. A word line stack wraps around the plurality of active columns. A charge-storage element is disposed between the word line stack and each of the plurality of active columns.

Abstract: A semiconductor device includes conductive patterns stacked and spaced apart from each other in a first direction to form a stepped structure, a stepped insulating layer overlapping the stepped structure, contact plugs extending through the stepped insulating layer in the first direction to contact respective contact portions of the conductive patterns, and barrier patterns disposed on sidewalls of the stepped insulating layer.

Abstract: A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the semiconductor pillar and the second electrode, a second insulating film provided between the first electrode and the second electrode and on two first-direction sides of the first electrode, and a conductive film provided between the second electrode and the second insulating film, the conductive film not contacting the first insulating film.

Abstract: A multilayer structure includes a substrate and a plurality of sub-stacks extending along a first direction respectively and disposed on an upper surface of the substrate along a second direction. Each of the sub-stacks includes insulating layers and patterned sacrificial layers alternately stacked on the upper surface along a third direction; conductive layers alternately stacked on the upper surface with the insulating layers along the third direction; and interlayer connectors extending along the third direction; wherein the patterned sacrificial layers have first sides and second sides opposite to the first sides, the conductive layers include first side conductive layers corresponding to the first sides and second side conductive layers corresponding to the second sides; wherein the interlayer connectors are electrically connected and directly contact corresponding ones of the conductive layers, and the first direction, the second direction, and the third direction are crossed.

Abstract: A three-dimensional (3D) memory device is provided and includes a substrate, an alternating stack and a channel structure. The alternating stack is disposed on the substrate, and the alternating stack includes a plurality of conductive layers and a plurality of air gap layers alternately stacked. The channel structure is disposed on the substrate and extends vertically through the conductive layers and the air gap layers. The alternating stack further includes a plurality of etching stop blocks between the air gap layers and the channel structure.

Abstract: Aspects of the disclosure provide a semiconductor device. The semiconductor device includes gate layers and insulating layers that are stacked alternatingly along a direction perpendicular to a substrate of the semiconductor device and form a stack upon the substrate. The semiconductor device includes an array of channel structures that are formed in an array region of the stack. Further, the semiconductor device includes a first staircase formed of a first section of the stack in a connection region upon the substrate, and a second staircase formed of a second section of the stack in the connection region upon the substrate. In addition, the semiconductor device includes a dummy staircase formed of the first section of the stack and disposed between the first staircase and the second staircase in the connection region.

Abstract: An integrated circuit having a vertical transistor includes first through fourth gate lines extending in a first direction and sequentially arranged in parallel with each other, a first top active region over the first through third gate lines and insulated from the second gate line, and a second top active region. The first top active region forms first and third transistors with the first and third gate lines respectively. The second top active region is over the second through fourth gate lines and insulated from the third gate line. The second top active region forms second and fourth transistors with the second and fourth gate lines respectively.

Abstract: Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body.

Abstract: A vertical 3D memory device may comprise: a substrate including a plurality of conductive contacts each coupled with a respective one of a plurality of digit lines; a plurality of word line plates separated from one another with respective dielectric layers on the substrate, the plurality of word line plates including at least a first set of word lines separated from at least a second set of word lines with a dielectric material extending in a serpentine shape and at least a third set of word lines separated from at least a fourth set of word lines with a dielectric material extending in a serpentine shape; at least one separation layer separating the first set of word lines and the second set of word lines from the third set of word lines and the fourth set of word lines, wherein the at least one separation layer is parallel to both a digit line and a word line; and a plurality of storage elements each formed in a respective one of a plurality of recesses such that a respective storage element is surrounded

Abstract: A vertical memory device includes gate electrodes on a substrate. The gate electrodes are spaced apart from each other in a vertical direction. A channel penetrates the gate electrodes and extends in the vertical direction. A tunnel insulation pattern is formed on an outer sidewall of the channel. A charge trapping pattern structure is formed on an outer sidewall of the tunnel insulation pattern adjacent the gate electrodes in a horizontal direction. The charge trapping pattern structure includes upper and lower charge trapping patterns. A blocking pattern is formed between the charge trapping pattern structure and each of the adjacent gate electrodes. An upper surface of the upper charge trapping pattern is higher than an upper surface of the adjacent gate electrode. A lower surface of the lower charge trapping pattern is lower than a lower surface of an adjacent gate electrode.

Abstract: Disclosed are DRAM devices and methods of forming DRAM devices. One non-limiting method may include providing a device, the device including a plurality of angled structures formed from a substrate, a bitline and a dielectric between each of the plurality of angled structures, and a drain disposed along each of the plurality of angled structures. The method may further include providing a plurality of mask structures of a patterned masking layer over the plurality of angled structures, the plurality of mask structures being oriented perpendicular to the plurality of angled structures. The method may further include etching the device at a non-zero angle to form a plurality of pillar structures.

Abstract: A memory device includes a cross-point array of spin-torque transfer MRAM cells. First rail structures laterally extend along a first horizontal direction. Each of the first rail structures includes a vertical stack including, from bottom to top, a first electrically conductive line, a reference layer having a fixed magnetization direction, and a tunnel barrier layer. Second rail structures laterally extend along a second horizontal direction. Each of the second rail structures includes a second electrically conductive line that overlies the first rail structures. A two-dimensional array of pillar structures is located between a respective one of the first rail structures and a respective one of the second rail structures. Each of the pillar structures includes a free layer having energetically stable magnetization orientations that are parallel or antiparallel to the fixed magnetization direction.

Abstract: A semiconductor structure, integrated circuit device, and method of forming semiconductor structure are provided. In various embodiments, the semiconductor structure includes a substrate containing a high topography region and a low topography region, an outer protection wall on an outer peripheral portion of the high topography region next to the low topography region, and an anti-reflective coating over the outer protection wall, the high topography region, and the low topography region.

Abstract: A semiconductor device may comprise a plurality of conductive lines and a plurality of contact plugs. The plurality of conductive lines may include a first conductive line a second conductive line. The plurality of contact plugs may include a first contact plug and a second contact plug. The first contact plug may have a first pillar portion and a first protruding portion protruding from a sidewall of the first pillar portion at a first depth, so as to be in alignment and contact with a sidewall of the first conductive line. The second contact plug may have a second pillar portion and a second protruding portion protruding from a sidewall of the second pillar portion at a second depth, so as to be in alignment and contact with a sidewall of the second conductive line.

Abstract: In a method of manufacturing a non-volatile memory device, a stack structure may be formed on a semiconductor substrate. The stack structure may be etched to form a contact hole through the stack structure. The contact hole may be filled with a gap-filling insulation layer. Ions may be implanted into a target position of the gap-filling insulation layer. The gap-filling insulation layer may be selectively removed to define a preliminary junction region. A junction region may be formed in the preliminary junction region.

Abstract: The present disclosure relates to split gate flash MLC based neuromorphic processing and method of making the same. Embodiments include MLC split-gate flash memory formed over a substrate, the MLC split-gate flash memory embedded with artificial neuromorphic processing to dynamically program and erase each cell of the MLC split-gate flash memory; and sense visual imagery by the artificial neuromorphic processing.

Abstract: A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, at least one memory cell, and at least one word line. The raised dummy feature is present on the semiconductor substrate and defines a cell region on the semiconductor substrate. The memory cell is present on the cell region. The word line is present adjacent to the memory cell.

Abstract: A semiconductor device includes gate electrodes stacked along a direction perpendicular to an upper surface of a substrate, the gate electrodes extending to different lengths in a first direction, and each gate electrode including subgate electrodes spaced apart from each other in a second direction perpendicular to the first direction, and gate connection portions connecting subgate electrodes of a same gate electrode of the gate electrodes to each other, channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, and dummy channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, the dummy channels including first dummy channels arranged in rows and columns, and second dummy channels arranged between the first dummy channels in a region including the gate connection portions.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack, and a NAND memory string. The memory stack includes a plurality of interleaved gate conductive layers and gate-to-gate dielectric layers above the substrate. Each of the gate-to-gate dielectric layers includes a silicon oxynitride layer. The NAND memory string extends vertically through the interleaved gate conductive layers and gate-to-gate dielectric layers of the memory stack.

Abstract: A semiconductor memory device includes a memory cell; and a page buffer including a sensing circuit that is coupled to the memory cell through a bit line. The page buffer includes a first transistor included in the sensing circuit; and a second transistor not included in the sensing circuit. A cross-sectional dimension of a first contact which is coupled to the first transistor and a cross-sectional dimension of a second contact which is coupled to the second transistor are different from each other. The cross-sectional dimension of the second contact is smaller than the cross-sectional dimension of the first contact.

Abstract: Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include forming a thin silicon germanium material in a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material. A source/drain material may be formed on the thin silicon germanium material, wherein the dislocations induce a tensile strain in a channel region of the device.

Abstract: A method, an apparatus, and a computer program product are provided. The apparatus may be a regulator circuit. The regulator circuit includes a first voltage regulator to regulate a first input voltage to the first voltage regulator, the first voltage regulator including a P-type metal-oxide-semiconductor (PMOS), and a second voltage regulator to regulate a second input voltage to the second voltage regulator, the second voltage regulator including an N-type metal-oxide-semiconductor (NMOS). In an aspect, the first voltage regulator is coupled to the second voltage regulator.

Abstract: According to one embodiment, a semiconductor memory device includes: a first insulating layer provided between first and second interconnection layers; a first semiconductor layer provided between the first interconnection layer and the first insulating layer; a second semiconductor layer provided between the second interconnection layer and the first insulating layer; a first charge storage layer provided between the first interconnection layer and the first semiconductor layer; a second charge storage layer provided between the second interconnection layer and the second semiconductor layer; and a second insulating layer provided between the first interconnection layer and the second interconnection layer, between the first semiconductor layer and the second semiconductor layer, and between the first charge storage layer and the second charge storage layer.

Abstract: A method for forming a semiconductor memory device is provided. The method includes forming a sacrificial via in a dielectric layer over a substrate, forming a first active layer over the dielectric layer, forming an insulating layer over the first active layer, and forming a second active layer over the insulating layer. The method also includes forming a trench through the second active layer, the insulating layer and the first active layer and corresponding to the sacrificial via, removing the sacrificial via to form a via hole in the dielectric layer, and filling the trench and the via hole with a conductive material.

Abstract: A semiconductor device includes a first stacked body comprising first conductive layers and first insulating layers interposed therebetween, a first columnar portion comprising a first semiconductor layer extending in the first stacked body in the first direction and a first memory layer between the first semiconductor layer and the first conductive layers, a second stacked body comprising second conductive layers and second insulating layers interposed therebetween, and a second columnar portion comprising a second semiconductor layer extending in the second stacked body in the first direction and a second memory layer between the second semiconductor layer and the second conductive layers. The first columnar portion has a first diameter, and the second columnar portion has a second diameter, and each of the plurality of first conductive layers has a first film thickness, and each of the plurality of second conductive layers has a second film thickness.

Abstract: An electrically erasable programmable nonvolatile memory cell includes a semiconductor substrate having a first substrate region and a trench region apart from the first substrate region in a lateral direction, a channel region between the first substrate region and the bottom portion of the trench region, an electrically conductive control gate insulated from and disposed over the first channel portion, an electrically conductive floating gate insulated from the bottom and sidewall portions of the trench region, an insulation region disposed over the second channel portion between the control gate and the second floating gate portion, an electrically conductive source line insulated from the floating gate and electrically connected to the trench region of the substrate, and an electrically conductive erase gate insulated from and disposed over a tip of the floating gate.

Abstract: Technologies relating to crossbar array circuits with parallel grounding lines are disclosed. An example crossbar array circuit includes: a word line; a bit line; a first selector line; a grounding line; a first transistor including a first source terminal, a first drain terminal, a first gate terminal, and a first body terminal; and an RRAM device connected in series with the first transistor. The grounding line is connected to the first body terminal and is grounded and the grounding line parallel to the bit line. The first selector line is connected to the first gate terminal. In some implementations, the RRAM device is connected between the first transistor via the first drain terminal and the word line, and the first source terminal is connected to the bit line.

Abstract: According to one embodiment, a memory device includes first to third interconnects, memory cells, and selectors. The first to third interconnects are provided along first to third directions, respectively. The memory cells includes variable resistance layers formed on two side surfaces, facing each other in the first direction, of the third interconnects. The selectors couple the third interconnects with the first interconnects. One of the selectors includes a semiconductor layer provided between associated one of the third interconnects and associated one of the first interconnects, and gates formed on two side surfaces of the semiconductor layer facing each other in the first direction with gate insulating films interposed therebetween.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, and memory stack structures extending through the alternating stack. Each of the memory stack structures contains a memory film and a vertical semiconductor channel. At least one of the electrically conductive layers contains a first conductive material portion having a respective inner sidewall that contacts a respective one of the memory films at a vertical interface, and a second conductive material portion that has a different composition from the first conductive material portion, and contacting the first electrically conductive material portion. The first conductive material portion has a lower work function than the second conductive material portion.

Abstract: A semiconductor radiation monitor is provided that includes a charge storage region composed of a dielectric material nanosheet, such as, for example an epitaxial oxide nanosheet, which is sandwiched between a top semiconductor nanosheet and a bottom semiconductor nanosheet. A functional gate structure is located above the top semiconductor nanosheet and beneath the bottom semiconductor nanosheet.

Abstract: A memory device includes a semiconductor substrate, a select gate stack, a main gate, a charge trapping layer, and a spacer. The a select gate stack is over the semiconductor substrate. The main gate is over the semiconductor substrate. The charge trapping layer has a first portion between the main gate and the semiconductor substrate. The spacer is on a sidewall of the main gate. At least a portion of the main gate is between the spacer and the select gate stack, and a lowermost surface of the spacer is above a lowermost surface of the main gate.

Abstract: A memory cell comprises, in the following order, channel material, a charge-passage structure, programmable material, a charge-blocking region, and a control gate. The charge-passage structure comprises a first material closest to the channel material, a third material furthest from the channel material, and a second material between the first material and the third material. The first and third materials comprise SiO2. The second material has a thickness of 0.4 nanometer to 5.0 nanometers and comprises SiOx, where “x” is less than 2.0 and greater than 0. Other embodiments are disclosed.

Abstract: A radio frequency (RF) switch includes a heating element and a thermally resistive material adjacent to sides of the heating element. A thermally conductive and electrically insulating material is situated on top of the heating element. A phase-change material (PCM) is situated over the thermally conductive and electrically insulating material. The PCM has an active segment overlying the thermally conductive and electrically insulating material, and passive segments underlying input/output contacts of the RF switch. The RF switch may include a bulk substrate heat spreader, a silicon-on-insulator (SOI) handle wafer heat spreader, or an SOI top semiconductor heat spreader under the heating element.

Abstract: A semiconductor memory device according to embodiments described herein, includes a first stacked body, a second stacked body, a first memory hole, a second memory hole, and a joint. In the first stacked body, a plurality of first conductive layers and a plurality of first insulating layers are alternately stacked. The second stacked body is disposed above the first stacked body, and a plurality of second conductive layers and a plurality of second insulating layers are alternately stacked therein. The first memory hole extends in the first stacked body in a first direction that is a stacking direction of the first stacked body. The second memory hole extends in the second stacked body in the first direction. The joint communicates the first memory hole and the second memory hole. The joint includes an inner wall surface and a sidewall insulating layer. The inner wall surface has a plane continuous with the inner wall of the first memory hole.

Abstract: A semiconductor storage device of an embodiment includes: a stacked body in which a plurality of conductive layers are stacked with an insulating layer interposed therebetween, the stacked body having a memory portion in which a plurality of memory cells are disposed and a stepped portion in which ends of the plurality of conductive layers form a step shape; and a conductive portion which extends in the memory portion in a stacking direction of the stacked body inside the plurality of conductive layers from an uppermost conductive layer among the plurality of conductive layers, extends in the stepped portion in the stacking direction of the stacked body inside at least some layers among the plurality of conductive layers, and extends from the memory portion to the stepped portion in a direction intersecting the stacking direction of the stacked body. A height of the conductive portion in the stepped portion is lower than a height of the conductive portion in the memory portion.

Abstract: After the step of polishing, a part of each of each gate electrode is removed such that the upper surface of each gate electrode is located closer than the damaged region formed in the gate insulating film located between the gate electrodes to the main surface of the semiconductor substrate in cross-section view. Thus, it is possible to suppress the occurrence of a short-circuit defect during the operation of the semiconductor device.

Abstract: According to one embodiment, a semiconductor storage device includes: a first stacked body in which a plurality of conductive layers are stacked via a first insulating layer, the first stacked body having a first stepped portion and a second stepped portion in which end portions of the plurality of conductive layers are formed in a step shape in a lower layer; a second stacked body in which a plurality of second insulating layers are stacked via a third insulating layer, the second stacked body having a third stepped portion in which end portions of the plurality of second insulating layers in an identical level as the conductive layers forming the first stepped portion are formed in a step shape. The first stepped portion and the third stepped portion oppose each other, and the second stepped portion and the third stepped portion overlap each other at least partially in a top view.

Abstract: Techniques are disclosed for writing, programming, holding, maintaining, sampling, sensing, reading and/or determining a data state of a memory cell of a memory cell array, such as a memory cell array having a plurality of memory cells each comprising an electrically floating body transistor. In one aspect, the techniques are directed to controlling and/or operating a semiconductor memory cell having an electrically floating body transistor in which an electrical charge is stored in the body region of the electrically floating body transistor. The techniques may employ bipolar transistor currents to control, write and/or read a data state in such a memory cell. In this regard, the techniques may employ a bipolar transistor current to control, write and/or read a data state in/of the electrically floating body transistor of the memory cell.

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A memory opening is formed through the alternating stack. A memory film including a silicon nitride layer and a tunneling dielectric layer is formed in the memory opening, and an opening is formed through the memory film. A chemical oxide layer is formed on a physically exposed surface of an underlying semiconductor material portion. A silicon nitride ring can be formed by selectively growing a silicon nitride material from an annular silicon nitride layer portion of the silicon nitride layer while suppressing deposition of the silicon nitride material on the tunneling dielectric layer and on the chemical oxide layer. A vertical semiconductor channel can be formed by depositing a continuous semiconductor material layer on the underlying semiconductor material portion and the tunneling dielectric layer and on the silicon nitride ring.

Abstract: Methods and devices are described herein for random cut patterning. A first metal line and a second metal line are formed within a cell of a substrate and extend in a vertical direction. A third metal line and a fourth metal line are formed within the cell and are perpendicular to the first metal line and the second metal line, respectively. A first circular region at one end of the first metal line is formed using a first patterning technique and a second circular region at one end of the second metal line is formed using a second patterning technique. The first circular region is laterally extended using a second patterning technique to form the third metal line and the second circular region is laterally extended using the second patterning technique to form the fourth metal line.

Abstract: A panel is provided, including a first conductive pattern and a second conductive pattern. The first conductive pattern includes a first portion and a second portion; the second conductive pattern connects the first portion to the second portion, and an insulation pattern substantially covering a side surface of the second conductive pattern. The insulation pattern is formed by thermally treating a mask pattern of an insulation material. A horizontal distance between an outer side surface of the insulation pattern and an inner side surface adjacent to the second conductive pattern is less than 3 micrometers.

Abstract: A memory device includes a conductive strip stack structure having conductive strips and insulating layers stacked in a staggered manner and a channel opening passing through the conductive strips and the insulating layer; a memory layer disposed in the channel opening and overlying the conductive strips; a channel layer overlying the memory layer; a semiconductor pad extending upwards from a bottom of the channel opening beyond an upper surface of a bottom conductive strip, in contact with the channel layer, and electrically isolated from the conductive strips; wherein the channel layer includes a first portion having a first doping concentration and a second portion having a second doping concentration disposed on the first portion.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a plurality of U-shaped memory strings, each of the plurality of U-shaped memory strings including a first columnar body, a second columnar body, and a conductive connection body. The conductive connection body connects the first columnar body and the second columnar body. A plurality of first memory cells are connected in series in the first columnar body and are composed of a plurality of first conductive layers, a first inter-gate insulating film, a plurality of first floating electrodes, a first tunnel insulating film, and a first memory channel layer. The plurality of first floating electrodes are separated from the plurality of first conductive layers by the first inter-gate insulating film. A plurality of second memory cells are connected in series in the second columnar body, similarly to the plurality of first memory cells.

Abstract: A semiconductor device includes a stack structure including alternately stacked interlayer insulating layers and electrode patterns. The semiconductor device also includes a plurality of contact plugs connected to the electrode patterns. The semiconductor device further includes a supporting structure penetrating the stack structure between two adjacent contact plugs of the plurality of contact plugs, wherein the supporting structure has a cross section extending in a zigzag shape.

Abstract: Some embodiments include an integrated structure having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include primary regions of a first vertical thickness, and terminal projections of a second vertical thickness which is greater than the first vertical thickness. Charge-blocking material is adjacent the terminal projections. Charge-storage material is adjacent the charge-blocking material. Gate-dielectric material is adjacent the charge-storage material. Channel material is adjacent the gate-dielectric material. Some embodiments include NAND memory arrays. Some embodiments include methods of forming integrated structures.

Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

Abstract: A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips located over a substrate and laterally spaced apart among one another by line trenches. The line trenches laterally extend along a first horizontal direction and are spaced apart along a second horizontal direction. Each line trench fill structure includes a laterally undulating dielectric rail having a laterally undulating width along the second horizontal direction and extending along the first horizontal direction and a row of memory stack structures located at neck regions of the laterally undulating dielectric rail.

Abstract: A memory device that includes source and drain regions formed in a semiconductor substrate, with a first channel region of the substrate extending there between. A floating gate is disposed over and insulated from the channel region, wherein the conductivity of the channel region is solely controlled by the floating gate. A control gate is disposed over and insulated from the floating gate. An erase gate is disposed over and insulated from the source region, wherein the erase gate includes a notch that faces and is insulated from an edge of the floating gate. Logic devices are formed on the same substrate. Each logic device has source and drain regions with a channel region extending there between, and a logic gate disposed over and controlling the logic device's channel region.