Variable Threshold (e.g., Floating Gate Memory Device) Patents (Class 257/314)
- With additional contacted control electrode (Class 257/316)
- With irregularities on electrode to facilitate charging or discharging of floating electrode (Class 257/317)
- Additional control electrode is doped region in semiconductor substrate (Class 257/318)
- Plural additional contacted control electrodes (Class 257/319)
- With thin insulator region for charging or discharging floating electrode by quantum mechanical tunneling (Class 257/321)
- With charging or discharging by control voltage applied to source or drain region (e.g., by avalanche breakdown of drain junction) (Class 257/322)
- With means to facilitate light erasure (Class 257/323)
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Patent number: 10879252Abstract: A pair of memory cells that includes first and second spaced apart trenches formed into the upper surface of a semiconductor substrate, and first and second floating gates disposed in the first and second trenches. First and second word line gates disposed over and insulated from a portion of the upper surface that is adjacent to the first and second floating gates respectively. A source region is formed in the substrate laterally between the first and second floating gates. First and second channel regions extend from the source region, under the first and second trenches respectively, along side walls of the first and second trenches respectively, and along portions of the upper surface disposed under the first and second word line gates respectively. The first and second trenches only contain the first and second floating gates and insulation material respectively.Type: GrantFiled: December 3, 2018Date of Patent: December 29, 2020Assignee: Silicon Storage Technology, Inc.Inventors: Leo Xing, Andy Liu, Xian Liu, Chunming Wang, Melvin Diao, Nhan Do
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Patent number: 10872980Abstract: A semiconductor device includes a substrate, an inter-layer dielectric layer, a contact plug, and a contact hole liner. The substrate has a source/drain region. The inter-layer dielectric layer is over the substrate and has a contact hole therein. The contact plug is electrically connected to the source/drain region through the contact hole of the inter-layer dielectric layer. The contact hole liner extends between the contact plug and a sidewall of a first portion of the contact hole. The contact hole liner terminates prior to reaching a second portion of the contact hole. The first portion is between the second portion and the source/drain region.Type: GrantFiled: April 25, 2017Date of Patent: December 22, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Che Tsai, Min-Yann Hsieh, Hua-Feng Chen, Kuo-Hua Pan
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Patent number: 10872899Abstract: A three-dimensional memory device includes a plurality of alternating stacks of insulating layers and electrically conductive layers located over a substrate, clusters of memory stack structures vertically extending through a respective one of the alternating stacks, and bit lines electrically connected to an upper end of a respective subset of the vertical semiconductor channels. In one embodiment, a subset of the bit lines can include a respective multi-level structure. Each multi-level structure includes bit-line-level bit line segments and an interconnection line segment located at a different level from the bit-line-level bit line segments. In another embodiment, groups of alternating stacks can be alternately indented along a horizontal direction perpendicular to the bit lines to provide dielectric material portions located in lateral indentation regions.Type: GrantFiled: May 7, 2019Date of Patent: December 22, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Jee-Yeon Kim, Kwang-Ho Kim, Fumiaki Toyama
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Patent number: 10872904Abstract: Provided herein is a semiconductor device including N stacked groups (where N is a natural number greater than or equal to two) sequentially stacked over a substrate, each stacked group including interlayer insulating films and conductive patterns alternately stacked, and N concave portions each having stepped sidewalls formed in the interlayer insulating films and the conductive patterns of the stacked groups, the N concave portions each having stepped sidewalls being aligned in a first direction.Type: GrantFiled: January 8, 2020Date of Patent: December 22, 2020Assignee: SK hynix Inc.Inventor: Nam Jae Lee
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Patent number: 10868035Abstract: A semiconductor device includes a stack structure, a channel layer passing through the stack structure, a memory layer enclosing the channel layer and including first and second openings which expose the channel layer, a well plate coupled to the channel layer through the first opening, and a source plate coupled to the channel layer through the second opening.Type: GrantFiled: March 20, 2019Date of Patent: December 15, 2020Assignee: SK hynix Inc.Inventor: In Su Park
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Patent number: 10868038Abstract: A memory device may include multiple channel regions extending in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate to be adjacent at least a portion of the plurality of channel regions, an interlayer insulating layer disposed on the plurality of gate electrode layers, a plurality of cell contact plugs passing through the interlayer insulating layer. Each of the plurality of cell contacts is connected to each of the plurality of gate electrode layers. A vertical insulating layer extends from the interlayer insulating layer disposed between the plurality of channel regions and the plurality of cell contact plugs and has a portion surrounded by at least one of the plurality of gate electrode layers.Type: GrantFiled: July 9, 2019Date of Patent: December 15, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seok Cheon Baek, Young Woo Kim, Dong Sik Lee, Min Yong Lee, Woong Seop Lee
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Patent number: 10868248Abstract: Methods, systems, and devices for tapered memory cell profiles are described. A tapered profile memory cell may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a bottom surface and a top surface opposite the bottom surface. In some cases, the self-selecting memory component may taper from the bottom surface to the top surface. In other examples, the self-selecting memory component may taper from the top surface to the bottom surface. The top surface of the self-selecting memory component may be coupled to a top electrode, and the bottom surface of the self-selecting memory component may be coupled to a bottom electrode.Type: GrantFiled: August 7, 2019Date of Patent: December 15, 2020Assignee: Micron Technology, Inc.Inventors: Agostino Pirovano, Kolya Yastrebenetsky, Fabio Pellizzer
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Patent number: 10861869Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Each of the memory stack structures includes respective charge storage elements and a respective vertical semiconductor channel contacting an inner sidewall of the respective charge storage elements. The sacrificial material layers are replaced with electrically conductive layers. A polycrystalline aluminum oxide blocking dielectric layer is provided between each charge storage element and a neighboring one of the electrically conductive layers. The polycrystalline aluminum oxide blocking dielectric layer is formed by: depositing an amorphous aluminum oxide layer, converting the amorphous aluminum oxide layer into an in-process polycrystalline aluminum oxide blocking dielectric layer, and by thinning the in-process polycrystalline aluminum oxide blocking dielectric layer.Type: GrantFiled: January 8, 2019Date of Patent: December 8, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Ryo Nakamura, Yu Ueda, Tatsuya Hinoue, Shigehisa Inoue, Genta Mizuno, Masanori Tsutsumi
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Patent number: 10854633Abstract: According to an embodiment, a semiconductor memory device comprises: a stacked body that includes a plurality of control gate electrodes stacked above a substrate; a memory columnar body that extends in a first direction above the substrate and configures a memory string along with the stacked body; and a source contact that extends in the first direction and is electrically connected to one end of the memory string. Moreover, this source contact is adjacent to the stacked body via a spacer insulating layer. Furthermore, a spacer protective layer including a nitride or a metal oxide is provided between these source contact and spacer insulating layer.Type: GrantFiled: March 11, 2020Date of Patent: December 1, 2020Assignee: Toshiba Memory CorporationInventor: Takeo Mori
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Patent number: 10854511Abstract: Methods for forming 3D-NAND devices comprising recessing a poly-Si layer to a depth below a spaced oxide layer. A liner is formed on the spaced oxide layer and not on the recessed poly-Si layer. A metal layer is deposited in the gaps on the liner to form wordlines.Type: GrantFiled: June 5, 2018Date of Patent: December 1, 2020Assignee: Applied Materials, Inc.Inventors: Yihong Chen, Yong Wu, Chia Cheng Chin, Xinliang Lu, Srinivas Gandikota, Ziqing Duan, Abhijit Basu Mallick
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Patent number: 10847537Abstract: A three-dimensional semiconductor memory device includes: gate electrodes and mold insulation layers alternately stacked on a substrate; a channel layer passing through the gate electrodes and the mold insulation layers; and a gate dielectric layer between the gate electrodes and the channel layer. The gate dielectric layer and the channel layer may be in an upper portion of the substrate and may be bent at a first angle and extend under the mold insulation layers in the upper portion of the substrate.Type: GrantFiled: January 30, 2019Date of Patent: November 24, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Young Hwan Son, Seo Goo Kang, Shin Hwan Kang
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Patent number: 10840125Abstract: The present invention relates to a memory structure and a method for forming the same. The memory structure includes a first substrate and an isolation structure. The first substrate includes a substrate layer and a storage layer. The substrate layer has a first surface and a second surface opposite to the first surface. The storage layer is disposed on the first surface of the substrate layer. The substrate layer has a doped well. The isolation structure penetrates through the substrate layer and is disposed at an edge of the doped well for isolating the doped well and the peripheral substrate layer. The memory structure can avoid current leakage between the doped well and the substrate layer so as to improve the performance.Type: GrantFiled: September 10, 2018Date of Patent: November 17, 2020Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Jin Wen Dong, Jun Chen, Zhiliang Xia, Zi Qun Hua, Jifeng Zhu, He Chen
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Patent number: 10840376Abstract: The semiconductor structure includes a semiconductor substrate having a first region and a second region being adjacent to the first region; first fins formed on the semiconductor substrate within the first region; a first shallow trench isolation (STI) feature disposed on the semiconductor substrate within the second region; and a first gate stack that includes a first segment disposed directly on the first fins within the first region and a second segment extending to the first STI feature within the second region. The second segment of the first gate stack includes a low resistance metal (LRM) layer, a first tantalum titanium nitride layer, a titanium aluminum nitride layer, and a second tantalum titanium nitride layer stacked in sequence. The first segment of the first gate stack within the first region is free of the LRM layer.Type: GrantFiled: January 31, 2018Date of Patent: November 17, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Max Liu, Yen-Ming Peng, Wei-Shuo Ho
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Patent number: 10838652Abstract: A memory device with memory cells each including source and drain regions with a channel region there between, a floating gate over a first channel region portion, a select gate over a second channel region portion, a control gate over the floating gate, and an erase gate over the source region. Control circuitry is configured to, for one of the memory cells, apply a first pulse of programming voltages that includes a first voltage applied to the control gate, perform a read operation that includes detecting currents through the channel region for different control gate voltages to determine a target control gate voltage using the detected currents that corresponds to a target current through the channel region, and apply a second pulse of programming voltages that includes a second voltage applied to the control gate that is determined from the first voltage, a nominal read voltage and the target voltage.Type: GrantFiled: December 12, 2018Date of Patent: November 17, 2020Assignee: Silicon Storage Technology, Inc.Inventors: Viktor Markov, Alexander Kotov
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Patent number: 10839900Abstract: A cross-point array and method for forming the same are provided. The cross-point array includes an array of Resistive Processing Unit (RPU) devices having rows and columns interconnected at cross-points. The cross-point array further includes a plurality of series resistors. Each respective one of the plurality of series resistors has a first end connected in series with a respective one of the RPU devices and a second end connected to a respective one of the cross-points to compensate for a parasitic voltage drop associated with each of the RPU devices.Type: GrantFiled: June 12, 2019Date of Patent: November 17, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Seyoung Kim, Tayfun Gokmen
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Patent number: 10833087Abstract: A semiconductor device comprises a memory storage component and a transistor in operable communication with the memory storage element. The transistor comprises a source region, a drain region, a gate electrode between the source region and the drain region, a charge trapping material surrounding at least an upper portion of the gate electrode, and an oxide material on sides of the charge trapping material. Related systems and methods are also disclosed.Type: GrantFiled: August 21, 2018Date of Patent: November 10, 2020Assignee: Micron Technology, Inc.Inventors: Fredrick D. Fishburn, Haitao Liu, Soichi Sugiura, Oscar O. Enomoto, Mark A. Zaleski, Keisuke Hirofuji, Makoto Morino, Ichiro Abe, Yoshiyuki Nanjo, Atsuko Otsuka
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Patent number: 10833101Abstract: A vertically alternating sequence of multi-fingered silicon-germanium layers and multi-fingered silicon layers is formed over a substrate. The multi-fingered silicon-germanium layers include silicon-germanium wires, and the multi-fingered silicon layers include silicon wires. Tubular memory films and multi-fingered gate electrodes are formed. Each gate electrode includes a respective gate electrode bar which overlies the silicon wires and a respective set of vertically-extending gate electrode fingers which is adjoined to a bottom portion of the respective gate electrode bar and spaced apart by the silicon wires. The multi-fingered silicon-germanium layers are removed selective to multi-fingered silicon layers. First active regions are formed at an end portion of each of the silicon wires. Second active regions are formed on silicon plate portions of the multi-fingered silicon layers.Type: GrantFiled: March 4, 2019Date of Patent: November 10, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Shigeki Shimomura, Satoru Mayuzumi, Hiroyuki Ogawa
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Patent number: 10833078Abstract: Aspects of the disclosure provide a semiconductor apparatus that comprises a first field-effect transistor (FET) formed on a substrate and comprising a first gate, a second FET stacked on the first FET along a direction substantially perpendicular to the substrate and comprising a second gate. The semiconductor apparatus also comprises a first routing track and a second routing track electrically isolated from the first routing track. Each of the first and second routing tracks is provided on a routing plane stacked on the second FET along said direction. The semiconductor apparatus also comprises a first conductive trace configured to conductively couple the first gate of the first FET to the first routing track, and a second conductive trace configured to conductively couple the second gate of the second FET to the second routing track.Type: GrantFiled: November 30, 2018Date of Patent: November 10, 2020Assignee: Tokyo Electron LimitedInventors: Jeffrey Smith, Anton J. deVilliers, Kandabara N. Tapily, Subhadeep Kal, Gerrit J. Leusink
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Patent number: 10833179Abstract: A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.Type: GrantFiled: September 19, 2019Date of Patent: November 10, 2020Assignee: Silicon Storage Technology, Inc.Inventors: Chunming Wang, Leo Xing, Andy Liu, Melvin Diao, Xian Liu, Nhan Do
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Patent number: 10833178Abstract: A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.Type: GrantFiled: September 19, 2019Date of Patent: November 10, 2020Assignee: Silicon Storage Technology, Inc.Inventors: Chunming Wang, Leo Xing, Andy Liu, Melvin Diao, Xian Liu, Nhan Do
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Patent number: 10818728Abstract: A three-dimensional semiconductor device is provided as follows. A substrate includes a contact region, a dummy region, and a cell array region. A stack structure includes electrodes vertically stacked on the substrate. The electrodes are stacked to have a first stepwise structure on the contact region and a second stepwise structure in the dummy region. Ends of at least two adjacent electrodes in the second stepwise structure have first sidewalls vertically aligned so that horizontal positions of the first sidewalls are substantially the same.Type: GrantFiled: May 13, 2020Date of Patent: October 27, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Joyoung Park, Seok-Won Lee, Seongjun Seo
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Patent number: 10818690Abstract: A semiconductor device includes conductive patterns stacked and spaced apart from each other in a first direction to form a stepped structure, a stepped insulating layer overlapping the stepped structure, contact plugs extending through the stepped insulating layer in the first direction to contact respective contact portions of the conductive patterns, and barrier patterns disposed on sidewalls of the stepped insulating layer.Type: GrantFiled: February 26, 2019Date of Patent: October 27, 2020Assignee: SK hynix Inc.Inventor: Dae Sung Eom
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Patent number: 10818594Abstract: There is provided a semiconductor device including a memory region and a logic region. The memory region includes a transistor (memory transistor) that stores information by accumulating charge in a sidewall insulating film. The width of the sidewall insulating film of the memory transistor included in the memory region is made larger than the width of a sidewall insulating film of a transistor (logic transistor) included in the logic region.Type: GrantFiled: May 10, 2019Date of Patent: October 27, 2020Assignee: UNITED SEMICONDUCTOR JAPAN CO., LTD.Inventors: Taiji Ema, Makoto Yasuda, Kazuhiro Mizutani
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Patent number: 10811495Abstract: Fabrication of a semiconductor structure includes forming a set of two or more fins on a source/drain region formed on a substrate. A first mask layer and a second mask layer are formed on each fin. A spacer layer is formed on the source/drain region and between each fin, and a dielectric layer is formed on the spacer layer and along an exterior of each fin. A plurality of gate metal portions is created each having a thickness about equal to a target thickness. The first mask layer and an exposed portion of the dielectric layer are removed from each fin. An interlayer dielectric is deposited on the semiconductor structure. Portions of the interlayer dielectric and the gate metal are removed to a top of the second mask layer. The gate metal portions are each recessed to substantially the same depth.Type: GrantFiled: October 25, 2017Date of Patent: October 20, 2020Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
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Patent number: 10811387Abstract: Semiconductor device packages include a stack of semiconductor memory devices positioned over an interposer substrate, a controller element, and a redistribution substrate positioned laterally adjacent to the controller element. At least a portion of the controller element is positioned directly between the stack and the interposer substrate. The controller element is operatively connected to the semiconductor memory devices of the stack through the redistribution substrate and the interposer substrate. Methods of manufacturing a semiconductor device package include positioning a redistribution substrate laterally adjacent to a controller element and attaching the redistribution substrate and the controller element to an interposer substrate. A stack of semiconductor memory devices is positioned over the controller element and the redistribution substrate.Type: GrantFiled: November 19, 2018Date of Patent: October 20, 2020Assignee: Micron Technology, Inc.Inventors: Seng Kim Dalson Ye, Hong Wan Ng
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Patent number: 10811504Abstract: An exemplary method includes forming a common source region in a substrate, and forming an isolation feature over the common source region. The common source region is disposed between the substrate and the isolation feature. The common source region and the isolation feature span a plurality of active regions of the substrate. A gate, such as an erase gate, may be formed after forming the common source region. In some implementations, the common source region is formed by etching the substrate to form a saw-tooth shaped recess region (or a U-shaped recess region) and performing an ion implantation process to form a doped region in a portion of the saw-tooth shaped recess region (or the U-shaped recess region), such that the common source region has a sawtooth profile (or a U-shaped profile).Type: GrantFiled: October 18, 2019Date of Patent: October 20, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming Chyi Liu, Chang-Ming Wu, Shih-Chang Liu, Wei Cheng Wu, Harry-Hak-Lay Chuang, Chia-Shiung Tsai, Ru-Liang Lee
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Patent number: 10804284Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures vertically extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and a contact well set that includes contact wells extending through a respective upper region of the alternating stack. Each of the contact wells contains first stepped surfaces which have a stepwise descending vertical profile along a first horizontal direction and second stepped surfaces which have a stepwise descending vertical profile along a second horizontal direction which is perpendicular to the first horizontal direction.Type: GrantFiled: April 11, 2018Date of Patent: October 13, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Yasushi Ishii, Jun Akaiwa, Kiyokazu Shishido, Hiroyuki Ogawa
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Patent number: 10804363Abstract: Disclosed are three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor memory device comprises a substrate that includes a cell array region and a connection region, an electrode structure that includes a plurality of electrodes and a plurality of dielectric layers alternately stacked on the substrate and has a stepwise structure on the connection region, an etch stop pattern that covers the stepwise structure of the electrode structure. The electrode structure and the etch stop pattern extend in a first direction when viewed in plan. The electrode structure has a first width in a second direction intersecting the first direction. The etch stop pattern has a second width in the second direction. The second width is less than the first direction.Type: GrantFiled: June 19, 2019Date of Patent: October 13, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Min Hwang, Joon-Sung Lim, Jiyoung Kim, Jiwon Kim, Woosung Yang
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Patent number: 10804282Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate, and memory stack structures are formed through the alternating stack. A backside trench is formed through the alternating stack, and backside recesses are formed by removing the sacrificial material layers. An undoped aluminum oxide backside blocking dielectric layer is formed in the backside recesses and on sidewalls the backside trench. A portion of the undoped aluminum oxide backside blocking dielectric layer located at an upper end of the backside trench is converted into a carbon-doped aluminum oxide layer. An electrically conductive material is deposited in the backside recesses and at peripheral regions of the backside trench. The electrically conductive material at the peripheral regions of the backside trench is removed by an etch process, with the carbon-doped aluminum oxide layer providing etch resistivity during the etch process.Type: GrantFiled: February 11, 2019Date of Patent: October 13, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Ashish Baraskar, Fei Zhou, Ching-Huang Lu, Raghuveer S. Makala
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Patent number: 10797142Abstract: A memory cell is formed on a semiconductor substrate having an upper surface with a plurality of upwardly extending fins. First and second fins extend in one direction, and a third fin extends in an orthogonal direction. Spaced apart source and drain regions are formed in each of the first and second fins, defining a channel region extending there between in each of the first and second fins. The source regions are disposed at intersections between the third fin and the first and second fins. A floating gate is disposed laterally between the first and second fins, and laterally adjacent to the third fin, and extends along first portions of the channel regions. A word line gate extends along second portions of the channel regions. A control gate is disposed over the floating gate. An erase gate is disposed over the source regions and the floating gate.Type: GrantFiled: December 3, 2018Date of Patent: October 6, 2020Assignee: Silicon Storage Technology, Inc.Inventors: Serguei Jourba, Catherine Decobert, Feng Zhou, Jinho Kim, Xian Liu, Nhan Do
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Patent number: 10797068Abstract: Provided are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic system adopting the same. The semiconductor device includes a semiconductor pattern, which is disposed on a semiconductor substrate and has an opening. The semiconductor pattern includes a first impurity region having a first conductivity type and a second impurity region having a second conductivity type different from the first conductivity type. A peripheral transistor is disposed between the semiconductor substrate and the semiconductor pattern. A first peripheral interconnection structure is disposed between the semiconductor substrate and the semiconductor pattern. The first peripheral interconnection structure is electrically connected to the peripheral transistor. Cell gate conductive patterns are disposed on the semiconductor pattern. Cell vertical structures are disposed to pass through the cell gate conductive patterns and to be connected to the semiconductor pattern.Type: GrantFiled: July 27, 2018Date of Patent: October 6, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Joon-Sung Lim, Jang-Gn Yun, Jaesun Yun
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Patent number: 10797070Abstract: An alternating stack of insulating layers and spacer material layers is formed over a source-level sacrificial layer overlying a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory stack structures including a respective vertical semiconductor channel and a respective memory film are formed through the alternating stack. A source-level cavity is formed by removing the source-level sacrificial layer. Semiconductor pillar structures may be used to provide mechanical support to the alternating stack during formation of the source-level cavity. A source-level semiconductor material layer can be formed in the source-level cavity. The source-level semiconductor material layer adjoins bottom end portions of the vertical semiconductor channels and laterally surrounds the semiconductor pillar structures.Type: GrantFiled: January 7, 2019Date of Patent: October 6, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Mitsuteru Mushiga, Kenji Sugiura, Akio Nishida
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Patent number: 10790027Abstract: A memory device includes a plurality of data lines, a common source, and control logic. The control logic is configured to implement a seed operation by biasing each of the plurality of data lines to a first voltage level with the common source biased to a second voltage level lower than the first voltage level. With each data line biased to the first voltage level, the control logic is configured to float each data line and bias the common source to the first voltage level such that the bias of each data line is boosted above the first voltage level due to capacitive coupling between each data line and the common source.Type: GrantFiled: March 24, 2020Date of Patent: September 29, 2020Assignee: Micron Technology, Inc.Inventors: Violante Moschiano, Raffaele Bufano, Mirko Scapin, Andrea Giovanni-Xotta
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Patent number: 10790290Abstract: A 3D NAND storage device includes a plurality of layers containing doped semiconductor material interleaved with a plurality of layers of dielectric material. Each of the pillars forming the 3D NAND storage device includes a plurality of memory cells and a drain-end select gate (SGD). The pillars are separated by a hollow channel in which a plurality of film layers, including at least a lower film layer and an upper film layer have been deposited. The systems and methods described herein remove at least the upper film layer proximate the SGD while maintaining the film layers proximate the memory cells. Such an arrangement beneficially permits tailoring the film layers proximate the SGD prior to depositing the channel film layer in the hollow channel. The systems and methods described herein permit the deposition of a continuous channel film layer proximate both the memory cells and the SGD.Type: GrantFiled: September 29, 2017Date of Patent: September 29, 2020Assignee: Intel CorporationInventors: David A. Daycock, Purnima Narayanan, John Hopkins, Guoxing Duan, Barbara L. Casey, Christopher J. Larsen, Meng-Wei Kuo, Qian Tao
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Patent number: 10777575Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack, drain-select-level trenches that vertically extend through at least one drain-select-level electrically conductive layer and laterally extend along a first horizontal direction and divide each drain-select-level electrically conductive layer into multiple drain-select-level electrically conductive strips, and pairs of vertical conductive strips located within a respective one of the drain-select-level trenches. Each of the vertical conductive strips has a pair of vertical straight sidewalls that laterally extends along the first horizontal direction. Each drain-select-level electrode may have at least one drain-select-level electrically conductive layer and at least one vertical conductive strip.Type: GrantFiled: March 22, 2019Date of Patent: September 15, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Zhixin Cui, Kiyohiko Sakakibara, Yanli Zhang
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Patent number: 10777574Abstract: According to one embodiment, in a semiconductor device, a stacked body is disposed above a substrate. In the stacked body, a conductive film and an insulating layer are alternately disposed in a stacking direction. A semiconductor columnar member penetrates the stacked body in a stacking direction. An insulating film surrounds the semiconductor columnar member. The insulating film penetrates the stacked body in the stacking direction. A pattern is disposed at a position adjacent to or close to a region. The region includes a penetration plug. The penetration plug extends from a position same as or above an upper end of the stacked body to a position below a lower end of the stacked body in the stacking direction. The pattern has a quadrangular or disjoined quadrangular shape.Type: GrantFiled: March 12, 2019Date of Patent: September 15, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Masayuki Shishido, Tatsuya Fujishima, Nozomi Kido, Tomonori Kajino
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Patent number: 10770469Abstract: In a method of manufacturing a semiconductor device, the semiconductor device includes a non-volatile memory formed in a memory cell area and a ring structure area surrounding the memory cell area. In the method, a protrusion of a substrate is formed in the ring structure area. The protrusion protrudes from an isolation insulating layer. A high-k dielectric film is formed, thereby covering the protrusion and the isolation insulating layer. A poly silicon film is formed over the high-k dielectric film. The poly silicon film and the high-k dielectric film are patterned. Insulating layers are formed over the patterned poly silicon film and high-k dielectric film, thereby sealing the patterned high-k dielectric film.Type: GrantFiled: September 7, 2017Date of Patent: September 8, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Meng-Han Lin, Chih-Ren Hsieh, Chin Wen Chan
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Patent number: 10770538Abstract: A method of forming an electronic device includes forming an opening through a dielectric layer located over a first resistive layer, the first resistive layer having a first sheet resistance. A second resistive layer is deposited over the dielectric layer and into the opening. The second resistive layer has a second sheet resistance different from the first sheet resistance. A portion of the second resistive layer is removed, thereby forming first and second noncontiguous portions of the second resistive layer, wherein the second portion of the second resistive layer contacts the first resistive layer.Type: GrantFiled: May 10, 2018Date of Patent: September 8, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Christoph Andreas Othmar Dirnecker, Wolfgang Schwartz, Doug Weiser, Joel Martin Halbert, Joseph Anthony DeSantis, Karsten Jens Spinger
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Patent number: 10763271Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack. Each of the memory stack structures comprises a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. The electrically conductive layers include aluminum and silicon and provide low resistance electrically conductive paths as word lines of the three-dimensional memory device. The aluminum-based electrically conductive layers can provide low resistivity, low mechanical stress, and thermal stability for use as high performance word lines.Type: GrantFiled: June 27, 2018Date of Patent: September 1, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Peter Rabkin, Masaaki Higashitani, Jayavel Pachamuthu
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Patent number: 10763275Abstract: A method for forming a 3D NAND structure includes providing a semiconductor substrate; forming a control gate structure having a plurality of staircase-stacked layers, each layer has a first end and a second end; forming a dielectric layer covering the semiconductor substrate, and the control gate structure; forming a hard mask layer on the dielectric layer; patterning the hard mask layer to form a plurality of openings above corresponding second ends of the layers of the control gate structure; forming a photoresist layer on the hard mask layer; repeating a photoresist trimming process and a first etching process to sequentially expose the openings, and to form a plurality of holes with predetermined depths in the dielectric layer; performing a second etching process to etch the plurality of holes until surfaces of the second ends are exposed to form through holes; and forming metal vias in the through holes.Type: GrantFiled: June 13, 2017Date of Patent: September 1, 2020Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Huayong Hu, Lei Ye
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Patent number: 10748920Abstract: According to one embodiment, a semiconductor memory device includes a plurality of electrode films, a semiconductor member, a tunneling insulating film, a charge storage member, and a blocking insulating film. The plurality of electrode films are arranged to be separated from each other along a first direction. The semiconductor member extends in the first direction. The tunneling insulating film is provided between the semiconductor member and the electrode films. The charge storage member is provided between the tunneling insulating film and the electrode films. The blocking insulating film is provided between the charge storage member and the electrode films. The blocking insulating film includes a first film contacting the charge storage film and including carbon-containing silicon oxide, and a second film contacting the electrode films and including hafnium oxide or aluminum oxide.Type: GrantFiled: September 10, 2018Date of Patent: August 18, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventor: Keisuke Nakatsuka
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Patent number: 10748923Abstract: A vertical memory device includes gate electrodes on a substrate, a channel extending through the gate electrodes, and a contact plug extending through the gate electrodes. The gate electrodes are stacked in a first direction substantially vertical to an upper surface of the substrate and arranged to have a staircase shape including steps of which extension lengths in a second direction substantially parallel to the upper surface gradually increase from a lowermost level toward an uppermost level. A pad at an end portion of each of the gate electrodes in the second direction has a thickness greater than those of other portions thereof. The channel extends in the first direction. The contact plug extends in the first direction. The channel contacts the pad of a first gate electrode among the gate electrodes to be electrically connected thereto, and is electrically insulated from second gate electrodes among the gate electrodes.Type: GrantFiled: December 4, 2018Date of Patent: August 18, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Hwan Son, Kohji Kanamori, Shin-Hwan Kang, Young Jin Kwon
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Patent number: 10749042Abstract: A vertical memory device and a method of manufacturing such device are provided. The vertical memory device may include a plurality of gate electrode layers stacked in a cell region of a semiconductor substrate; a plurality of upper isolation insulating layers dividing an uppermost gate electrode layer among the plurality of gate electrode layers, extending in a first direction; a plurality of vertical holes arranged to have any two adjacent vertical holes to have a uniform distance from each other throughout the cell region and including a plurality of channel holes penetrating through the plurality of gate electrode layers disposed between the plurality of upper isolation insulating layers and a plurality of first support holes penetrating through the plurality of upper insulating layers; a plurality of channel structures disposed in the plurality of channel holes; and a plurality of first support structures disposed in the plurality of first support holes.Type: GrantFiled: May 1, 2019Date of Patent: August 18, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyuk Kim, Dae Hyun Jang, Seung Pil Chung, Sung II Cho
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Patent number: 10748894Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack, source regions located on, or in, the substrate, and at least one memory-side bonding pad electrically connected to the source regions. A logic die includes a power supply circuit configured to generate a supply voltage for the source regions, and at least one logic-side bonding pad electrically connected to the power supply circuit through a network of logic-side metal interconnect structures. The memory die is bonded to the logic die. The network of logic-side metal interconnect structures distributes source power from the power supply circuit over an entire area of the memory stack structures and transmits the source power to the memory die through bonded pairs of memory-side bonding pads and logic-side bonding pads.Type: GrantFiled: January 18, 2019Date of Patent: August 18, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Murshed Chowdhury, Kwang-Ho Kim, James Kai, Johann Alsmeier
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Patent number: 10748929Abstract: A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.Type: GrantFiled: January 10, 2020Date of Patent: August 18, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Changhyun Lee, Chanjin Park, Byoungkeun Son, Sung-Il Chang
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Patent number: 10748630Abstract: An artificial neural network device that utilizes analog neuromorphic memory that comprises one or more non-volatile memory arrays. The embodiments comprise improved mechanisms and algorithms for tuning the non-volatile memory arrays such that the floating gates of the memory cells can be quickly and accurately injected with the desired amount of charge to signify an analog value utilized as a weight by the artificial neural network.Type: GrantFiled: November 29, 2017Date of Patent: August 18, 2020Assignee: SILICON STORAGE TECHNOLOGY, INC.Inventors: Hieu Van Tran, Vipin Tiwari, Nhan Do, Steven Lemke, Santosh Hariharan, Stanley Hong
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Patent number: 10741678Abstract: In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase.Type: GrantFiled: October 30, 2017Date of Patent: August 11, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun-Chieh Lu, Carlos H. Diaz, Chih-Sheng Chang, Cheng-Yi Peng, Ling-Yen Yeh, Chien-Hsing Lee
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Patent number: 10741574Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure including conductive layers stacked on the substrate. Moreover, the semiconductor device includes a dummy structure penetrating a stepped region of the stack structure. A portion of the dummy structure includes a first segment and a second segment. The first segment extends in a first direction in a plane parallel to an upper surface of the substrate. The second segment protrudes from the first segment in a second direction, in the plane, that intersects the first direction.Type: GrantFiled: April 17, 2018Date of Patent: August 11, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Kwangyoung Jung, Jongwon Kim, Dongseog Eun, Joonhee Lee
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Patent number: 10741258Abstract: Memory having an array of memory cells and a controller for access of the array of memory cells that is configured to generate a data value indicative of a level of a property sensed from a data line while applying potentials to control gates of memory cells of more than one string of series-connected memory cells connected to that data line.Type: GrantFiled: July 18, 2019Date of Patent: August 11, 2020Assignee: Micron Technology, Inc.Inventors: Tommaso Vali, Kenneth J. Eldredge, Frankie F. Roohparvar, Luca De Santis
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Patent number: 10734404Abstract: A semiconductor device includes a cell structure; n first pad structures formed on one side of the cell structure and each configured to have a step form in which 2n layers form one stage; and n second pad structures formed on the other side of the cell structure each configured to have a step form in which 2n layers form one stage, wherein n is a natural number of 1 or higher, and the first pad structures and the second pad structures have asymmetrical step forms having different heights.Type: GrantFiled: July 17, 2018Date of Patent: August 4, 2020Assignee: SK hynix Inc.Inventors: Ki Hong Lee, Seung Ho Pyi, Sung Ik Moon