Abstract: A non-volatile random access memory (NVRAM) structure comprising an injector element in a single crystal silicon substrate; an insulator layer over the substrate; a silicon-on-insulator (SOI) layer over the insulator layer; and a sensing element in the SOI layer overlying the injector element. The NVRAM structure may further comprise a gate above the SOI layer, a floating gate in the insulator layer, or both.

Abstract: The provision of an isolation gate connecting unassociated active areas of adjacent transistors formed in a semiconductor substrate provides effective isolation of the adjacent transistors with no additional process steps required. The isolation gate is tied to a reference to ensure that a channel between the unassociated active areas is not formed, and effective isolation is provided. The adjacent transistors are cross coupled to form sense amplifiers for dynamic random access memory devices.

Abstract: A semiconductor memory device comprising a source and a drain formed in a P-type semiconductor substrate and a floating gate and a control gate constituting a two-layer gate. Electric-field moderating layer is provided in the P-type semiconductor substrate to contact with a side face of the drain. P-type region is formed in contact with channel region side surface and bottom surface of the electric-field moderating layer. P-type region lower part of the P-type region in contact with the bottom surface of the electric-field moderating layer is given a lower impurity concentration than P-type region side part formed at the channel region side of the electric-field moderating layer. By this means it is possible to increase the writing speed of the semiconductor memory device while suppressing delay in the switching speed during reading operation.

Abstract: An article and method of manufacturing a semiconductor flash cell. The method includes producing an isolation formation layer on a silicon substrate, forming an oxide on the isolation formation layer, growing a tunnel oxide layer thereon, depositing a first poly silicon layer, masking and etching the first poly silicon layer, depositing a second poly silicon layer and performing a blanket etch back step, forming an oxide/nitride/oxide layer forming a third poly-silicon layer and depositing a silicide layer thereon.

Abstract: A split gate flash memory cell formed in a semiconductor substrate is disclosed. The memory cell comprises: a deep n-well formed in the substrate; a p-well formed in the deep n-well; a select gate structure formed on the p-well, the select gate structure comprising a stack of a gate oxide, a polysilicon layer, and a cap oxide; a tunnel oxide layer formed on the p-well, the tunnel oxide adjacent to the control gate structure; a floating gate formed over the select gate structure and extending over at least a portion of the tunnel oxide layer; a source formed in the p-well, the source formed adjacent to the floating gate; and a drain formed in the p-well, the drain formed adjacent to the select gate structure. The memory cell is programmed by source side channel hot electron and is erased using channel erasing to improve cycling endurance.

Abstract: Instead of using a common substrate (101) for each sector of a flash memory, trenches are used to isolate columnar active substrate regions (304) of the substrate (101), and independent access to each of these columnar regions (304) is provided. First, the independent access to each of these columnar regions (304) provides a capability for achieving more precise control over the voltage on the floating gates (106). For example, flash memory in accordance with the present invention is better suited for multi-level storage (storing of more than 1 bit of information per cell). Second, the independent access to each of these columnar regions (304) also provides a capability for areas of flash memory smaller than an entire sector to be erased at one time. Finally, since both programming and erasing is achieved by way of cold electron tunneling from the columnar active substrate region (304), no high voltages need to be applied to either the drain (102) or source (104).

Abstract: A method of manufacturing a trench non-volatile memory cell, comprises the steps of: providing a semiconductor substrate; performing ion implantation to form a source region in the semiconductor substrate; forming a trench on the semiconductor substrate by silicon etching, the trench reaching down to the source region; growing a first isolation layer on the surface of the semiconductor substrate, and the bottom and sidewall of the trench; forming a hollow-shaped first conducting layer in the trench; performing thermal oxidation on the first conducting layer to form a bird's beak isolation layer and a floating gate, which are the oxidized and unoxidized part of the first conducting layer, respectively, wherein the floating gate has a peak; partially removing the first isolation layer and the bird's beak isolation layer to bare the surface of the semiconductor substrate, the peak and the sidewall of the trench; depositing a second conducting layer; patterning the second conducting layer to form a cont

Abstract: An avalanche breakdown from the buried channel to the substrate in a semiconductor component, in particular an EEPROM, is avoided by a local thickened portion of the gate dielectric. The thickened portion establishes an insulation structure at the transition to the tunnel dielectric. This produces a potential barrier which enables the gate dielectric and the tunnel dielectric to have the same thickness. The space requirement of such a cell is reduced.

Abstract: In a non-volatile semiconductor memory device according to the present invention, a p type source region and a p type drain region are formed in the surface of an n well. A floating gate electrode and a control gate electrode are formed on a channel region with a tunnel oxide film interposed therebetween. According to this structure, a negative potential is applied to the drain region and a positive potential is applied to the control gate electrode when data is programmed, whereby electrons are injected from the drain region to the floating gate electrode by a band-to-band tunnel current induced hot electron injection current in the drain region. As a result, a non-volatile semiconductor memory device is provided which can prevent deterioration of the tunnel oxide film and which can be miniaturized.

Abstract: Methods of forming EEPROM memory cells having uniformly thick tunneling oxide layers include the steps of forming a preliminary field oxide isolation region of first thickness at a face of a semiconductor substrate of first conductivity type (e.g., P-type) and then forming a tunneling oxide layer on the face, adjacent the preliminary field oxide isolation region. The memory cell's drain region dopants are then implanted through the preliminary field oxide isolation region and into the substrate to form a preliminary drain region of second conductivity type. The preliminary field oxide isolation region is then grown to a second thickness greater than the first thickness by oxidizing the portion of the substrate containing the implanted dopants, to form a final field oxide isolation region which may have a thickness of about 2000 .ANG..

Abstract: A non-volatile memory device having a trench structure and a shallow drain region is formed in a substrate, thereby facilitating increased densification, improved planarization and low power programming and erasing. Embodiments include forming first and second trenches in a substrate and, in each trench, sequentially forming a substantially U-shaped tunnel dielectric layer and a substantially U-shaped floating gate electrode. A dielectric layer is then formed on the floating gate electrode extending on the substrate surface and a substantially T-shaped control gate electrode is formed filling the trench and extending on the substrate. Sidewall spacers are formed on side surfaces of the control gate electrode and dielectric layer, followed by ion implantation to form a shallow drain region between the first and second trenches and source regions extending to a greater depth than the drain region.

Abstract: In a semiconductor device and a method of manufacturing the same, two floating gate electrodes are independently controlled with one control gate electrode. In the semiconductor device, the first floating gate electrode is formed on a channel region with a first gate insulating film therebetween, and the control gate electrode is formed on the first floating gate electrode with a first interlayer insulating film therebetween. The second floating gate electrode exists on the control gate electrode and has a portion extended above a semiconductor substrate and overlapping with a second impurity diffusion layer. A first impurity diffusion layer overlaps with an end of the first floating gate electrode. Thereby, writing, erasing and reading are effected on the two, i.e., first and second floating gate electrodes with one control gate electrode while maintaining the substantially same memory cell area as the prior art.

Abstract: A split gate P-channel flash memory cell and method of forming a split gate P-channel flash memory cell which avoids of high erasing voltage, reverse tunneling during programming, drain disturb and over erase problems, and permits shrinking the cell dimensions. The control gate has a concave top surface which intersects with the sidewalls to form a sharp edge. The cell is programmed by charging the floating gate with electrons by means of hot electron injection from the channel into the floating gate. The cell is erased by discharging the excess electrons from the floating gate into the control gate using Fowler-Nordheim tunneling. The sharp edge at the intersection of the concave top surface and the sidewalls of the floating gate produces a high electric field between the control gate and the floating gate to accomplish the Fowler-Nordheim tunneling with only moderate voltage differences between the floating gate and control gate.

Abstract: A single polysilicon DRAM cell is disclosed. The DRAM cell comprises: a deep n-well in a silicon substrate; a p-well within the deep n-well; a gate structure over and straddling the deep n-well and the p-well, the gate structure being a stack of a thin gate oxide layer and a conductive layer; and a n+ well within the p-well and adjacent to a sidewall of the gate structure. The p-well potential can be reset to -V.sub.cc /2 representing "0", and written to V.sub.cc /2 representing "1". The parasitic n-channel MOS with the p-well as the "body" will have a threshold voltage modulated by the p-well potential at V.sub.cc /2 and -V.sub.cc /2 for representing "1" and "0" states, respectively.

Abstract: An ETOX cell formed in a semiconductor substrate is disclosed. The ETOX cell includes a p-well formed within the substrate. A floating-gate is formed above the p-well, the floating-gate being separated from the substrate by a thin oxide layer. Next, a control gate is formed above the floating-gate, the floating-gate and the control gate being separated by a dielectric layer. A drain region is formed in the p-well and adjacent to a first edge of the floating-gate. The drain region is of a first dopant type. Finally, a source region is formed in the p-well and adjacent to a second edge of the floating-gate, the source region being of a second dopant type.

Abstract: A split-gate source side injection flash EEPROM array structure and method of fabrication that utilizes the same polysilicon layer to form the control gate and the floating gate. Furthermore, there is a tunneling oxide layer underneath the floating gate, a gate oxide layer underneath the control gate, and that the tunneling oxide layer has a thickness smaller than the gate oxide layer. Since the control gate and the floating gate are formed on a silicon layer through the same patterning process, polysilicon spacers can be used to control the gap width between the control gate and the floating gate. Therefore, a reliable and reproducible flash cell array can be produced.

Abstract: A scalable flash EEPROM cell has a semiconductor substrate with a drain and a source and a channel therebetween. A select gate is positioned over a portion of the channel and is insulated therefrom. A floating gate has a first edge and a second edge with a first portion over the select gate and insulated therefrom, and a second portion over a second portion of the channel and over the source, and is between the select gate and the source. A control gate is over the floating gate and is insulated therefrom and has a first edge and a second edge aligned with the first edge and the second edge of the floating gate.

Abstract: In a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first surface region and the second surface region together, a channel region has a triple structure. Thus, a high electric field is formed in a corner portion between the step side region and the second surface region and in the vicinity thereof. A high electric field is also formed in the first surface region. As a result, the efficiency, with which electrons are injected into a floating gate, is considerably increased.

Abstract: A non-volatile memory cell includes a well region formed in a semiconductor substrate. First and second avalanche injection elements reside in the well region. A bifurcated floating-gate electrode includes a first segment overlying the first avalanche injection element and a second segment overlying the second avalanche injection element. A first contact region resides in the well region adjacent to the first segment of the floating-gate electrode, and a second contact region resides in the well region adjacent to the second segment of the floating-gate electrode. Upon the application of programming or erasing voltage, electrical charge is independently transferred to each of the first and second segments of the floating-gate electrode from the first and second avalanche injection elements, respectively.

Abstract: A zero-power non-volatile memory cell includes a control element, an avalanche injection element, and a CMOS inverter. A floating-gate electrode is capacitively coupled to the control element, the avalanche injection element, and to the CMOS inverter. The avalanche injection element is arranged, so as to transfer electrical charge onto the floating-gate electrode. The presence of stored data within the memory cell is indicated by reading a supply voltage V.sub.DD at an output terminal of the inverter. Accordingly, data can be read from the non-volatile memory cell without applying electrical power to the cell.

Abstract: A plurality of memory cells are arranged in lattice arrangement to form a memory cell array. Each of the memory cells is provided with a source. Data in the memory cell can be electrically written and erased. Sources of all the memory cells are connected in common. Also, a source voltage control circuit having two or more kinds of load characteristics is connected to the sources connected in common. According to a load characteristics selected from a plurality of load characteristics, source voltage of the memory cell is controlled.

Abstract: A flash memory cell of the present invention comprises a silicon substrate consisted of an insulating film and a silicon film in which a first and second channel regions are formed and a pair of gate electrodes formed on the first and second channel regions, respectively. Each channel region has a drain region and source region formed at both sides thereof.

Abstract: Hot-electron injection driven by a hole impact ionization mechanism at the channel-drain junction provides a new method of hot electron injection. Using this mechanism, a four-terminal pFET floating-gate silicon MOS transistor for analog learning applications provides nonvolatile memory storage. Electron tunneling permits bidirectional memory updates. Because these updates depend on both the stored memory value and the transistor terminal voltages, the synapses can implement a learning function. The synapse learning follows a simple power law. Unlike conventional EEPROMs, the synapses allow simultaneous memory reading and writing. Synapse transistor arrays can therefore compute both the array output, and local memory updates, in parallel. Synaptic arrays employing these devices enjoy write and erase isolation between array synapses is better than 0.01% because the tunneling and injection processes are exponential in the transistor terminal voltages.

Abstract: A non-volatile semiconductor cell structure and method comprises a trenched floating gate, a sidewall doping and a corner doping and further includes a sidewall doped region, a corner doped region, a channel region, and an inter-gate dielectric layer, and a control gate. The trenched floating gate is formed in a trench etched into the semiconductor substrate. In a preferred embodiment, the trenched floating gate has a top surface which is substantially planar with a top surface of the semiconductor substrate. The control gate and the inter-gate dielectric are formed on the top surface of the trenched floating gate. The sidewall doped region and the corner doped region are laterally separated by the trench in which the trenched floating gate is formed. The sidewall doped region has a depth which is greater than the depth of the trench, and the corner doped region has a depth which is less than the depth of the trench.

Abstract: A flash memory device has improved erasable characteristics and device reliability. The flash memory device includes a semiconductor substrate and heavily doped impurity regions formed spaced apart from one another by a predetermined distance in the semiconductor substrate in a first direction. First and second isolation regions are formed spaced apart from each other by a second predetermined distance on the semiconductor substrate, in a second direction which is preferably at a right angle to the first direction. Each of the floating gates are formed between the first and second isolation regons and between the heavily doped impurity regions. The control gate lines are formed between the first and second isolation regions, and over the floating gates in the same direction as the first and second isolation regions. An erase gate line is formed to have a narrower width than the floating gate, and is formed over the floating gate, preferably at a right angle to the control gate line.

Abstract: A method of fabricating a flash memory having a vertical floating gate terminal layer and controlling gate terminal layer structure, which is suitable for use in ultra-high density IC circuits, and which has two separate tunneling layers, one used for data programming and the other used for data erasure. The fabrication method includes a number of steps. A protruding plateau is first formed on the surface of a silicon substrate. Then, ions are implanted to form a drain region on the top surface of the protruding plateau, as well as to form source regions in the substrate on each side of and adjacent to the base of the protruding plateau. A gate oxide layer is formed on each side wall of the protruding plateau; exposing only part of the side wall of the drain region. A tunnel oxide layer that is thinner than the gate oxide layer, is formed above the surface of the silicon substrate so as to cover the source regions and drain region.

Abstract: A non-volatile semiconductor memory in which a plurality of flash memory cells are arranged in a matrix, each flash memory cell including source and drain regions formed on a silicon substrate, a floating gate formed on at least a part of the source and drain regions with a dielectric film provided therebetween, and a control gate formed on the floating gate with a dielectric layer provided therebetween, wherein a writing operation is performed by applying a positive voltage to the drain region and a negative voltage to the control gate and extracting electrons from the floating gate to the drain region by an FN tunnel current, a common source line for connecting the source region of the flash memory cells includes a diffusion layer formed in the silicon substrate and a silicide formed on the diffusion layer, and impurity concentration of the source region and the common source line are set lower than the impurity concentration of the drain region.

Abstract: A tunneling insulation film MOSFET and a fabrication method for a tunneling insulation film MOSFET avoid a short channel effect and prevent a punchthrough phenomenon by forming a tunneling insulation film between a channel area and one of source area and a drain area. The fabrication method can include the steps of forming a gate oxide film and a gate electrode on a silicon substrate, forming a hole perpendicular to the surface of the silicon substrate along one side of the gate electrode, forming a tunneling oxide film in the hole, and forming a source and a drain by implanting an impurity into the silicon substrate using the gate electrode as a mask.

Abstract: A two-transistor flash EPROM cell for high-speed high-density PLD applications is provided. The two-transistor cell includes a storage transistor connected in series to an access transistor. The storage transistor prevents problems associated with both over-erase and punch-through, and allows for scaling of the gate length to realize 5V cell programming.

Abstract: Semiconductor memory device and method is provided for a stacked gate type flash semiconductor memory device. The semiconductor memory device improves programming and erasing operation efficiency. A gate oxide layer and a floating gate are formed to be stacked on a substrate. A first dielectric layer and a control gate are formed to be stacked on the floating gate. A second dielectric layer is formed on both sides of the floating gate and first and second semiconductor sidewalls are formed on the second dielectric layer on the both sides of the floating gate. Impurity regions are formed in the substrate at the both sides of the floating gate and a wire layer is formed to contact with the semiconductor sidewalls and each of the impurity regions.

Abstract: A nonvolatile semiconductor memory device is obtained of which tunnel oxide film can be made thinner and which can allow low voltage and power consumption. P type polycrystal silicon is used as a floating gate electrode. Thickness of a tunnel oxide film (first insulating film) is set to less than 10 nm. By using P type polysilicon as a material of the floating gate electrode, a barrier height of a well-type potential is increased from 3.1 eV to 4.4 eV, and thus the leak current is effectively prevented. Thus, the film thickness of the tunnel oxide film can be made less than 10 nm, and operating voltage can also be lowered. Therefore, reduction in power consumption and improvement in performance of the nonvolatile semiconductor memory device can be achieved.

Abstract: A flash E.sup.2 PROM cell includes a single polysilicon layer part of which makes up the floating gate of a transistor of the cell, part of which makes up an electrode of a capacitor coupled to the floating gate, and part of which makes up the gate of a second transistor of the cell.

Abstract: In a non-volatile semiconductor memory device according to the present invention, a p type source region and a p type drain region are formed in the surface of an n well. A floating gate electrode and a control gate electrode are formed on a channel region with a tunnel oxide film interposed therebetween. According to this structure, a negative potential is applied to the drain region and a positive potential is applied to the control gate electrode when data is programmed, whereby electrons are injected from the drain region to the floating gate electrode by a band-to-band tunnel current induced hot electron injection current in the drain region. As a result, a non-volatile semiconductor memory device is provided which can prevent deterioration of the tunnel oxide film and which can be miniaturized.

Abstract: A raised-bitline, contactless flash memory device with trenches on a semiconductor substrate doped with a first conductivity type includes a first well of an opposite conductivity type comprising a deep conductor line to a device, and a second well of the first conductivity type above the first well comprising a body line to the device. Deep trenches extend through the second well into the first well. The trenches are filled with a first dielectric. There are gate electrode stacks for a flash memory device including a gate oxide layer over the device. First doped polysilicon floating gates are formed over the gate oxide layer. An interpolysilicon dielectric layer is formed over floating gate electrodes, and control gate electrodes formed of doped polysilicon layer overlie the interpolysilicon dielectric layer. A dielectric cap overlies the control gate electrodes.

Abstract: A least one one-time programmable nonvolatile (NV) memory element uses a field-effect transistor (FET) as a selectively programmed element. A short duration applied drain voltage exceeding the FET's drain-to-source breakdown voltage results in a drain source resistance which is substantially unaffected by the voltages typically applied at the gate terminal. Since the programmed resistance is less than 200 ohms and a high programming voltage is not required, the present invention compares favorably with antifuse nonvolatile memory techniques. The nonvolatile memory element is implemented without adding complexity to a very large scale integrated (VLSI) circuit process.

Abstract: The semiconductor nonvolatile memory has integrated memory cells, each being operative to carry out writing and reading of information in random-access basis and having an electric charge storage structure effective to memorize the information in nonvolatile state. The information is temporarily written into each memory cell in volatile state, and thereafter the temporarily written information is written at one into the respective electric charge storage structure of each memory cell, thereby effecting quick writing of nonvolatile information into the respective memory cells of multi-bits.

Abstract: A three-terminal silicon MOS transistor with a time-varying transfer function is provided which may operate both as a single transistor analog learning device and as a single transistor non-volatile analog memory. The time-varying transfer function is achieved by adding or removing electrons from the fully insulated floating gate of an N-type MOS floating gate transistor. The transistor has a control gate capacitively coupled to the floating gate; it is from the perspective of this control gate that the transfer function of the transistor is modified. Electrons are removed from the floating gate via Fowler-Nordheim tunneling. Electrons are added to the floating gate via hot-electron injection.

Abstract: A non-volatile split-gate memory cell 8 which can be programmed with only a five volt power supply and is fabricated using standard transistor processing methods, comprises a semiconductor substrate 10 with a source 12 and a drain 14 region separated by a channel region 16. A conductive floating gate 18 is formed over a portion 16a of the channel region 16 and separated by a FAMOS oxide 20. A conductive control gate 22 is formed over but electrically insulated from the floating gate 18 and over a second portion 16b of the channel region 16. The control gate 22 is separated from the second portion of the channel 16b by a pass oxide 26 which is thicker than the FAMOS oxide 20. Other embodiments and processes are also disclosed.

Abstract: A floating gate diode which can be used as a sourceless memory cell, and which may be arranged into an array of memory cells is disclosed. The floating gate diode comprises: a drain region formed in a substrate; an oxide overlying and associated with the drain region; and a floating gate overlying the oxide. Upon application of a voltage to the drain, a current between the drain and substrate is induced in proportion to an amount of electrons stored on the gate. The cells may be arranged into an array which comprises a substrate having a surface; a plurality of drain regions, one of said drain regions respectively corresponding to one of the plurality of cells, formed in the substrate; an oxide region overlying the plurality of drain regions on the surface of the substrate; and a plurality of floating gates overlying the oxide and respectively associated with the plurality of drain regions.

Abstract: In a flash type EEPROM device, when a dose amount of an impurity of a floating gate is controlled, or, a channel of a transistor is buried by an ion implantation, the threshold value at no charges accumulated is set between the threshold at writing and the threshold at erasure, to reduce the disturbances of a drain and a gate when reading.

Abstract: The present invention is directed toward a novel type of FLASH EEPROM cell that is highly scalable in size, easy to fabricate, reliable and capable of in-system programmability. The semiconductor memory cell comprises a lightly doped n- region including a channel region, a first insulating layer overlying portions of said n- region, and a floating gate overlying said first insulating layer. The cell further includes a second insulating layer overlying said floating gate and a control gate overlying second insulating layer.

Abstract: A nonvolatile memory device includes a semiconductor substrate of a first conductivity type; a gate insulating film formed on the substrate; a floating gate having a first region and a second region, the first region lying flat over the gate insulating film and the second region being extended from a first end portion of the first region and perpendicular to the first region; a control gate extending parallel to the second region of the floating gate, lying over the second end portion of the first region of the floating gate and perpendicular to the first region; an inter-insulating layer disposed between the floating gate and the control gate; a first spacer formed at a side wall of the second region of the floating gate and a second spacer formed at a side wall defined by the floating gate and the control gate; a high density source region of a second conductivity type formed in the substrate, being disposed a thickness of the first spacer distant from the floating gate; a first high density drain region of

Abstract: Each of source regions (4) is provided only immediately below a bottom surface (3B) of each of trenches (3) which is formed in a silicon substrate (1), extending inward from a main surface (1S) thereof along a second direction, and each of gate electrode portions (23) is provided inside each of the trenches (3). Specifically, each of the gate electrode portions (23) consists of a gate oxide film (19) formed on a side surface (S1) and part of the bottom surface (3B) of the trench (3), an FG electrode (20) formed thereon, a gate insulating film (21) formed on a side surface of the FG electrode (20) which is out of contact with the gate oxide film (19), an upper surface of the FG electrode (20), a side surface (2S) and the other part of the bottom (3B) of the trench (3), and a CG electrode (22) formed so as to cover an upper surface of the gate insulating film (21). Each of drain regions (11) is shared by the two adjacent transistors.

Abstract: A non-volatile semiconductor memory device including a memory cell having a memory transistor and a selection transistor, comprising: a composite gate structure of the memory transistor formed on a surface of a semiconductor substrate at its first region with a first insulating film interposed therebetween and including a laminate of a floating gate electrode, a second insulating film and a control gate electrode; a gate electrode of the selection transistor formed on the surface of the semiconductor substrate at its second region close to the first region with a third insulating film interposed therebetween; and an impurity diffusion layer formed in the semiconductor substrate at its region between the first and second regions and functioning as a drain of the memory transistor, common to a source of the selection transistor, the impurity diffusion layer having at least an extension region extending to a part of the semiconductor substrate disposed under the composite gate structure, the extension region hav

Abstract: A nonvolatile memory cell (10) includes a single n-channel insulated gate FET (11) having a single floating gate (12). The FET (11) operates asymmetrically in a sense that the capacitance of a parasitic gate-source capacitor (24) is smaller than the capacitance of a parasitic gate-drain capacitor (26). The asymmetric condition is achievable either by fabricating the FET (11) as an asymmetric structure (30, 60) or by adjusting the capacitance of the parasitic capacitors (24, 26) through terminal biasing when the FET (11) is a short channel device. The potential of the floating gate (12) is controlled by biasing the source (14), drain (16), and substrate (18) of the FET (11). The cell (10) is programmed by moving charge onto the floating gate (12) via hot carrier injection, erased by moving charge from the floating gate (12) via tunneling, and read by sensing the conductive state of the FET (11).

Abstract: A programmable interconnect which closely integrates an independent switching transistor with separate NVM programming and erasing elements. The programming element is an EPROM transistor and the erasing element is a Fowler-Nordheim tunneling device. A unitary floating gate is shared by the switching transistor and the NVM programming and elements which charge and discharge the floating gate. The shared floating gate structure is the memory structure of the integrated programmable interconnect and controls the impedance of the switching transistor.

Abstract: A method for sensing the content of a FLASH memory cell, and a new FLASH memory cell structure that is suitable for use with this new sensing scheme. In a first aspect, a semiconductor memory cell comprises a lightly doped n-region including a channel region; a first insulating layer overlying portions of said n-region; a floating gate overlying said first insulating layer; a second insulating layer overlying said floating gate; and a control gate overlying second insulating layer.

Abstract: A cell array circuit for a programmable logic device is provided with split read and write lines in the memory cell. The circuit eliminates the need for pass gates in the speed path. The circuit includes steering logic, a row line driver circuit and a row decoder circuit to facilitate the different modes of operation of the cell array circuit.

Abstract: A non-volatile memory cell structure capable of being programmed by band-to-band tunneling induced substrate hot electron injection is formed in a semiconductor substrate 8 and comprises first 10 and second 12 highly doped regions separated by a channel region 14. A nitride layer 16, such as silicon nitride for example, is formed over the channel region 14. An oxide layer 18, such as silicon dioxide, is then formed over nitride layer. The oxide/nitride layer serves as the floating gate insulator. In another embodiment, an additional oxide layer 15 may be formed between the channel region 14 and the nitride layer 16. The floating gate 20 is formed over the oxide layer 16 and a control gate 24 is insulatively formed over the floating gate 20. Other variations, advantages and a fabrication method are also disclosed.

Abstract: A floating gate cell memory device, such as an EPROM or flash EEPROM, with improved discharge speed. A negative bias is applied to the effective substrate during discharge. The negative bias increases the electric field near the junction, thereby increasing the number of hot holes which can be injected to the floating gate, improving discharge speed.