Abstract: A metal-oxide-semiconductor field-effect transistor (MOSFET) device is described herein. The MOSFET device comprises a unit cell on a silicon carbide (SiC) substrate. The unit cell comprises: a source region; a well region; and a source attachment region. The source attachment region is in contact with the source region. The source attachment region is doped using first conductivity type ions. In an embodiment, the source attachment region is doped using second conductivity type ions. The source attachment region comprises a depth shallower than a depth of source region. In an embodiment, the source attachment region comprises a depth equal to a depth of the source region. The source attachment region comprises a doping concentration lower than a doping concentration of the source region. In an embodiment, the source attachment region comprises a doping concentration equal to a doping concentration of the source region.

Abstract: A semiconductor structure includes a substrate, a gate structure on the substrate, and a source structure and a drain structure on opposite sides of the gate structure. The gate structure includes a gate electrode on the substrate and a gate metal layer on the gate electrode. The gate metal layer has at least one notch, which exposes the gate electrode below. The electric potential of the source structure is different from that of the gate structure.

Abstract: The present disclosure relates to a radio frequency (RF) device and a process for making the same. According to the process, a precursor wafer, which includes device regions, individual interfacial layers, individual p-type doped layers, and a silicon handle substrate, is firstly provided. Each individual interfacial layer is over an active layer of a corresponding device region, each individual p-type doped layer is over a corresponding individual interfacial layer, and the silicon handle substrate is over each individual p-type doped layer. Herein, each individual interfacial layer is formed of SiGe, and each individual p-type doped layer is a silicon layer doped with a p-type material that has a doped concentration greater than 1E18cm-3. Next, the silicon handle substrate is completely removed to provide an etched wafer, and each individual p-type doped layer is completely removed from the etched wafer.

Abstract: The present disclosure relates to a radio frequency (RF) device and a process for making the same. According to the process, a precursor wafer, which includes device regions, individual interfacial layers, individual p-type doped layers, and a silicon handle substrate, is firstly provided. Each individual interfacial layer is over an active layer of a corresponding device region, each individual p-type doped layer is over a corresponding individual interfacial layer, and the silicon handle substrate is over each individual p-type doped layer. Herein, each individual interfacial layer is formed of SiGe, and each individual p-type doped layer is a silicon layer doped with a p-type material that has a doped concentration greater than 1E18cm-3. Next, the silicon handle substrate is completely removed to provide an etched wafer, and each individual p-type doped layer is completely removed from the etched wafer.

Abstract: The present disclosure relates to a radio frequency (RF) device and a process for making the same. According to the process, a precursor wafer, which includes device regions, individual interfacial layers, individual p-type doped layers, and a silicon handle substrate, is firstly provided. Each individual interfacial layer is over an active layer of a corresponding device region, each individual p-type doped layer is over a corresponding individual interfacial layer, and the silicon handle substrate is over each individual p-type doped layer. Herein, each individual interfacial layer is formed of SiGe, and each individual p-type doped layer is a silicon layer doped with a p-type material that has a doped concentration greater than 1E18cm-3. Next, the silicon handle substrate is completely removed to provide an etched wafer, and each individual p-type doped layer is completely removed from the etched wafer.

Abstract: The present disclosure relates to a radio frequency (RF) device and a process for making the same. According to the process, a precursor wafer, which includes device regions, individual interfacial layers, individual p-type doped layers, and a silicon handle substrate, is firstly provided. Each individual interfacial layer is over an active layer of a corresponding device region, each individual p-type doped layer is over a corresponding individual interfacial layer, and the silicon handle substrate is over each individual p-type doped layer. Herein, each individual interfacial layer is formed of SiGe, and each individual p-type doped layer is a silicon layer doped with a p-type material that has a doped concentration greater than 1E18cm-3. Next, the silicon handle substrate is completely removed to provide an etched wafer, and each individual p-type doped layer is completely removed from the etched wafer.

Abstract: In some examples, a semiconductor device, comprises a semiconductor substrate; an epitaxial layer having a top side disposed on the semiconductor substrate, wherein the epitaxial layer has a source implant region, a drain implant region, a first doped region, and a second doped region, wherein the first doped region is adjacent to the source implant region and the second doped region is adjacent to the drain implant region, wherein the top side has a sloped surface over the second doped region; a gate electrode supported by the top side; a source electrode in contact with the source implant region; and a drain electrode in contact with the drain implant region.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a source region, a drain region, a filed plate and a gate electrode. The source region is of a first conductivity type located at a first side within the substrate. The drain region is of the first conductive type located at a second side within the substrate opposite to the first side. The field plate is located over the substrate and between the source region and the drain region. A portion of the gate electrode is located over the field plate.

Abstract: A MOSFET device structure is formed on a semiconductor wafer. The structure includes an array of plurality of MOS gate trenches and self-aligned p+ contact trenches that are formed in a p body region. Trench depth of MOS gate trenches are deeper than the self-aligned p+ contact trenches. P doped shield regions are formed under each MOS gate trench.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a gate disposed on the substrate, a source disposed in the substrate and located on one side of the gate, a drain disposed in the substrate and located on another side of the gate, and a gate extending portion disposed on the substrate and located between the gate and the drain. The doping type of the gate is the opposite of that of the gate extending portion.

Abstract: An organic light-emitting diode (OLED) device includes an active layer of a transistor disposed on the buffer insulating film. A gate insulating film is disposed on the buffer insulating film over the conducting layer and disposed on the active layer. A gate electrode is disposed on the gate insulating film over a channel region of the active layer. A first connecting pattern is disposed on the gate insulating film over the conducting line and the active layer. The first connecting pattern is connected to the conducting layer via a first connecting contact hole through the gate insulating film and the buffer insulating film. The first connecting pattern is also connected to the active layer via a second connecting contact hole through the gate insulating film. The first connecting pattern has a same material as the gate electrode.

Abstract: A transistor includes a semiconductor substrate having a first terminal and a gate region, and an interconnect structure formed of multiple layers of dielectric and electrically material on an upper surface of the semiconductor substrate. The electrically conductive material includes first and second layers, the second layer being spaced apart from the first layer by a first dielectric layer of the dielectric material, the first layer residing closest to the upper surface of the semiconductor substrate relative to the second layer. The interconnect structure includes a pillar formed from the conductive material. The pillar is in electrical contact with the first terminal, the pillar extends through the dielectric material, and the pillar includes a pillar segment in the first layer of the conductive material. The interconnect structure also includes a shield structure in the first layer of the conductive material and positioned between the pillar segment and the gate region.

Abstract: A semiconductor device capable of high-voltage operation includes a semiconductor substrate having a first conductivity type. A first well doped region is formed in a portion of the semiconductor substrate. The first well doped region has a second conductivity type. A first doped region is formed on the first well doped region, having the second conductivity type. A second doped region is formed on the first well doped region and is separated from the first doped region, having the second conductivity type. A first gate structure is formed over the first well doped region and is adjacent to the first doped region. A second gate structure is formed beside the first gate structure and is close to the second doped region. A third gate structure is formed overlapping a portion of the first gate structure and a first portion of the second gate structure.

Abstract: A method of forming a memory device that in one embodiment may include forming a magnetic tunnel junction on a first electrode using an electrically conductive mask and subtractive etch method. Following formation of the magnetic tunnel junction, at least one dielectric layer is deposited to encapsulate the magnetic tunnel junction. Ion beam etching/Ion beam milling may then remove the portion of the at least one dielectric layer that is present on the electrically conductive mask, wherein a remaining portion of the at least one dielectric layer is present over the first electrode. A second electrode may then be formed in contact with the electrically conductive mask.

Abstract: Methods for forming a transistor include forming a gate conductor in contact with a gate stack. The gate conductor has a top surface that meets a middle point of sidewalls of a sacrificial region of a fin. The sacrificial region of the fin is trimmed to create gaps above the gate stack. A top spacer is formed on the gate conductor. The top spacer includes airgaps above the gate stack.

Abstract: A semiconductor device and the method of manufacturing the same are provided. The semiconductor device includes a substrate, a source region, a drain region, a filed plate and a gate electrode. The source region is of a first conductivity type located at a first side within the substrate. The drain region is of the first conductive type located at a second side within the substrate opposite to the first side. The field plate is located over the substrate and between the source region and the drain region. A portion of the gate electrode is located over the field plate.

Abstract: A method of fabricating a FET includes forming a gate on the surface of a substrate. A trench contact extends between a first region located proximate the surface of the substrate and a second region located below the first region is formed in the surface. The surface of the substrate is coated with a conductive material, wherein the conductive material at least partially covers the gate and lines the trench contact to electrically connect the first region and the second region. A void remains in the trench contact. A dielectric material is applied to the conductive material, wherein the dielectric material at least partially fills the void in the trench contact. At least a portion of the conductive material is etched from the gate.

Abstract: A device includes a semiconductor substrate, a body region in the semiconductor substrate having a first conductivity type and in which a channel is formed during operation, source and drain regions in the semiconductor substrate and having a second conductivity type, the source region being disposed on the body region, and a composite drift region in the semiconductor substrate, having the second conductivity type, and through which charge carriers from the source region drift to reach the drain region after passing through the channel. The composite drift region includes a first section adjacent the channel, a second section adjacent the drain region, and a third section disposed between the first and second sections. The first and second sections have a lower effective dopant concentration level than the third section.

Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type, a first electrode, a second electrode, a third electrode, a first insulation region, a second insulation region, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a fourth semiconductor region of the second conductivity type, and a fourth electrode. The second electrode includes first portions and a second portion. The second portion extends in a first direction. The first portions extend in a direction away from the second portion. The second portion is between the first portions and the first electrode in a second direction. The fourth semiconductor region is positioned between adjacent first electrode portions in the first direction.

Abstract: A semiconductor device and a method for manufacturing the same are provided. A semiconductor device includes a semiconductor substrate and a gate structure formed on the semiconductor substrate. A source region and a drain region are disposed on opposite sides of the gate structure on the semiconductor substrate. A lightly-doped drain region is adjacent to a side of the drain region close to the gate structure, and a lightly-doped source region is adjacent to a side of the source region close to the gate structure. An oxidation region is disposed in the lightly-doped drain region. A trench extends from the surface of the semiconductor substrate to the drain region. A source electrode is disposed on the source region, and the drain electrode has a first portion disposed on the drain region and a second portion disposed in the trench.

Abstract: An organic light emitting display is provided. The organic light emitting display comprises a multi-type thin-film transistor (TFT) and an organic light emitting diode. The multi-type TFT has a low-temperature-poly-silicon (LTPS) TFT and an oxide semiconductor TFT (oxide TFT) disposed on the LTPS TFT. The organic light emitting diode is electrically connected to the multi-type TFT. The LTPS TFT and the oxide TFT are connected to the same gate line.

Abstract: A semiconductor device includes a gate electrode adjacent to a body region in a semiconductor substrate. The semiconductor device further includes a field electrode in a field plate trench in the main surface, the field plate trench having an extension length in a first direction parallel to a main surface. The extension length is less than the double of an extension length in a second direction that is perpendicular to the first direction parallel to the main surface. The extension length in the first direction is more than half of the extension length in the second direction. The field electrode is insulated from an adjacent drift zone by means of a field dielectric layer. A field plate material of the field electrode has a resistivity in a range from 105 to 10?1 Ohm·cm.

Abstract: An array substrate having a wiring of a pad region formed without an insulating film or without an insulating film and an organic film to reduce abnormal operations due to an increase in resistance caused by a contact margin at a high temperature, and a method for manufacturing the same are provided. The array substrate includes: an insulating substrate including a pad region and a thin film transistor (TFT) formation region; a first electrode layer formed in the pad region of the substrate; and a second electrode formed on the first electrode layer in an overlapping manner.

Abstract: A method for processing a semiconductor device in accordance with various embodiments may include: providing a semiconductor device having a first pad and a second pad electrically disconnected from the first pad; applying at least one electrical test potential to at least one of the first pad and the second pad; and electrically connecting the first pad and the second pad to one another after applying the at least one electrical test potential.

Abstract: A test method in accordance with one or more embodiments may include: providing a semiconductor device to be tested, the semiconductor device including at least one device cell, the at least one device cell having at least one trench, at least one first terminal electrode region and at least one second terminal electrode region, at least one gate electrode, and at least one additional electrode disposed at least partially in the at least one trench, wherein an electrical potential of the at least one additional electrode may be controlled separately from electrical potentials of the at least one first terminal electrode region, the at least one second terminal electrode region and the at least one gate electrode; and applying at least one electrical test potential to at least the at least one additional electrode to detect defects in the at least one device cell.

Abstract: A split gate field effect transistor device. The device includes a split gate structure having a trench, a gate electrode and a source electrode. A first poly layer is disposed within the trench and is connected to the gate electrode. A second poly layer connected to the source electrode, wherein the first poly layer and the second poly layer are independent.

Abstract: In one embodiment, an apparatus can include a trench extending into a semiconductor region of a first conductivity type, an electrode disposed in the trench, and a source region of the first conductivity type abutting a sidewall of the trench. The apparatus can include a first well region of a second conductivity type disposed in the semiconductor region below the source region and abutting the sidewall of the trench lateral to the electrode where the second conductivity type is opposite the first conductivity type. The apparatus can also include a second well region of the second conductivity type disposed in the semiconductor region and abutting the sidewall of the trench, and a third well region of the first conductivity type disposed between the first well region and the second well region.

Abstract: A lateral double diffused metal-oxide-semiconductor device includes: a semiconductor substrate; an epitaxial semiconductor layer disposed over the semiconductor substrate; a gate structure disposed over the epitaxial semiconductor layer; a first doped region disposed in the epitaxial semiconductor layer at a first side of the gate structure; a second doped region disposed in the epitaxial semiconductor layer at a second side of the gate structure; a third doped region disposed in the first doped region; a fourth doped region disposed in the second doped region; a trench formed in the third doped region, the first doped region and the epitaxial semiconductor layer under the first doped region; a conductive contact formed in the trench; and a fifth doped region disposed in the epitaxial semiconductor layer under the trench.

Abstract: A test method in accordance with one or more embodiments may include: providing a semiconductor device to be tested, the semiconductor device including at least one device cell, the at least one device cell having at least one trench, at least one first terminal electrode region and at least one second terminal electrode region, at least one gate electrode, and at least one additional electrode disposed at least partially in the at least one trench, wherein an electrical potential of the at least one additional electrode may be controlled separately from electrical potentials of the at least one first terminal electrode region, the at least one second terminal electrode region and the at least one gate electrode; and applying at least one electrical test potential to at least the at least one additional electrode to detect defects in the at least one device cell.

Abstract: A power semiconductor device according to an embodiment includes an element portion in which MOSFET elements are provided and a termination portion provided around the element portion, and has pillar layers provided respectively in parallel to each other in a semiconductor substrate. The device includes a first trench and a first insulation film. The first trench is provided between end portions of the pillar layers, in the semiconductor substrate at the termination portion exposed from a source electrode of the MOSFET elements. The first insulation film is provided on a side surface and a bottom surface of the first trench.

Abstract: A semiconductor device of the present invention includes a semiconductor layer composed of SiC, a metal layer directly bonded to one face of the semiconductor layer, and a high carbon concentration layer formed on a surface layer portion at one side of the semiconductor layer and containing more highly concentrated carbon than a surface layer portion of the other side. Further, a manufacturing method of a semiconductor device of the present invention includes the steps of forming, on a surface layer portion at one face side of a semiconductor layer composed of SiC, a high carbon concentration layer containing more highly concentrated carbon than a surface layer portion at the other face side by heat treatment and directly bonding metal to the high carbon concentration layer.

Abstract: According to one embodiment, the semiconductor device includes a drift region, a first semiconductor region, a second semiconductor region, a main electrode, first gate electrodes and a second gate electrode. The first gate electrodes and the second gate electrode between a pair of first gate electrodes are provided in the drift region. The first semiconductor region is provided between the first gate electrodes and the second gate electrode. The first semiconductor region has a first side surface opposite to the one of the adjacent ones and a second side surface partially opposite to the second gate electrode. The second semiconductor region is selectively provided on the first semiconductor region. The main electrode has a portion directly adjacent to part of the second side surface and the second semiconductor region.

Abstract: A LDMOS device includes a substrate having opposite first and second surfaces; a well region in a portion of the substrate; a gate structure over a portion of the substrate; a first doped region disposed in a portion of the well region from a first side; a second doped region disposed in the well region from a second side; a third doped region disposed in the first doped region; a fourth doped region disposed in the second doped region; a first trench in the third doped region, the first doped region, the well region, and the substrate adjacent to the first surface; a conductive contact in the first trench; a second trench in the substrate adjacent to the second surface; a first conductive layer in second trench; and a second conductive layer over the second surface of the substrate and the first conductive layer.

Abstract: A semiconductor device of the present invention includes: a semiconductor substrate of a first conductive type; an epitaxial layer of the first conductive type formed on the semiconductor substrate and having a protrusion formed on a surface thereof; a well region of a second conductive type formed on the surface of the epitaxial layer at each side of the protrusion; a source region of the first conductive type selectively formed in a surface of the well region; a gate insulating film formed so as to cover at least the protrusion and the surface of the well region; and a gate electrode formed on a part of the gate insulating film corresponding to the protrusion. The gate insulating film is thicker in a region thereof corresponding to an upper surface of the protrusion than the other regions thereof.

Abstract: This invention discloses a semiconductor power device that includes a plurality of power transistor cells surrounded by a trench opened in a semiconductor substrate. At least one of the cells constituting an active cell has a source region disposed next to a trenched gate electrically connecting to a gate pad and surrounding the cell. The trenched gate further has a bottom-shielding electrode filled with a gate material disposed below and insulated from the trenched gate. At least one of the cells constituting a source-contacting cell surrounded by the trench with a portion functioning as a source connecting trench is filled with the gate material for electrically connecting between the bottom-shielding electrode and a source metal disposed directly on top of the source connecting trench.

Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: a first conductive type substrate, a second conductive type high voltage well, a gate, a first conductive type body region, a second conductive type source, a second conductive type drain, a first conductive type body electrode, and a first conductive type floating region. The floating region is formed in the body region, which is electrically floating and is electrically isolated from the source and the gate, such that the electrostatic discharge (ESD) effect is mitigated.

Abstract: A semiconductor device including a gate insulating film; a gate electrode; a source region of a first conductivity; a drain region of the first conductivity type; a drift region of the first conductivity type formed between the channel region and the drain region; a first semiconductor region of a second conductivity type that encloses the source region, the drift region and the drain region, and includes the channel region; and a first shield wiring that encloses a portion of the source region in a plan view in conjunction with the gate electrode, the portion being not covered by the gate electrode, and is connected to the first semiconductor region, or that covers the portion and is connected to the first semiconductor region and the source region.

Abstract: In one general aspect, a method can include forming a shield dielectric layer in a trench in a semiconductor substrate, forming a shield electrode on at least a portion of the shield dielectric layer, and etching the shield dielectric layer so that a portion of the shield dielectric layer is recessed in the trench. The method can include forming a gate dielectric layer on the recessed portion of the shield dielectric layer in the trench, forming a first conductive gate electrode on a first side of the shield electrode and insulated from a first sidewall of the trench by the gate dielectric layer, and forming a second conductive gate electrode on a second side of the shield electrode and insulated from a second sidewall of the trench by the gate dielectric layer.

Abstract: A semiconductor device includes a semiconductor body and a source metallization arranged on a first surface of the body. The body includes: a first semiconductor layer including a compensation-structure; a second semiconductor layer adjoining the first layer, comprised of semiconductor material of a first conductivity type and having a doping charge per horizontal area lower than a breakdown charge per area of the semiconductor material; a third semiconductor layer of the first conductivity type adjoining the second layer and comprising at least one of a self-charging charge trap, a floating field plate and a semiconductor region of a second conductivity type forming a pn-junction with the third layer; and a fourth semiconductor layer of the first conductivity type adjoining the third layer and having a maximum doping concentration higher than that of the third layer. The first semiconductor layer is arranged between the first surface and the second semiconductor layer.

Abstract: A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate, a channel region in the semiconductor substrate between the source and drain regions through which charge carriers flow during operation from the source region to the drain region, and a drift region in the semiconductor substrate, on which the drain region is disposed, and through which the charge carriers drift under an electric field arising from application of a bias voltage between the source and drain regions. A PN junction along the drift region includes a first section at the drain region and a second section not at the drain region. The drift region has a lateral profile that varies such that the first section of the PN junction is shallower than the second section of the PN junction.

Abstract: A multi-path transistor includes an active region including a channel region and an impurity region. A gate is dielectrically separated from the channel region. A signal line is dielectrically separated from the impurity region. A conductive shield is disposed between, and dielectrically separated from, the signal line and the channel region. In some multi-path transistors, the channel region includes an extension-channel region under the conductive shield and the multi-path transistor includes different conduction paths, at least one of the different conduction paths being in the extension-channel region to conduct substantially independent of a voltage on the signal line. In other multi-path transistors, the conductive shield is operably coupled to the impurity region and the multi-path transistor includes different conduction paths, at least one of the different conduction paths being under the conductive shield to conduct substantially independent of a voltage on the signal line.

Abstract: In an LDMOS transistor, a channel length is reduced to increase a saturation current without causing an off-state breakdown voltage optimized in terms of trade-off between an on-resistance and the off-state breakdown voltage. A short channel region is selectively formed between an element isolation film and a low-concentration body region in which a channel is formed such that the short channel region is located immediately below a gate oxide film. The short channel region has a conduction type opposite to that of the low-concentration body region and has a carrier concentration higher than that of the low-concentration body region. The body region is retreated by the presence of the short channel region toward a high-concentration source region.

Abstract: In a general aspect, a power device can include at least one N-type epitaxial layer disposed on a substrate and a plurality of N-pillars and P-pillars that define alternating P-N-pillars in the at least one N-type epitaxial layer. The power device can also include an active region and a termination region, where the termination region surrounds the active region. The alternating P-N-pillars can be disposed in both the active region and the termination region, where the termination region can include a predetermined number of floating P-pillars.

Abstract: This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area.

Abstract: A method of forming a device is disclosed. A substrate having a device region is provided. The device region comprises a source region, a gate and a drain region defined thereon. A drift well is formed in the substrate adjacent to a second side of the gate. The drift well underlaps a portion of the gate with a first edge of the drift well beneath the gate. A secondary portion is formed in the drift well. The secondary portion underlaps a portion of the gate with a first edge of the secondary portion beneath the gate. The first edge of the secondary portion is offset from the first edge of the drift well. A gate dielectric of the gate comprises a first portion having a first thickness and a second portion having a second thickness. The second portion is over the secondary portion.

Abstract: A device includes a semiconductor region in a semiconductor chip, a gate dielectric layer over the semiconductor region, and a gate electrode over the gate dielectric. A drain region is disposed at a top surface of the semiconductor region and adjacent to the gate electrode. A gate spacer is on a sidewall of the gate electrode. A dielectric layer is disposed over the gate electrode and the gate spacer. A conductive field plate is over the dielectric layer, wherein the conductive field plate has a portion on a drain side of the gate electrode. A deep metal via is disposed in the semiconductor region. A source electrode is underlying the semiconductor region, wherein the source electrode is electrically shorted to the conductive field plate through the deep metal via.

Abstract: A technique for improving characteristics of a semiconductor device (DMOSFET) is provided. A semiconductor device is configured so as to include: an n-type source layer (102) disposed on an upper portion of a first surface side of an SiC substrate (106); a p body layer (103) which surrounds the source layer and has a channel region; an n?-type drift layer (107) which is in contact with the p body layer (103); a gate electrode (116) which is disposed on an upper portion of the channel region via a gate insulating film; and a first p+ layer (109) which is disposed in the p body layer (103), extends to a portion below the n+ source layer (102), and serves as a buried semiconductor region having an impurity concentration higher than that of the p body layer (103). In this manner, since the first p+ layer (109) is formed in the middle of the p body layer (103), it is possible to reduce the diffusion resistance of the p body layer (103). Thus, it is possible to make a parasitic bipolar transistor harder to turn on.

Abstract: A MOSFET device has a funnel-shaped trench etched in a semiconductor substrate. The funnel-shaped trench has flared rim extending from a wider cross section trench mouth at the surface of the semiconductor substrate to a narrower cross section trench body portion which terminates in an epilayer portion of the semiconductor substrate. A gate electrode is disposed in the trench on the flared rim. Source and gate regions of the device abut upper and lower portions of the flared rim, respectively. A drain region of the device, which abuts the narrower cross section trench body portion, is self-aligned with a lower edge of a gate electrode.

Abstract: In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the transistor segments in the first and second sections includes a pillar of a semiconductor material that extends in a vertical direction. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. Outer field plates of transistor segments adjoining first and second sections are either separated or partially merged.

Abstract: An LDMOS device includes: a semiconductor layer formed over a semiconductor substrate; a gate structure disposed over the semiconductor layer; a first doped region disposed in the semiconductor layer adjacent to a first side of the gate structure; a second doped region disposed in the semiconductor layer adjacent to a second side of the gate structure; a third doped region disposed in the first doped region; a fourth doped region disposed in the second doped region; a trench formed in the third doped region, the first doped region and the semiconductor layer under in the first doped region; an insulating layer covering the third doped region, the gate structure, and the fourth doped region; a conductive layer conformably formed over a bottom surface and sidewalls of the trench; a dielectric layer disposed in the trench; and a diffused region disposed in the semiconductor layer under the trench.