Abstract: Hybrid semiconductor devices including a PIN diode portion and a Schottky diode portion are provided. The PIN diode portion is provided on a semiconductor substrate and has an anode contact on a first surface of the semiconductor substrate. The Schottky diode portion is also provided on the semiconductor substrate and includes a polysilicon layer on the semiconductor substrate and a ohmic contact on the polysilicon layer. Related Schottky diodes are also provided herein.

Abstract: Disclosed is a semiconductor device including: a base substrate; a semiconductor layer disposed on the base substrate; an ohmic electrode part which has ohmic electrode lines disposed in a first direction, on the semiconductor layer; and a Schottky electrode part which is disposed to be spaced apart from the ohmic electrode lines on the semiconductor layer and includes Schottky electrode lines disposed in the first direction, wherein the Schottky electrode lines and the ohmic electrode lines are alternately disposed in parallel, and the ohmic electrode part further includes first ohmic electrodes covered by the Schottky electrode lines on the semiconductor layer.

Abstract: This invention discloses a gallium nitride based semiconductor power device disposed in a semiconductor substrate. The power device comprises a termination area disposed at a peripheral area of the semiconductor power device comprises a termination structure having at least a guard ring disposed in a trench filled with doped gallium-based epitaxial layer therein.

Abstract: Provided is a semiconductor device having an anode of a Si-FRD and a cathode of a Si-SBD which are serially connected. The Si-SBD has a junction capacitance whose amount of accumulable charge is equal to or more than an amount of charge occurring at the time of reverse recovery of the Si-FRD, and has a lower breakdown voltage than the Si-FRD does.

Abstract: A III-V-group compound semiconductor device includes a substrate, a channel layer provided over the substrate, a barrier layer provided on the channel layer so as to form a hetero-interface, a plurality of electrodes provided on the barrier layer, an insulator layer provided to cover an entire upper surface of the barrier layer except for at least partial regions of the electrodes, and a hydrogen-absorbing layer stacked on the insulator layer or an integrated layer in which an hydrogen-absorbing layer is integrated with the insulator layer.

Abstract: The embodiments of the present invention disclose a semiconductor device and a method for forming the semiconductor device. Wherein the semiconductor comprises: a first semiconductor layer, having a first conductivity type on a semiconductor substrate, a guard ring region, formed in the surface of the first semiconductor layer, having a second conductivity type; a Schottky diode metal contact, coupled to the first semiconductor layer, wherein the guard ring region is at periphery of the Schottky diode interface, and wherein the Schottky diode metal contact has no direct electrical connection with the guard ring region; and an electrical resistance module, coupled between the Schottky diode metal contact and the guard ring. Due to the ballasting effect from the electrical resistance module, the minority injection or the parasitic transistor action are alleviated. Thus, forward current capability is extended without introducing significant minority injection.

Abstract: A junction barrier Schottky diode has N-type well having a surface and first peak impurity concentration; P-type anode region in surface of the well having second peak impurity concentration; N-type cathode contact region in surface of the well and laterally spaced from a first wall of the anode region having third peak impurity concentration; and first N-type region in surface of the well and laterally spaced from second wall of the anode region having fourth impurity concentration. Center of the spaced region between the first N-type region and the second wall of the anode region has fifth peak impurity concentration. Ohmic contact is made to the anode region and cathode contact region. Schottky contact is made to the first N-type region. First and fifth peak impurity concentrations are less than the fourth peak impurity concentration. The fourth peak impurity concentration is less than the second and third peak impurity concentrations.

Abstract: Provided is a light-receiving device which has light-receiving sensitivity superior to that of a conventional Schottky diode type light-receiving device and also has sufficiently-strengthened junction of a Schottky electrode. A first contact layer formed of AlGaN and having conductivity, a light-receiving layer formed of AlGaN, and a second contact layer formed of AlN and having a thickness of 5 nm are epitaxially formed on a predetermined substrate in the stated order, and a second electrode is brought into Schottky junction with the second contact layer, to thereby form MIS junction. Further, after the Schottky junction, heat treatment is performed under a nitrogen gas atmosphere at 600° C. for 30 seconds.

Abstract: A bidirectional switch includes a plurality of unit cells 11 including a first ohmic electrode 15, a first gate electrode 17, a second gate electrode 18, and a second ohmic electrode 16. The first gate electrodes 15 are electrically connected via a first interconnection 31 to a first gate electrode pad 43. The second gate electrodes 18 are electrically connected via a second interconnection 32 to a second gate electrode pad 44. A unit cell 11 including a first gate electrode 17 having the shortest interconnect distance from the first gate electrode pad 43 includes a second gate electrode 18 having the shortest interconnect distance from the second gate electrode pad 44.

Abstract: A semiconductor circuit and method of fabrication is disclosed. In one embodiment, the semiconductor circuit comprises a metal-insulator-metal trench capacitor in a silicon substrate. A field effect transistor is disposed on the silicon substrate adjacent to the metal-insulator-metal trench capacitor, and a silicide region is disposed between the field effect transistor and the metal-insulator-metal trench capacitor. Electrical connectivity between the transistor and capacitor is achieved without the need for a buried strap.

Abstract: A unipolar diode with low turn-on voltage includes a subcathode semiconductor layer, a low-doped, wide bandgap cathode semiconductor layer, and a high-doped, narrow bandgap anode semiconductor layer. A junction between the cathode layer and the anode layer creates an electron barrier in the conduction band, with the barrier configured to produce a low turn-on voltage for the diode. A unipolar diode with low turn-on voltage includes an n+ subcathode semiconductor layer, a low-doped, wide bandgap cathode semiconductor layer, and an n+ narrow bandgap anode semiconductor layer. Again, a junction between the cathode layer and the anode layer creates an electron barrier in the conduction band, with the barrier configured to produce a low turn-on voltage for the diode.

Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type and formed of a material having a band gap wider than that of silicon; a first layer selectively disposed on a surface of and forming a first junction with the first semiconductor region; a second layer selectively disposed on the first semiconductor region and forming a second junction with the first semiconductor region; a first diode formed by a region including the first junction; a second diode formed by a region including the second junction; and a fourth semiconductor region of a second conductivity type and disposed in the first semiconductor region, between and contacting the first and second junctions. A recess and elevated portion are disposed on the first semiconductor region. The first and the second junctions are formed at different depths. The second diode has a lower built-in potential than the first diode.

Abstract: A semiconductor device according to some embodiments includes a semiconductor layer having a first conductivity type and a surface in which an active region of the semiconductor device is defined. A plurality of spaced apart first doped regions are arranged within the active region. The plurality of first doped regions have a second conductivity type that is opposite the first conductivity type, have a first dopant concentration, and define a plurality of exposed portions of the semiconductor layer within the active region. The plurality of first doped regions are arranged as islands in the semiconductor layer. A second doped region in the semiconductor layer has the second conductivity type and has a second dopant concentration that is greater than the first dopant concentration.

Abstract: A Schottky diode includes a Schottky barrier and a plurality of dopant regions disposed near the Schottky barrier as floating islands to function as PN junctions for preventing a leakage current generated from a reverse voltage. At least a trench opened in a semiconductor substrate with a Schottky barrier material disposed therein constitutes the Schottky barrier. The Schottky barrier material may also be disposed on sidewalls of the trench for constituting the Schottky barrier. The trench may be filled with the Schottky barrier material composed of Ti/TiN or a tungsten metal disposed therein for constituting the Schottky barrier. The trench is opened in a N-type semiconductor substrate and the dopant regions includes P-doped regions disposed under the trench constitute the floating islands. The P-doped floating islands may be formed as vertical arrays under the bottom of the trench.

Abstract: The present invention provides a semiconductor device including: a base substrate; a semiconductor layer which is disposed on the base substrate and has a 2-Dimensional Electron Gas (2DEG) formed therewithin; a first ohmic electrode disposed on a central region of the semiconductor layer; a second ohmic electrode which is formed on the edge regions of the semiconductor layer in such a manner to be disposed to be spaced apart from the first ohmic electrodes, and have a ring shape surrounding the first ohmic electrode; and a Schottky electrode part which is formed on the central region to cover the first ohmic electrode and is formed to be spaced apart from the second ohmic electrode.

Abstract: The present invention provides a semiconductor device including: a base substrate; a first semiconductor layer disposed on the base substrate; first ohmic electrodes disposed on a central region of the first semiconductor layer; a second ohmic electrode having a ring shape surrounding the first ohmic electrodes, on edge regions of the first semiconductor layer; a second semiconductor layer interposed between the first ohmic electrodes and the first semiconductor layer; and a Schottky electrode part which covers the first ohmic electrodes on the central regions, and is spaced apart from the second ohmic electrode.

Abstract: A diode (200) is disclosed having improved efficiency, smaller form factor, and reduced reverse biased leakage current. Schottky diodes (212) are formed on the sidewalls (210) of a mesa region (206). The mesa region (206) is a cathode of the Schottky diode (212). The current path through the mesa region (206) has a lateral and a vertical current path. The diode (200) further comprises a MOS structure (214), p-type regions (220), MOS structures (230), and p-type regions (232). MOS structure (214) with the p-type regions (220) pinch-off the lateral current path under reverse bias conditions. P-type regions (220), MOS structures (230), and p-type regions (232) each pinch-off the vertical current path under reverse bias conditions. MOS structure (214) and MOS structures (230) reduce resistance of the lateral and vertical current path under forward bias conditions. The mesa region (206) can have a uniform or non-uniform doping concentration.

Abstract: The present invention relates to the field of microelectronic technology. It discloses a mixed Schottky/P-N junction diode and a method of making the same. The mixed Schottky/P-N junction diode comprises a semiconductor substrate having a bulk region and a doped region, and a conductive layer on the semiconductor substrate. The doped region has opposite doping from that of the bulk region. A P-N junction is formed between the bulk region and the doped region, a Schottky junction is formed between the conductive layer and the semiconductor substrate, and an ohmic contact is formed between the conductive layer and the doped region. The mixed Schottky/P-N junction diode of the present invention has high operating current, fast switching speed, small leakage current, high breakdown voltage, ease of fabrication and other advantages.

Abstract: The present invention relates to a Schottky diode with a diamond rod, which comprises: a substrate with a gate layer formed thereon; a patterned insulating layer disposed on the gate layer, wherein the patterned insulating layer comprises a first contact region and a second contact region; a diamond rod disposed on the patterned insulating layer, wherein a first end of the diamond rod connects to the first contact region, and a second end of the diamond rod connects to the second contact region; a first electrode corresponding to the first contact region of the patterned insulating layer, and covering the first end of the diamond rod; and a second electrode corresponding to the second contact region of the patterned insulating layer, and covering the second end of the diamond rod, and a method for manufacturing the same.

Abstract: Hybrid semiconductor devices including a PIN diode portion and a Schottky diode portion are provided. The PIN diode portion is provided on a semiconductor substrate and has an anode contact on a first surface of the semiconductor substrate. The Schottky diode portion is also provided on the semiconductor substrate and includes a polysilicon layer on the semiconductor substrate and a ohmic contact on the polysilicon layer. Related Schottky diodes are also provided herein.

Abstract: A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.

Abstract: A Schottky barrier diode comprises a doped guard ring having a doping of a second conductivity type in a semiconductor-on-insulator (SOI) substrate. The Schottky barrier diode further comprises a first-conductivity-type-doped semiconductor region having a doping of a first conductivity type, which is the opposite of the second conductivity type, on one side of a dummy gate electrode and a Schottky barrier structure surrounded by the doped guard ring on the other side. A Schottky barrier region may be laterally surrounded by the dummy gate electrode and the doped guard ring. The doped guard ring includes an unmetallized portion of a gate-side second-conductivity-type-doped semiconductor region having a doping of a second conductivity type. A Schottky barrier region may be laterally surrounded by a doped guard ring including a gate-side doped semiconductor region and a STI-side doped semiconductor region. Design structures for the inventive Schottky barrier diode are also provided.

Abstract: A semiconductor device includes a first semiconductor layer and a second semiconductor layer of opposite conductivity type, a first epitaxial layer of the first conductivity type formed on sidewalls of the trenches, and a second epitaxial layer of the second conductivity type formed on the first epitaxial layer where the second epitaxial layer is electrically connected to the second semiconductor layer. The first epitaxial layer and the second epitaxial layer form parallel doped regions along the sidewalls of the trenches, each having uniform doping concentration. The second epitaxial layer has a first thickness and a first doping concentration and the first epitaxial layer and a mesa of the first semiconductor layer together having a second thickness and a second average doping concentration where the first and second thicknesses and the first doping concentration and second average doping concentrations are selected to achieve charge balance in operation.

Abstract: A semiconductor device includes a first conductivity-type semiconductor stack including the recesses which extend from a first principal surface toward a second principal surface and have bottoms not reaching the second principal surface, the second conductivity-type anode regions which are embedded at a distance from one another in the first principal surface, each of which has a part of an outer edge region exposed to a side surface of the corresponding recess, an anode electrode which is provided on the first principal surface of the semiconductor stack to form a Schottky barrier junction with the semiconductor stack in a region where the plurality of anode regions are not formed and form ohmic junctions with the anode regions; and a cathode electrode provided on the second principal surface of the semiconductor stack.

Abstract: A compound semiconductor device is provided with a substrate, an AlN layer formed over the substrate, an AlGaN layer formed over the AlN layer and larger in electron affinity than the AlN layer, another AlGaN layer formed over the AlGaN layer and smaller in electron affinity than the AlGaN layer. Furthermore, there are provided an i-GaN layer formed over the latter AlGaN layer, and an i-AlGaN layer and an n-AlGaN layer formed over the i-GaN layer.

Abstract: A switching element that includes a first semiconductor layer, the first semiconductor layer having a first portion and a second portion; a second semiconductor layer, the second semiconductor layer having a first portion and a second portion; an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction; a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction, wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts.

Abstract: A Schottky diode and a method for making one. The method includes the following steps: providing a semiconductor base body, preferably in the form of a wafer, having a high dopant concentration and having a first main surface, which forms the first electrical contact surface of the Schottky diode; epitaxially depositing a semiconductor layer having the same conductivity and a lower dopant concentration on that surface of the semiconductor base body which lies opposite the first main surface; arranging a first metal layer on the semiconductor layer with the formation of a Schottky contact between the first metal layer and the semiconductor layer; connecting a planar contact body to the first metal layer by means of a connecting means; forming at least one individual Schottky diode; and arranging a passivation layer in the edge region of the at least one Schottky diode.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, a plurality of second semiconductor regions of a second conductivity type, a third semiconductor region of the second conductivity type and a first electrode. The second regions are provided separately on a first major surface side of the first layer. The third region is provided on the first major surface side of the first layer so as to surround the second regions. The first electrode is provided on the first layer and the second regions. The first layer has a first portion and a second portion. The second portion has a lower resistivity than the first portion. The second portion is provided between the second regions and between the first portion and the first major surface and is provided outside the third region and between the first portion and the first major surface.

Abstract: A diode includes an organic composite plate, a first electrode and a second electrode. The organic composite plate includes a first portion, a second portion and a plurality of carbon nanotubes distributed therein. The carbon nanotubes in the first portion have a first band gap and the carbon nanotubes in the second portion have a second band gap. The first band gap and the second band gap are different from each other. The first electrode is electrically connected to the first portion. The second electrode electrically is connected to the second portion.

Abstract: A field-effect transistor has at least one electrode disposed independently of source and drain electrodes and in direct contact with the surface of a semiconductor channel to form a schottky barrier, so that it is possible to easily control the schottky barrier.

Abstract: A trench Schottky diode and a manufacturing method thereof are provided. A plurality of trenches are formed in Asemiconductor substrate. A plurality of doped regions are formed in the semiconductor substrate and under some of the trenches. A gate oxide layer is formed on a surface of the semiconductor substrate and the surfaces of the trenches. A polysilicon structure is formed on the gate oxide layer. Then, the polysilicon structure is etched, so that the gate oxide layer within the trenches is covered by the polysilicon structure. Then, a mask layer is formed to cover the polysilicon structure within a part of the trenches and a part of the gate oxide layer, and the semiconductor substrate uncovered by the mask layer is exposed. Afterwards, a metal sputtering layer is formed to cover a part of the surface of the semiconductor substrate.

Abstract: A Schottky diode with high antistatic capability has an N? type doped drift layer formed on an N+ type doped layer. The N? type doped drift layer has a surface formed with a protection ring. Inside the protection ring is a P-type doped area. The N? type doped drift layer surface is further formed with an oxide layer and a metal layer. The contact region between the metal layer and the N? type doped drift layer and the P-type doped area forms a Schottky contact. The P-type doped area has a low-concentration lower layer and a high-concentration upper layer, so that the surface ion concentration is high in the P-type doped area. The Schottky diode thus has such advantages of lowered forward voltage drop and high antistatic capability.

Abstract: A Schottky diode with a low forward voltage drop has an N? type doped drift layer formed on an N+ type doped layer. The N? type doped drift layer has a first surface with a protection ring inside which is a P-type doped area. The N? type doped drift layer surface is further formed with an oxide layer and a metal layer. The contact region between the metal layer and the N? type doped drift layer and the P-type doped area forms a Schottky barrier. The height of the Schottky barrier is lower than the surface of the N? type doped drift layer, thereby reducing the thickness of the N? type doped drift layer under the Schottky barrier. This configuration reduces the forward voltage drop of the Schottky barrier.

Abstract: An integrated circuit including a Schottky diode, and a method of making the same. The diode includes an active region bordered by an isolation region in a semiconductor substrate of the integrated circuits, a first electrode having a metal contact provided on a surface of the active region, and a second electrode having a silicide contact also provided on the surface of the active region.

Abstract: A switching element that includes a first semiconductor layer, the first semiconductor layer having a first portion and a second portion; a second semiconductor layer, the second semiconductor layer having a first portion and a second portion; an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction; a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction, wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts.

Abstract: A Schottky diode device is provided, including a p-type semiconductor structure. An n drift region is disposed over the p-type semiconductor structure, wherein the n drift region comprises first and second n-type doping regions having different n-type doping concentrations, and the second n-type doping region is formed with a dopant concentration greater than that in the first n-type doping region. A plurality of isolation structures is disposed in the second n-type doping region of the n drift region, defining an anode region and a cathode region. A third n-type doping region is disposed in the second n-type doping region exposed by the cathode region. An anode electrode is disposed over the first n-type doping region in the anode region. A cathode electrode is disposed over the third n-type doping region in the cathode region.

Abstract: An electronic device includes a silicon carbide drift region having a first conductivity type, a Schottky contact on the drift region, and a plurality of junction barrier Schottky (JBS) regions at a surface of the drift region adjacent the Schottky contact. The JBS regions have a second conductivity type opposite the first conductivity type and have a first spacing between adjacent ones of the JBS regions. The device further includes a plurality of surge protection subregions having the second conductivity type. Each of the surge protection subregions has a second spacing between adjacent ones of the surge protection subregions that is less than the first spacing.

Abstract: Disclosed are semiconductor devices with breakdown voltages that are more controlled and stable after repeated exposure to breakdown conditions than prior art devices. The disclosed devices can be used to provide secondary circuit functions not previously contemplated by the prior art.

Abstract: A portion of a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate is patterned into a semiconductor fin having substantially vertical sidewalls. A portion of a body region of the semiconductor fin is exposed on a top surface of the semiconductor fin between two source regions having a doping of a conductivity type opposite to the body region of the semiconductor fin. A metal semiconductor alloy portion is formed directly on the two source regions and the top surface of the exposed body region between the two source regions. The doping concentration of the exposed top portion of the body region may be increased by ion implantation to provide a low-resistance contact to the body region, or a recombination region having a high-density of crystalline defects may be formed. A hybrid surface semiconductor-on-insulator (HSSOI) metal-oxide-semiconductor-field-effect-transistor (MOSFET) thus formed has a body region that is electrically tied to the source region.

Abstract: The present invention provides a multi-finger structure of a SiGe heterojunction bipolar transistor (HBT). It is consisted of plural SiGe HBT single cells. The multi-finger structure is in a form of C/BEBC/BEBC/.../C, wherein, C, B, E respectively stands for collector, base and emitter; CBEBC stands for a SiGe HBT single cell. The collector region is consisted of an n type ion implanted layer inside the active region. The bottom of the implanted layer is connected to two n type pseudo buried layers. The two pseudo buried layers are formed through implantation to the bottom of the shallow trenches that surround the collector active region. Two collectors are picked up by deep trench contact through the field oxide above the two pseudo buried layers. The present invention can reduce junction capacitance, decrease collector electrode output resistance, and improve device frequency characteristics.

Abstract: A semiconductor system having a trench MOS barrier Schottky diode is described, including an n-type epitaxial layer, in which at least two etched trenches are located in a two-dimensional manner of presentation on an n+-type substrate which acts as the cathode zone. An electrically floating, p-type layer, which acts as the anode zone of the p-n type diode, is located in the n-type epitaxial layer, at least in a location below the trench bottom. An oxide layer is located between a metal layer and the surface of the trenches. The n-type epitaxial layer may include two n-type layers of different doping concentrations.

Abstract: To achieve a further reduction in the size of a finished product by reducing the number of externally embedded parts, the embedding of a Schottky barrier diode which is relatively large in the amount of current in a semiconductor integrated circuit device has been pursued. In such a case, it is general practice to densely arrange a large number of contact electrodes in a matrix over a Schottky junction region. It has been widely performed to perform a sputter etching process with respect to the surface of a silicide layer at the bottom of each contact hole before a barrier metal layer is deposited. However, in a structure in which electrodes are thus arranged over a Schottky junction region, a reverse leakage current in a Schottky barrier diode is varied by variations in the amount of sputter etching. The present invention is a semiconductor integrated circuit device having a Schottky barrier diode in which contact electrodes are arranged over a guard ring in contact with a peripheral isolation region.

Abstract: A mesa edge shielding trench Schottky rectifier includes a semiconductor substrate; an epitaxial layer grown on the first surface of the semiconductor substrate; a plurality of trenches spaced from each other and extended into the epitaxial layer, wherein an epitaxial region between two adjacent trenches forms the silicon mesa; a polysilicon region, having a T-shape, is separated from an inner wall of each of the trenches and a top surface of the epitaxial layer by an oxide layer, wherein a width of the top surface of the polysilicon region is bigger than an open size of each of the trenches; an anode electrode, deposited on an entire structure, forming an ohmic contact on the top surface of the polysilicon region and a Schottky contact on an exposed surface of the epitaxial layer; and a cathode electrode, deposited on the second surface of the semiconductor substrate, forming an ohmic contact thereon.

Abstract: A diode has a semiconductor layer and cathode and anode electrodes on a surface of the semiconductor layer. The semiconductor layer has cathode and anode regions respectively contacting the cathode and anode electrodes. The anode region has a first diffusion region having high surface concentration, a second diffusion region having intermediate surface concentration, and a third diffusion region having low surface concentration. The first diffusion region is covered with the second and third diffusion regions. The second diffusion region has a first side surface facing the cathode region, a second side surface opposite to the cathode region, and a bottom surface extending between the first and second side surfaces. The third diffusion region covers at least one of the first corner part connecting the first side surface with the bottom surface and the second corner part connecting the second side surface with the bottom surface.

Abstract: A schottky diode includes a drift region of a first conductivity type and a lightly doped silicon region of the first conductivity type in the drift region. A conductor layer is over and in contact with the lightly doped silicon region to form a schottky contact with the lightly doped silicon region. A highly doped silicon region of the first conductivity type is in the drift region and is laterally spaced from the lightly doped silicon region such that upon biasing the schottky diode in a conducting state, a current flows laterally between the lightly doped silicon region and the highly doped silicon region through the drift region. A plurality of trenches extend into the drift region perpendicular to the current flow. Each trench has a dielectric layer lining at least a portion of the trench sidewalls and at least one conductive electrode.

Abstract: The present invention provides for nanostructures grown on a conducting or insulating substrate, and a method of making the same. The nanostructures grown according to the claimed method are suitable for interconnects and/or as heat dissipators in electronic devices.

Abstract: A method for manufacturing an integrated circuit structure is disclosed. First, a dielectric layer is formed on a substrate, the substrate has a transistor region and a diode region. Next, a contact hole and an opening are formed in the dielectric layer, a size of the opening being larger than that of the contact hole. Next, a first metal layer is formed on the dielectric layer and filled into the contact hole and the opening. Next, a portion of the first metal layer is removed to form a contact plug above the transistor region and form a metal spacer on a sidewall of the opening. Next, an ion implantation process is performed to form a lightly doped region in the substrate at a bottom of the opening. Finally, a contact metal layer is formed on the lightly doped region.

Abstract: A semiconductor structure may include a semiconductor bulk region with a gate stack on the semiconductor bulk region. The source region and the drain region in the semiconductor bulk region may be located on opposing sides of a channel region below the gate stack. An interfacial layer coupled to the channel region may modify a workfunction of a metal-semiconductor contact. In a MOSFET, the metal-semiconductor contact may be between a metal contact and the source region and the drain region. In a Schottky barrier-MOSFET, the metal-semiconductor contact may be between a silicide region in the source region and/or the drain region and the channel region. The interfacial layer may use a dielectric-dipole mitigated scheme and may include a conducting layer and a dielectric layer. The dielectric layer may include lanthanum oxide or aluminum oxide used to tune the workfunction of the metal-semiconductor contact.

Abstract: An intermediate metal film is formed between a Schottky electrode and a pad electrode. A Schottky barrier height between the intermediate metal film and a silicon carbide epitaxial film is equivalent to or higher than a Schottky barrier height between the Schottky electrode and the silicon carbide epitaxial film. By this configuration, an excess current and a leak current through a pin-hole can be suppressed even in the case in which a Schottky barrier height between the pad electrode and the silicon carbide epitaxial film is less than the Schottky barrier height between the Schottky electrode and the silicon carbide epitaxial film.

Abstract: A semiconductor device is obtained, in which excellent characteristics are achieved, the reliability is improved, and an SiC wafer can also be used for the fabrication. A plurality of Schottky-barrier-diode units 10 is formed on an SiC chip 9, and each of the units 10 has an external output electrode 4 independently of each other. Bumps 11 (the diameter is from several tens to several hundreds of ?m) are formed only on the external output electrodes 4 of non-defective units among the units 10 formed on the SiC chip 9, meanwhile bumps are not formed on the external output electrodes 4 of defective units in which the withstand voltage is too low, or the leakage current is too much.