Abstract: A method for forming a gate structure of a 3D memory device is provided. The method comprises forming an array wafer including a periphery region and a staircase and array region. A process of forming the array wafer comprises forming an etch stop layer on a first substrate in the periphery region, forming an array device on the first substrate in the staircase and array region, and forming at least one first vertical through in the periphery region and in contact with the etch stop layer. The method further comprises forming a CMOS wafer, and bonding the array wafer and the CMOS wafer. The method further comprises forming at least one through substrate contact penetrating the first substrate and the etch stop layer, and in contact with the at least one first vertical through contact.

Abstract: A diode is disclosed. The diode includes a semiconductor substrate, a hard mask formed above the substrate, vertically oriented components of a first material adjacent sides of the hard mask, and laterally oriented components of the first material on top of the hard mask. The laterally oriented components are oriented in a first direction and a second direction. The diode also includes a second material on top of the first material. The second material forms a Schottky barrier.

Abstract: The present invention relates to an optoelectronic sensor used with light curtains for monitoring a sensing field. The optoelectronic sensor includes at least one optical unit having at least one radiation emitting element and at least one radiation receiving element and a control unit for processing an output signal generated by said radiation receiving element and for generating a defined sensor signal based on the output signal. The optical unit has a diagnostic unit including a monitoring unit operable to monitor at least one parameter indicative of an operational status of the optical unit. The diagnostic unit includes a processing unit operable to generate a communication signal indicative of said operational status, and the diagnostic unit is arranged in a separately housed, detachable plug-in module. The processing unit comprises a wireless communication interface for wirelessly receiving and transmitting communication signals.

Abstract: A switching device including: a body of semiconductor material, which has a first conductivity type and is delimited by a front surface; a contact layer of a first conductive material, which extends in contact with the front surface; and a plurality of buried regions, which have a second conductivity type and are arranged within the semiconductor body, at a distance from the contact layer.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type, an impurity region of a second conductivity type formed in a surface layer portion of the semiconductor layer, a terminal region of the second conductivity type that is formed in the surface layer portion of the semiconductor layer along a peripheral edge of the impurity region and that has a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the impurity region, and a surface electrode that is formed on the semiconductor layer and that has a connection portion connected to the impurity region and to the terminal region.

Abstract: A power conversion circuit includes: a MOSFET having a super junction structure; an inductive load; and a freewheel diode. A switching frequency of the MOSFET is 10 kHz or more. When the MOSFET is turned off, a first period during which a drain current decreases, a second period during which the drain current increases, and a third period during which the drain current decreases again appear in this order. The freewheel diode is an Si-FRD or an SiC-SBD, and current density obtained by dividing a current value of the forward current by an area of an active region of the freewheel diode falls within a range of 200 A/cm2 to 400 A/cm2 when the freewheel diode is the Si-FRD, and the current density falls within a range of 400 A/cm2 to 1500 A/cm2 when the freewheel diode is the SiC-SBD.

Abstract: A semiconductor device is disclosed. In a surface layer of a front surface of an n-type semiconductor substrate, an anode layer is provided in an element activation portion and an annular p-type guard ring and an n-type high-concentration surface region are provided in an annular termination breakdown voltage region which surrounds the outer circumference of the anode layer. The impurity concentration of the n-type high-concentration surface region is higher than that of the semiconductor substrate and is lower than that of the p-type guard ring. The depth of the n-type high-concentration surface region is less than that of the guard ring. The anode layer and the guard ring are formed while the oxygen concentration of the semiconductor substrate is set to be equal to or more than 1×1016/cm3 and equal to or less than 1×1018/cm3.

Abstract: A hetero-junction Schottky diode device includes a buffer layer, at least one channel layer, at least one barrier layer and a Schottky metal layer. The buffer layer is disposed on a substrate. The at least one channel layer is disposed on the buffer layer. The at least one barrier layer is disposed on the at least one channel layer. Besides, multiple strip openings are configured to penetrate through the at least one barrier layer and at least one channel layer. The Schottky metal layer is disposed on the at least one barrier layer, across the strip openings and fills in the strip openings.

Abstract: A method for manufacturing a semiconductor device includes forming a first well region in a semiconductor substrate, forming isolation structures on the semiconductor substrate, and forming second well regions and a third well region in the first well region, wherein the second well regions are isolated from the third well region by the isolation structures, and two of the adjacent second well regions have a first distance between them. The method also includes performing a rapid thermal annealing process to shorten the first distance to a second distance. The method further includes forming first barrier metal layers on the first well region and covering the second well regions, forming a second barrier metal layer on the first well region and covering the third well region, forming first electrodes on the first barrier metal layers, and forming a second electrode on the second barrier metal layer.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate, a well region on the semiconductor substrate, a radio frequency circuit, a first guard ring adjacent to the RF circuit, and a first isolation region directly disposed between the RF circuit and the first guard ring. The well region has a first conductive type. The RF circuit includes a FIN field-effect transistor having a plurality of first fins and a plurality of first polys on the well region, wherein the first polys are perpendicular to the first fins. The first guard ring includes a plurality of second fins and a pair of second polys on the well region, wherein the second polys are perpendicular to the second fins. The first fins are arranged parallel to the second fins, and the first fins are separated from the second fins by the first isolation region.

Abstract: A low capacitance transient voltage suppressor is disclosed. The transient voltage suppressor comprises a first diode with a first anode thereof coupled to an I/O port. A first cathode of the first diode and a second cathode of a second diode are respectively coupled to two ends of a resistor. A second anode of the second diode is coupled to a low-voltage terminal. A third anode and a third cathode of a third diode are respectively coupled to the second cathode and the resistor. The third diode induces a third parasitic capacitance smaller than a first capacitance of the first diode and a second parasitic capacitance of the second diode, and the third parasitic capacitance in series with the first and second parasitic capacitances dominate a small capacitance in a path during normal operation.

Abstract: The disclosed technology relates to a device including a diode. In one aspect, the device includes a lower group III metal nitride layer and an upper group III metal nitride layer and a heterojunction formed therebetween, where the heterojunction extends horizontally and is configured to form a two-dimensional electron gas (2DEG) that is substantially confined in a vertical direction and within the lower group III metal nitride layer. The device additionally includes a cathode forming an ohmic contact with the upper group III metal nitride layer. The device additionally includes an anode, which includes a first portion that forms a Schottky barrier contact with the upper group III metal nitride layer, and a second portion that is separated vertically from the upper group III metal nitride layer by a layer of dielectric material.

Abstract: A Schottky device includes a barrier height adjustment layer in a portion of a semiconductor material. In accordance with an embodiment, the Schottky device is formed from a semiconductor material of a first conductivity type which has a barrier height adjustment layer of a second conductivity type that extends from a first major surface of the semiconductor material into the semiconductor material a distance that is less than a zero bias depletion boundary. A Schottky contact is formed in contact with the doped layer.

Abstract: Edge termination structures for semiconductor devices are provided including a plurality of spaced apart concentric floating guard rings in a semiconductor layer that at least partially surround a semiconductor junction. The spaced apart concentric floating guard rings have a highly doped portion and a lightly doped portion. Related methods of fabricating devices are also provided herein.

Abstract: A Schottky diode comprising a cathode region, an anode region and a guard ring region, wherein the anode region may comprise a metal Schottky contact, and the guard ring region may comprise an outer guard ring and a plurality of inner open stripes inside the outer guard ring, and wherein the inner open stripes has a shallower junction depth than the outer guard ring.

Abstract: A Schottky barrier diode includes a first semiconductor layer, a LOCOS layer arranged in contact with the first semiconductor layer, a Schottky junction region provided on a contact surface between the first semiconductor layer and a first electrode, a second semiconductor layer connected to the first semiconductor layer and having a higher carrier concentration than that of the first semiconductor layer, and a second electrode forming an ohmic contact with the second semiconductor layer. In this case, the Schottky junction region and the LOCOS layer are in contact.

Abstract: A SiC junction barrier controlled Schottky rectifier includes a SiC substrate, a n-type drift layer, a p-type doping region, a plurality of junction field-effect regions, a first metal layer and a second metal layer. The drift layer is disposed on the SiC substrate. The junction field-effect regions are disposed in the drift layer and are surrounded by the p-type doping region. The first metal layer is disposed on the drift layer. The second metal layer is disposed at one side of the SiC substrate away from the drift layer. Through N circular regions and (N?1) inter-circle regions each connecting two of the circular regions, as well as geometric characteristics of the circular regions and the inter-circle regions, a leakage current of devices is effectively reduced and ruggedness is increased to improve an issue of a large leakage current of a conventional Schottky barrier diode.

Abstract: A semiconductor device includes a drain region, an epitaxial layer overlaying the drain region, and an active region. The active region includes: a body disposed in the epitaxial layer; a source embedded in the body; a gate trench extending into the epitaxial layer; a gate disposed in the gate trench; a contact trench extending through the source and at least part of the body; a contact electrode disposed in the contact trench; and an implant disposed at least in part along a contact trench wall; and an epitaxial enhancement portion disposed below the contact trench and in contact with the implant.

Abstract: A Schottky device includes a barrier height adjustment layer in a portion of a semiconductor material. In accordance with an embodiment, the Schottky device is formed from a semiconductor material of a first conductivity type which has a barrier height adjustment layer of a second conductivity type that extends from a first major surface of the semiconductor material into the semiconductor material a distance that is less than a zero bias depletion boundary. A Schottky contact is formed in contact with the doped layer.

Abstract: A Schottky barrier diode and a method of manufacturing the Schottky barrier diode are provided. The diode includes an n? type epitaxial layer disposed on a first surface of an n+ type silicon carbide substrate and having an upper surface, a lower surface, and an inclined surface that connects the upper surface and the lower surface. A p region is disposed on the inclined surface of the n? type epitaxial layer and a Schottky electrode is disposed on the upper surface of the n? type epitaxial layer and the p region. In addition, an ohmic electrode is disposed on a second surface of the n+ type silicon carbide substrate.

Abstract: Semiconductor Schottky barrier devices include a wide bandgap semiconductor layer, a Schottky barrier metal layer on the wide bandgap semiconductor layer and forming a Schottky junction, a current spreading layer on the Schottky barrier metal layer remote from the wide bandgap semiconductor layer and two or more diffusion barrier layers between the current spreading layer and the Schottky barrier metal layer. The first diffusion barrier layer reduces mixing of the current spreading layer and the second diffusion barrier layer at temperatures of the Schottky junction above about 300° C. and the second diffusion barrier layer reduces mixing of the first diffusion barrier layer and the Schottky barrier metal layer at the temperatures of the Schottky junction above about 300° C.

Abstract: A schottky barrier diode may include a first n? type epitaxial layer disposed on a first surface of an n+ type silicon carbide substrate, a first p+ region disposed in the first n? type epitaxial layer, a second n type epitaxial layer disposed on the first n? type epitaxial layer and the first p+ region, a second p+ region disposed in the second n type epitaxial layer, a schottky electrode disposed on the second n type epitaxial layer and the second p+ region, and an ohmic electrode disposed on a second surface of the n+ type silicon carbide substrate, wherein the first p+ region and the second p+ region may be in contact with each other.

Abstract: Provided is a rectifier such as a detector in which a cutoff frequency may be increased in a view point different from the reduction in size of the structure. The rectifier includes: a Schottky barrier portion including a Schottky electrode; a barrier portion having a rectifying property with respect to a majority carrier in the Schottky barrier portion; and an ohmic electrode in electrical contact with the barrier portion having the rectifying property, in which each of the Schottky barrier portion and the barrier portion having the rectifying property has an asymmetrical band profile whose gradient on one side is larger than a gradient of another side, and the Schottky barrier portion and the barrier portion having the rectifying property are connected to each other so that the steep gradient side of the band profile is located on a side of the Schottky electrode.

Abstract: A power switching module includes a three-terminal power semiconductor device designed for a rated current and a freewheeling unit. The freewheeling unit includes a pn-diode integrated in a first semiconductor material having a first band-gap, and a Schottky-diode integrated in a second semiconductor material having a second band-gap that is larger than the first band-gap. The Schottky-diode is electrically connected in parallel to the pn-diode.

Abstract: A method of making an integrated circuit including forming a seal ring structure around a circuit where the seal ring structure has a first portion and a tilted portion. The first portion of the seal ring structure is substantially parallel with an edge of the circuit. The tilted portion of the seal ring structure forms an obtuse angle with the first portion. The method further includes forming a first pad which is electrically coupled with the seal ring structure. The method further includes disposing a leakage current test structure in an area enclosed by the seal ring where at least one portion of the leakage current test structure is substantially parallel with the tilted portion of the seal ring structure. The method further includes forming a second pad which is electrically coupled with the leakage current test structure.

Abstract: A Schottky diode includes a Schottky barrier and a plurality of dopant regions disposed near the Schottky barrier as floating islands to function as PN junctions for preventing a leakage current generated from a reverse voltage. At least a trench opened in a semiconductor substrate with a Schottky barrier material disposed therein constitutes the Schottky barrier. The Schottky barrier material may also be disposed on sidewalls of the trench for constituting the Schottky barrier. The trench may be filled with the Schottky barrier material composed of Ti/TiN or a tungsten metal disposed therein for constituting the Schottky barrier. The trench is opened in a N-type semiconductor substrate and the dopant regions includes P-doped regions disposed under the trench constitute the floating islands. The P-doped floating islands may be formed as vertical arrays under the bottom of the trench.

Abstract: A semiconductor device and an operating method for the same are provided. The semiconductor structure comprises a first doped region, a second doped region, a third doped region, a fourth doped region and a first gate structure. The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity. The first doped region is surrounded by the second doped region. The third doped region has the first type conductivity. The fourth doped region has the second type conductivity. The first gate structure is on the second doped region. The third doped region and the fourth doped region are in the second doped region and the first doped region on opposing sides of the first gate structure respectively.

Abstract: A downsized semiconductor device having an excellent reverse characteristic, and a method of manufacturing the semiconductor device is sought to improve. The semiconductor device comprises a semiconductor body having a polygonal contour. An active area is formed in the semiconductor body. An EQR electrode is formed so as to surround the active area and to have curved portions of the EQR electrode along the corners of the semiconductor body. An interlayer insulating film is formed to cover the active area and the EQR electrode. The EQR electrode is embedded in the interlayer insulating film around the active area. EQR contacts are in contact with the curved portions of the EQR electrode and the semiconductor body outside the curved portions, and have at least side walls covered with the interlayer insulating film.

Abstract: An electronic device includes a silicon carbide layer including an n-type drift region therein, a contact forming a junction, such as a Schottky junction, with the drift region, and a p-type junction barrier region on the silicon carbide layer. The p-type junction barrier region includes a p-type polysilicon region forming a P-N heterojunction with the drift region, and the p-type junction barrier region is electrically connected to the contact. Related methods are also disclosed.

Abstract: In one surface of a semiconductor substrate, an active region in which main current flows and an IGBT is disposed is formed. A termination structure portion serving as an electric-field reduction region is formed laterally with respect to the active region. In the termination structure portion, a porous-oxide-film region, a p-type guard ring region, and an n+-type channel stopper region are formed. A plurality of floating electrodes are formed to contact the surface of the porous-oxide-film region. Another plurality of floating electrodes are formed to contact a first insulating film.

Abstract: A superjunction device and methods for layout design and fabrication of a superjunction device are disclosed. A layout of active cell column structures can be configured so that a charge due to first conductivity type dopants balances out charge due to second conductivity type dopants in a doped layer in an active cell region. A layout of end portions of the active cell column structures proximate termination column structures can be configured so that a charge due to the first conductivity type dopants in the end portions and a charge due to the first conductivity type dopants in the termination column structures balances out charge due to the second conductivity type dopants in a portion of the doped layer between the termination column structures and the end portions.

Abstract: A semiconductor device that can achieve a high-speed operation at a time of switching, and the like. The semiconductor device includes: a p-type buried layer buried within an n?-type semiconductor layer; and a p-type surface layer formed in a central portion of each of cells. In a contact cell, the p-type buried layer is in contact with the p-type surface layer. The semiconductor device further includes: a p+-type contact layer formed on the p-type surface layer of the contact cell; and an anode electrode provided on the n?-type semiconductor layer. The anode electrode forms a Schottky junction with the n?-type semiconductor layer and forms an ohmic junction with the p+-type contact layer.

Abstract: A third insulating layer is formed in a periphery region of a substrate over a first surface (main surface) of the substrate so as to straddle a second semiconductor layer closest to a guard ring layer and a second semiconductor layer closest to the second semiconductor layer. In other words, the third insulating layer is formed to cover a portion of the first semiconductor layer, which is exposed to the first surface (main surface) of the substrate and which is between the second semiconductor layers. Thereby, the third insulating layer electrically insulates the metal layer from the portion of the first semiconductor layer, which is exposed to the first surface (main surface) of the substrate and which is between the second semiconductor layers.

Abstract: A semiconductor structure includes a III-nitride substrate characterized by a first conductivity type and having a first side and a second side opposing the first side, a III-nitride epitaxial layer of the first conductivity type coupled to the first side of the III-nitride substrate, and a plurality of III-nitride epitaxial structures of a second conductivity type coupled to the III-nitride epitaxial layer. The semiconductor structure further includes a III-nitride epitaxial formation of the first conductivity type coupled to the plurality of III-nitride epitaxial structures, and a metallic structure forming a Schottky contact with the III-nitride epitaxial formation and coupled to at least one of the plurality of III-nitride epitaxial structures.

Abstract: Methods and apparatus for ESD structures. A semiconductor device includes a first active area containing an ESD cell coupled to a first terminal and disposed in a well; a second active area in the semiconductor substrate, the second active area comprising a first diffusion of the first conductivity type for making a bulk contact to the well; and a third active area in the semiconductor substrate, separated from the first and second active areas by another isolation region, a portion of the third active area comprising an implant diffusion of the first conductivity type within a first diffusion of the second conductivity type and adjacent a boundary with the well of the first conductivity type; wherein the third active area comprises a diode coupled to the terminal and reverse biased with respect to the well of the first conductivity type.

Abstract: A chip-scale schottky package which has at least one cathode electrode and at least one anode electrode disposed on only one major surface of a die, and solder bumps connected to the electrode for surface mounting of the package on a circuit board.

Abstract: A trench Schottky rectifier device includes a substrate having a first conductivity type, a plurality of trenches formed in the substrate, and an insulating layer formed on sidewalls of the trenches. The trenches are filled with conductive structure. There is an electrode overlying the conductive structure and the substrate, and thus a Schottky contact forms between the electrode and the substrate. A plurality of embedded doped regions having a second conductivity type are formed in the substrate and located under the trenches. Each doped region and the substrate form a PN junction to pinch off current flowing toward the Schottky contact so as to suppress current leakage.

Abstract: A Schottky diode includes a deep well formed in a substrate, an isolation layer formed in the substrate, a first conductive type guard ring formed in the deep well along an outer sidewall of the isolation layer and located at a left side of the isolation layer, a second conductive type well formed in the deep well along the outer sidewall of the isolation layer and located at a right side of the isolation layer, an anode electrode formed over the substrate and coupled to the deep well and the guard ring, and a cathode electrode formed over the substrate and coupled to the well. A part of the guard ring overlaps the isolation layer.

Abstract: Schottky barrier diodes, methods for fabricating Schottky barrier diodes, and design structures for a Schottky barrier diode. A guard ring for a Schottky barrier diode is formed with a selective epitaxial growth process. The guard ring for the Schottky barrier diode and an extrinsic base of a vertical bipolar junction diode on a different device region than the Schottky barrier diode may be concurrently formed using the same selective epitaxial growth process.

Abstract: A method of making an edge-reinforced microelectronic element is disclosed. The steps include mechanically cutting along dicing lanes of a substrate at least partially through a thickness thereof to form a plurality of edge surfaces extending away from a front surface thereof and forming a continuous monolithic metallic edge-reinforcement ring that covers each of the plurality of edge surfaces and extends onto the front surface. The front surface may have a plurality of contacts thereat and the substrate may embody a plurality of microelectronic elements.

Abstract: The present invention aims to enhance the reliability of a semiconductor device equipped with a Schottky barrier diode within the same chip, and its manufacturing technology. The semiconductor device includes an n-type n-well region formed over a p-type semiconductor substrate, an n-type cathode region formed in part thereof and higher in impurity concentration than the n-well region, a p-type guard ring region formed so as to surround the n-type cathode region, an anode conductor film formed so as to integrally cover the n-type cathode region and the p-type guard ring region and to be electrically coupled thereto, n-type cathode conduction regions formed outside the p-type guard ring region with each separation portion left therebetween, and a cathode conductor film formed so as to cover the n-type cathode conduction regions and to be electrically coupled thereto. The anode conductor film and the n-type cathode region are Schottky-coupled to each other.

Abstract: A semiconductor structure is proposed. A third well is formed between a first well and a second well. A first doped region and a second doped region are formed in a surface of the third well. A third doped region is formed between the first doped region and the second doped region. A fourth doped region is formed in a surface of the first well. A fifth doped region is formed in a surface of the second well. A first base region and a second base region are respectively formed in surfaces of the first well and the second well. A first Schottky barrier is overlaid on a part of the first base region and the first doped region. A second Schottky barrier is overlaid on a part of the second base region and the second doped region.

Abstract: A semiconductor device has a field insulating film provided on a semiconductor substrate, and a fuse provided on the field insulating film and having a fuse trimming laser irradiation portion and fuse terminals. The semiconductor device further includes an intermediate insulating film covering the fuse, a first TEOS layer on the intermediate insulating film, an SOG layer for planarizing the first TEOS layer, a second TEOS layer on the SOG layer and on the first TEOS layer, a protective film on the second TEOS layer, and an opening portion above the fuse trimming laser irradiation portion in a region from the protective film to the first TEOS layer. A seal ring is provided on the intermediate insulating film so as to surround the opening portion. The seal ring is disposed over the fuse so as to overlap each of the fuse terminals in plan view.

Abstract: A power diode is disclosed wherein it is possible to lower on-voltage by expanding a conducting region at an on time. By applying negative voltage to a plate electrode when turning on a power diode, an inversion layer is formed in a front surface layer of an n drift region sandwiched between a p guard ring region and a p anode region, and the p guard ring region and p anode region are connected by the inversion layer, thereby causing one portion or all of the p guard ring region to function as an active region together with the anode region, and expanding an energization region, thus lowering on-voltage.

Abstract: A termination structure for a nitride-based Schottky diode includes a guard ring formed by an epitaxially grown P-type nitride-based compound semiconductor layer and dielectric field plates formed on the guard ring. The termination structure is formed at the edge of the anode electrode of the Schottky diode and has the effect of reducing electric field crowding at the anode electrode edge, especially when the Schottky diode is reverse biased. In one embodiment, the P-type epitaxial layer includes a step recess to further enhance the field spreading effect of the termination structure.

Abstract: A semiconductor device comprises a substrate, a cathode, an outer ring, an anode, an electrically insulating layer, and an electrically conducting layer. The substrate includes a semiconducting material having a first conduction type. The substrate has a first face and a second face substantially parallel to the first face. A cathode is disposed at the second face and has the first conduction type. An outer ring, having the first conduction type, is disposed at an outer perimeter of the first face of the substrate. An anode, having the second conduction type, is disposed at the first face of the substrate within an inner perimeter of the outer ring. An electrically insulating layer is disposed over the outer ring. An electrically conducting layer is disposed over the electrically insulating layer and over the outer ring. The electrically conducting layer electrically is insulated from the outer ring by the electrically insulating layer.

Abstract: A Schottky junction diode device having improved performance and a multiple well structure is fabricated in a conventional CMOS process. A substrate including a material doped to a first conductivity type is formed. A first well is disposed over the substrate. The first well includes a material doped differently, such as to a second conductivity type opposite that of the first conductivity type. A second well is disposed within the first well. A region of metal-containing material is disposed in the second well to form a Schottky junction at an interface between the region of metal-containing material and the second well. In one embodiment, a second well contact is disposed in a portion of the second well.

Abstract: A method for fabricating an edge termination structure includes providing a substrate having a first surface and a second surface and a first conductivity type, forming a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the substrate, and forming a second GaN epitaxial layer of a second conductivity type opposite to the first conductivity type. The second GaN epitaxial layer is coupled to the first GaN epitaxial layer. The method also includes implanting ions into a first region of the second GaN epitaxial layer to electrically isolate a second region of the second GaN epitaxial layer from a third region of the second GaN epitaxial layer. The method further includes forming an active device coupled to the second region of the second GaN epitaxial layer and forming the edge termination structure coupled to the third region of the second GaN epitaxial layer.

Abstract: The present invention discloses a Schottky diode. The Schottky diode comprises a cathode region, an anode region and a guard ring region. The anode region may comprise a metal Schottky contact. The guard ring region may comprise an outer guard ring and a plurality of inner guard stripes inside the outer guard ring. And wherein the inner guard stripe has a shallower junction depth than the outer guard ring.

Abstract: A high-voltage Schottky diode and a manufacturing method thereof are disclosed in the present disclosure. The diode includes: a P-type substrate and two N-type buried layers, a first N-type buried layer is located below a cathode lead-out area, and a second N-type buried layer is located below a cathode region; an epitaxial layer; two N-type well regions located on the epitaxial layer, a first N-type well region is a lateral drift region and it is provided with a cathode lead-out region, and a second N-type well region is located on the second N-type buried layer and it is a cathode region; a first P-type well region located on the second N-type buried layer and surrounding the cathode region; a field oxide isolation region located on the lateral drift region; an anode located on the cathode region and a cathode located on the surface of the cathode lead-out region.