Abstract: A Schottky device having a substrate layer of a first conductivity type having a surface, and a guard ring formed over the surface of the substrate layer and also surrounding a barrier region of the substrate layer. The guard ring has a gate of a second conductivity type disposed over a dielectric layer. A metal can be formed over the barrier region to form a Schottky junction.

Abstract: A semiconductor device has a guard ring in a multilayer interconnection structure, wherein the guard ring includes a conductive wall extending zigzag in a plane parallel with a principal surface of a substrate.

Abstract: The present invention includes a MOS device (100) that has a P-type substrate (102) and an N-type drain region (104) formed within the substrate (102). An annular N-type source region (106) generally surrounds the drain region (104). The source region (106) serves as both the source for the MOS device (100) and a sacrificial collector guard ring for an electrostatic discharge protection circuit. An annular gate region (110) generally surrounds the drain region (104) and is electrically insulated from the drain region (104) and electrically connected to the source region (106). An annular P-type bulk region (108) generally surrounds the source region (106) and is electrically connected to the source region (106).

Abstract: A power Schottky rectifier device and method of making the same are disclosed. The Schottky rectifier device including a LOCOS structure and two p-type doping regions, which are positioned one above another therein to isolate cells so as to avoid premature of breakdown voltage. The Schottky rectifier device comprises: an n? drift layer formed on an n+ substrate; a cathode metal layer formed on a surface of the n+ substrate opposite the n? drift layer; a pair of field oxide regions and termination region formed into the n? drift layer and each spaced from each other by the mesas, where the mesas have metal silicide layer formed thereon. A top metal layer formed on the field oxide regions and termination region and contact with the silicide layer.

Abstract: A semiconductor device having guard grooves uniformly filled with a semiconductor filler is provided. The four corners of a rectangular ring-shaped guard groove meet at right angles, and outer and inner auxiliary diffusion regions both rounded are connected to the four corners. Since the guard grooves do not have to be rounded, the plane orientation of a silicon single crystal exposed inside the guard grooves can be all {100}. Therefore, epitaxial growth in the guard grooves is uniformly carried out, and the grooves are filled with guard regions without defects.

Abstract: The invention relates to a vertical-type single-pole component, comprising regions (34) with a first type of conductivity (P) which are embedded in a thick layer (32) with a second type of conductivity (N). Said regions are distributed over at least one same horizontal level and are independent of each other. The regions also underlie an insulating material (70).

Abstract: A photodetector circuit incorporates an avalanche photodiode (APD) 300 produced by epitaxy on a CMOS substrate 302 with implanted n-well 304 and p-well 306. The n-well 304 has an implanted p+ guard ring 310 delimiting the APD 300. Within the guard ring 310 is an implanted n+ APD layer 312 upon which is deposited an epitaxial p+ APD layer 314, these layers forming the APD 300. The APD may be incorporated in an amplifier circuit 50 providing feedback to maintain constant bias voltage, and may include an SiGe absorption region to provide extended long wavelength response or lower avalanche voltage. Non-avalanche photodiodes may also be used.

Abstract: As etch-stop films or Cu-diffusion barrier films used in insulation films constituting conductor layers of a stacked structure, films having smaller dielectric constant than silicon nitride films are used, and an insulation film at a lower-layer part of the stacked structure is made to have smaller dielectric constant than that at an upper-layer part thereof, and further this insulation film is a silicon oxide (SiO) film and has in the interior thereof, nano-pores of from 0.05 nm or more to 4 nm or less in diameter as chief construction. This makes it possible to dramatically reduce effective dielectric constant while keeping the mechanical strength of the conductore layers themselves, and can materialize a highly reliable and high-performance semiconductor device having mitigated the wiring delay of signals which pass through wirings.

Abstract: A semiconductor device such as a photodetector has a substrate having an active region layer containing an active region of the device. A dielectric layer is disposed on the active region layer, and a metal active region contact is disposed in the dielectric layer above the active region and electrically contacting the active region. A metal electrostatic discharge (ESD)protection structure is disposed in the dielectric layer around the active region contact, wherein the ESD protection structure electrically contacts the active region layer of the substrate to provide an ESD discharge path for charge on the surface of the dielectric layer.

Abstract: A high withstand voltage semicnductor device does not show any significant fall of its withstand voltage if the impurity concentration of the RESURF layer of a low impurity concentration semiconductor region thereof varies from the optimal level and/or influenced by the fixed electric charge.

Abstract: A diode has a semiconductor layer of a first conductive type having a first principal plane and a second principal plane facing the first principal plane; a first impurity layer of a second conductive type which is opposite to said first conductive type, said first impurity layer being selectively formed on said first principal plane of said semiconductor layer; a second impurity layer of the first conductive type which is selectively formed on said first principal plane of said semiconductor layer apart from said first impurity layer; a first main electrode connected to said first impurity layer; a second main electrode connected to said second impurity layer; a third impurity layer of the first conductive type which is selectively formed on said second principal plane of said semiconductor layer and which is formed so as to face said first impurity layer; a fourth impurity layer of the second conductive type which is selectively formed on said second principal plane of said semiconductor layer and which is

Abstract: An integrated Schottky barrier diode chip includes a compound semiconductor substrate, a plurality of Schottky barrier diodes formed on the substrate and an insulating region formed on the substrate by an on implantation. The insulating region electrically separates a portion of a diode at a cathode voltage from a portion of the diode at an anode voltage. Because of the absence of a polyimide layer and trench structures, this planar device configuration results in simpler manufacturing method and improved device characteristics.

Abstract: An integrated circuit having very low parasitic current gain includes a guard ring that is used to completely surround a device, such as a power device, that induces parasitic current. The guard ring is formed in a semiconductor body layer such as an epitaxial layer and has a central guard ring of the same type conductivity as that of the body layer and additional flanking rings of the opposite type conductivity. An unbiased configuration of the guard ring based on the above structure is particularly effective in reducing the parasitic gain. The effectiveness of the guard ring, such as the high current performance, is further improved by reducing the resistance between neighboring rings using various methods.

Abstract: A Schottky rectifier includes a semiconductor structure having first and second opposing faces each extending to define an active semiconductor region and a termination semiconductor region. The semiconductor structure includes a cathode region of the first conductivity type adjacent the first face and a drift region of the first conductivity type adjacent the second face. The drift region has a lower net doping concentration than that of the cathode region. A plurality of trenches extends from the second face into the semiconductor structure and defines a plurality of mesas within the semiconductor structure. At least one of the trenches is located in each of the active and the termination semiconductor regions. A first insulating region is located adjacent the semiconductor structure in the plurality of trenches. A second insulating region electrically isolates the active semiconductor region from the termination semiconductor region.

Abstract: A diode (20), having first and second conductive layers (24,26), a conductive pad (28), and a distributed reverse surge guard (22), provides increased protection from reverse current surges. The surge guard (22) includes an outer loop (42) of P+-type surge guard material and an inner grid (44) of linear sections (46, 48) which form a plurality of inner loops extending inside the outer loop (42). The surge guard (22) distributes any reverse current over the area of the conductive pad (28) to provide increased protection from transient threats such as electrostatic discharge (ESD) and during electrical testing.

Abstract: A semiconductor device comprises a first semiconductor layer of a first conductivity type provided on a semiconductor substrate of the first conductivity type, a base layer of a second conductivity type provided in the first semiconductor layer, for defining a vertical MISFET including source regions and a gate electrode on a gate insulation film, a Schottky barrier diode (SBD)-forming region provided in the first semiconductor layer around the base layer, a guard ring region of the second conductivity type provided around SBD-forming region, a first main electrode disposed above the first semiconductor layer and provided in common as both a source electrode of the MISFET and an anode of the SBD, a surface gate electrode disposed above the first semiconductor layer, and a second main electrode provided in common as a drain electrode of the MISFET and a cathode of the SBD.

Abstract: The present invention is generally directed to intermeshed guard bands for multiple voltage supply regions or structures on an integrated circuit, and methods of making same. In one illustrative embodiment, an integrated circuit is provided that comprises a plurality of voltage supply structures formed above a substrate, the plurality of voltage supply structures being at differing voltage levels, and a guard band comprised of at least one doped region formed in the substrate under each of the plurality of voltage supply regions, each of the guard bands being comprised of a plurality of fingers extending from each end of the guard bands.

Abstract: A semiconductor device which can prevent an operation thereof from being uncontrollable to obtain a high reliability, and can be manufactured easily and can reduce a manufacturing cost. A p-type impurity layer containing a p-type impurity in a relatively high concentration is provided as an operation region of a diode in one of main surfaces of a silicon substrate containing an n-type impurity in a relatively low concentration and a plurality of ring-shaped Schottky metal layers are concentrically provided on the main surface of the silicon substrate around the p-type impurity layer with a space formed therebetween to surround the p-type impurity layer. A silicon oxide film is provided on the main surface of the silicon substrate around the p-type impurity layer and an anode electrode is provided on the p-type impurity layer.

Abstract: The present invention relates to a contacting structure on a lightly-doped P-type region of a semiconductor component, this P-type region being positively biased during the on-state operation of said component, including, on the P region a layer of a platinum silicide, or of a metal silicide having with the P-type silicon a barrier height lower than or equal to that of the platinum silicide.

Abstract: Disclosed are semiconductor devices including at least one junction which is rectifying whether the semiconductor is caused to be N or P-type, by the presence of applied gate voltage field induced carriers in essentially intrinsic, essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at substantially equal doping levels, essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at different doping levels, and containing a single metallurgical doping type, and functional combinations thereof. In particular, inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to conventional multiple device CMOS systems, which can be operated as modulators, are disclosed as are a non-latching SCR and an approach to blocking parasitic currents utilizing material(s) which form rectifying junctions with both N and P-type semiconductor whether metallurigically or field induced.

Abstract: A semiconductor device includes an electronic circuit, a metal guard ring surrounding the electronic circuit, and a passivation layer covering the electronic circuit and guard ring. The passivation layer has a slot extending from the surface of the device down to the guard ring. The slot prevents cracks that may form in the passivation layer at the edges of the device from propagating to the area inside the guard ring. Locating the slot over the guard ring enables the size of the device to be reduced, and enables the guard ring to keep moisture and contaminants that enter the slot from reaching lower layers of the device.

Abstract: The invention relates to a semiconductor device, in particular a Schottky hybrid diode with a guard ring (S). The semiconductor device comprises a semiconductor substrate (1), an epitaxial layer (2) on which an insulating layer (3) with an opening (10) is deposited, with a Schottky metal layer (9) covering the epitaxial layer (2) lying at the bottom of the opening (10), and with an annular semiconductor region (4) which is present in the epitaxial layer (2). A doping region (6) is present in the epitaxial layer (2) along the outer contour of the semiconductor device, and in addition an oxide layer (8) is present on the epitaxial layer (2).

Abstract: A semiconductor memory device comprises a semiconductor substrate having a memory cell region and a periphery circuit region. The memory cell region includes first and second conductivity type wells and an array of memory cell formed on the first and second conductivity type wells. The periphery circuit region comprises a guard ring that is formed at a location next to a second conductivity type well and to surround a side portion of the array of memory cells. The guard ring is formed with a depth different from that of the second conductivity type well.

Abstract: A vertical Schottky diode including an N-type silicon carbide layer of low doping level formed by epitaxy on a silicon carbide substrate of high doping level. The periphery of the active area of the diode is coated with a P-type epitaxial silicon carbide layer. A trench crosses the P-type epitaxial layer and penetrates into at least a portion of the height of the N-type epitaxial layer beyond the periphery of the active area. The doping level of the P-type epitaxial layer is chosen so that, for the maximum voltage that the diode is likely to be subjected to, the equipotential surfaces corresponding to approximately ¼ to ¾ of the maximum voltage extend up to the trench.

Abstract: A first guard ring formed by high concentration ion diffusion is established around the transistor formation region of the semiconductor substrate. A second guard ring is established around the first guard ring with a prescribed gap therebetween. A metal film is formed opposing to each guard ring with an insulating film interposed therebetween; these metal films are connected to the opposing guard rings by interlayer wires. The metal films are each connected to external terminals providing a standard potential by individual metal wires from their respective electrodes.

Abstract: A method for producing Schottky diodes having a protective ring in an edge region of a Schottky contact. The protective ring is produced by a protective ring material that is deposited onto a surface of a semiconductor layer, which surface is provided with a patterned masking layer beforehand, and the protective ring material subsequently being siliconized. In this case, the protective ring material constitutes a metal, in particular a high barrier metal, which has, in particular, platinum.

Abstract: A high-speed, soft-recovery semiconductor device that reduces leakage current by increasing the Schottky ratio of Schottky contacts to pn junctions. In one embodiment of the present invention, an n− drift layer is formed on an n+ cathode layer 1 by epitaxial growth, and ring-shaped ring trenches having a prescribed width are formed in the n− drift layer. Oxide films are formed on the side walls of each ring trench. The ring trenches are arranged such that the centers of the rings of the ring trenches adjacent to one another form a triangular lattice unit. A p− anode layer is formed at the bottom of each ring trench. Schottky contacts are formed at the interface between an anode electrode and the surface of the n− drift layer. Ohmic contact is established between the surfaces of polysilicon portions and the anode electrode.

Abstract: A termination structure and reduced mask process for its manufacture for either a FRED device or any power semiconductor device comprises at least two concentric diffusion guard rings and two spaced silicon dioxide rings used in the definition of the two guard rings in an implant and drive system. A first metal ring overlies and contacts the outermost diffusion. A second metal ring which acts as a field plate contacts the second diffusion and overlaps the outermost oxide ring. A third metal ring, which acts as a field plate, is a continuous portion of the active area top contact and overlaps the second oxide ring. The termination is useful for high voltage (of the order of 1200 volt) devices. The rings are segments of a common aluminum or palladium contact layer. A thin high resistivity layer of amorphous silicon is deposited over the full upper surface of the wafer and is disposed between the wafer upper surface and all of the metal rings.

Abstract: A natural-resource-conservative, environmentally-friendly, cost-effective, leadless semiconductor packaging apparatus, having superior mechanical and electrical properties, and having an optional windowed housing which uniquely seals and provides a mechanism for viewing the internally packaged integrated semiconductor circuits (chips/die). A uniquely stamped and/or bent lead-frame is packaged by a polymeric material during a unique compression-molding process using a mold, specially contoured to avoid the common “over-packaging” problem in related art techniques. The specially contoured mold facilitates delineation of the internal portions from the external portions of the lead-frame, as the external portions are the effective solderable areas that contact pads on a printed circuit board, thereby avoiding a laborious environmentally-unfriendly masking step and de-flashing step, streamlining the device packaging process.

Abstract: A method for producing a semiconductor component with adjacent Schottky (5) and pn (9) junctions positions in a drift area (2, 10) of a semiconductor material. According to the method, a silicon carbide substrate doped with a first doping material of at least 1018 cm−3 is provided, and a silicon carbide layer with a second doping material of the same charge carrier type in the range of 1014 and 1017 cm−3 is homo-epitaxially deposited on the substrate. A third doping material with a complimentary charge carrier is inserted, and structured with the aid of a diffusion and/or ion implantation, on the silicon carbide layer surface that is arranged far from the substrate to form pn junctions. Subsequently the component is subjected to a first temperature treatment between 1400° C. and 1700° C.

Abstract: The invention relates to a semiconductor component with adjacent Schottky (5) and pn (9) junctions positioned in a drift area (2, 10) of a semiconductor material. The invention also relates to a method for producing said semiconductor component.

Abstract: A semiconductor device comprises a first semiconductor layer of a first conductivity type provided on a semiconductor substrate of the first conductivity type, a base layer of a second conductivity type provided in the first semiconductor layer, for defining a vertical MISFET including source regions and a gate electrode on a gate insulation film, a Schottky barrier diode (SBD)-forming region provided in the first semiconductor layer around the base layer, a guard ring region of the second conductivity type provided around SBD-forming region, a first main electrode disposed above the first semiconductor layer and provided in common as both a source electrode of the MISFET and an anode of the SBD, a surface gate electrode disposed above the first semiconductor layer, and a second main electrode provided in common as a drain electrode of the MISFET and a cathode of the SBD.

Abstract: The invention includes a method of implanting dopants into a semiconductor structure wherein a lateral periphery of a photoresist mask is shifted after implanting a first dopant and prior to implanting a second dopant. The invention also includes semiconductor structures having two doped regions of a semiconductive material separated by a region less heavily doped than the doped regions.

Abstract: A FRED device having an ultralow Irr employs a contact layer which contacts spaced P diffusions in an N type silicon substrate and also contacts the silicon surface spanning between the P diffusions. The contact layer is formed of a contact having a lower barrier height than the conventional aluminum, and is palladium silicide with a top contact layer of aluminum.

Abstract: A Schottky contact is formed in the area of a MOSgated device semiconductor device chip which is occupied by a source pad. The Schottky contact is formed by the direct contact of the aluminum source electrode to the silicon chip in the source area. A different barrier metal can be used for the Schottky. A guard ring diffusion surrounds the Schottky metal.

Abstract: A semiconductor device includes a protective circuit at an input/output port thereof, wherein the protective circuit includes a plurality of protective MOS transistors. A diffused region is disposed between the n-type source/drain regions and a guard ring formed in a p-well for encircling the source/drain regions of the protective transistors. The diffused region is of lightly doped p-type or of an n-type and increases the resistance of a parasitic bipolar transistor formed in association with the protective transistors. The increase of the resistance assists protective function of the protective device against an ESD failure of the internal circuit of the semiconductor device.

Abstract: A structure of a cross guard ring along the edge of a semiconductor chip is disclosed. A first guard ring, a second guard ring and a third guard ring are formed along the edge of a semiconductor chip. Each guard ring comprises several rectangle shaped vias which are positioned along the edge of the chip structure, wherein each rectangle via is separated from an adjacent rectangle via by a gap. Further, each rectangle via of the second guard ring is positioned opposite the said gap of the first guard ring and are crossed over and have some overlay with rectangle vias of the first guard ring which are separated by the said gap as shown in FIG. 2. Similarly the third guard ring is positioned with respect to the second guard ring.

Abstract: A silicon-based semiconductor component includes a high-efficiency barrier junction termination. In the semiconductor component, a silicon semiconductor region takes on the depletion region of an active area of the semiconductor component. The junction termination for the active area is formed with silicon with a doping that is opposite to that of the semiconductor region, and the junction termination surrounds the active area on or in a surface of the semiconductor region. The junction termination is doped with a dopant that has a low impurity energy level of at least 0.1 eV in silicon. Preferably Be, Zn, Ni, Co, Mg, Sn or In are used as acceptors and S, Se or Ti are provided as donors.

Abstract: Inner trenches (11) of a trenched Schottky rectifier (1a; 1b; 1c; 1d) bound a plurality of rectifier areas (43a) where the Schottky electrode (3) forms a Schottky barrier 43 with a drift region (4). A perimeter trench (18) extends around the outer perimeter of the plurality of rectifier areas (43a). These trenches (11, 18) accommodate respective inner field-electrodes (31) and a perimeter field-electrode (38) that are connected to the Schottky electrode (3). The inner field-electrodes (11) are capacitively coupled to the drift region (4) via dielectric material (21) that lines the inner trenches (11). The perimeter field-electrode (38) is capacitively coupled across dielectric material (28) on the inside wall (18a) of the perimeter trench 18, without acting on any outside wall (18b). Furthermore, the inner and perimeter trenches (11, 18) are closely spaced and the intermediate areas (4a, 4b) of the drift region (4) are lowly doped.

Abstract: A semiconductor memory device comprises a semiconductor substrate having a memory cell region and a periphery circuit region. The memory cell region includes first and second conductivity type wells and an array of memory cell formed on the first and second conductivity type wells. The periphery circuit region comprises a guard ring that is formed at a location next to a second conductivity type well and to surround a side portion of the array of memory cells. The guard ring is formed with a depth different from that of the second conductivity type well.

Abstract: A pin diode includes an inner zone, a cathode zone and an anode zone. A boundary surface between the inner zone and the anode zone is at least partly curved and/or at least one floating region having the same conduction type and a higher dopant concentration than in the inner zone is provided in the inner zone. The turnoff performance in such geometrically coupled power diodes, in contrast to the turnoff performance of pin power diodes (in the Read-diode version) with spaced charge coupling, is largely temperature-independent. Hybrid diodes with optimized conducting-state and turnoff performance can be made from such FCI diodes. FCI diodes are preferably used in conjunction with switching power semiconductor elements, as voltage limiters or free running diodes.

Abstract: A semiconductor device 100 has a substrate 11 including a high breakdown voltage transistor region where transistors with high breakdown voltage and high dielectric strength Qn and Qp are formed and a low breakdown voltage transistor region where transistors with low breakdown voltage and low dielectric strength are formed. The transistors with high voltage breakdown and high dielectric strength Qn and Qp and the transistors with low voltage breakdown and low dielectric strength operate at different voltages. In the high breakdown voltage transistor region, the semiconductor device has metal wiring layers 19a and 19b that are fed with a high potential. The metal wiring layers 19a and 19b are provided over the transistors with high voltage breakdown and high dielectric strength Qn and Qp through a first interlayer dielectric film 16 and a second interlayer dielectric film 17. An element isolation dielectric region 14 is provided over the substrate 11.

Abstract: A Schottky diode comprises a semiconductor body of one conductivity type, the semiconductor body having a grooved surface, a metal layer on the grooved surface and forming a Schottky junction with the semiconductor body. The semiconductor body preferably includes a silicon substrate with the grooved surface being on a device region defined by a guard ring of a conductivity type opposite to the conductivity type of the semiconductor body, and a plurality of doped regions at the bottom of grooves and forming P-N junctions with the semiconductor body. The P-N junctions of the doped regions form carrier depletion regions across and spaced from the grooves to increase the reverse bias breakdown voltage and reduce the reverse bias leakage current.

Abstract: A Schottky diode comprises a semiconductor body of one conductivity type, the semiconductor body having a grooved surface, and a metal layer on the grooved surface and forming a Schottky junction with the semiconductor body. The semiconductor body preferably includes a silicon substrate with the grooved surface being on a device region defined by a guard ring of a conductivity type opposite to the conductivity type of the semiconductor body.

Abstract: A high-voltage edge termination structure for planar structures. The planar structures have a semiconductor body of a first conductivity type whose edge area is provided with at least one field plate isolated from the semiconductor body by an insulator layer. The edge area of the semiconductor body is provided with floating regions of a second conductivity type. The floating regions are spaced at such a distance from one another that zones between the floating regions are depleted even at an applied voltage which is low in comparison with a breakdown voltage of the semiconductor body for the floating regions.

Abstract: A semiconductor device includes a protective circuit at an input/output port thereof, wherein the protective circuit includes a plurality of protective MOS transistors. A diffused region is disposed between the n-type source/drain regions and a guard ring formed in a p-well for encircling the source/drain regions of the protective transistors. The diffused region is of lightly doped p-type or of an n-type and increases the resistance of a parasitic bipolar transistor formed in association with the protective transistors. The increase of the resistance assists protective function of the protective device against an ESD failure of the internal circuit of the semiconductor device.

Abstract: A Schottky barrier semiconductor device comprises an n+-type semiconductor substrate, an n−-type semiconductor layer grown on the semiconductor substrate by epitaxial growth, and two or more adjacent p+-type semiconductor regions formed on a surface of the semiconductor layer. The device comprises a metal layer having a Schottky barrier on the surface of an active region of the semiconductor layer. The p+-type semiconductor regions are formed so that a ratio of a distance between the adjacent p+-type semiconductor regions to a distance between the bottom surface of the p+-type semiconductor region and the bottom surface of the semiconductor layer may be the ratio of 1 to 1 through 2.

Abstract: An improved diode or rectifier structure and method of fabrication is disclosed involving the incorporation in a Schottky rectifier, or the like, of a dielectric filled isolation trench structure formed in the epitaxial layer adjacent the field oxide layers provided at the edge of the active area of the rectifier, for acting to enhance the field plate for termination of the electric field generated by the device during operation. The trench is formed in a closed configuration about the drift region and by more effectively terminating the electric field at the edge of the drift region the field is better concentrated within the drift region and acts to better interrupt reverse current flow and particularly restricts leakage current at the edges.

Abstract: Disclosed are semiconductor devices including at least one junction which is rectifying whether the semiconductor is caused to be N or P-type, by the presence of field induced carriers. In particular, inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to conventional multiple device CMOS systems, which can be operated as modulators, are disclosed as are a non-latching SCR and an approach to blocking parasitic currents. Operation of the gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems under typical bias schemes is described, and simple demonstrative five mask fabrication procedures for the inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems are also presented.

Abstract: The n-channel VDMOS transistor is formed in an n-type active region of an integrated circuit with junction isolation. To prevent over-voltages between source and gate which could damage or destroy the gate dielectric, a p-channel MOS transistor is formed in the same active region and has its gate electrode connected to the gate electrode of the VDMOS transistor, its source region in common with the source region of the VDMOS transistor, and its drain region connected to the p-type junction-isolation region. The p-channel MOS transistor has a threshold voltage below the breakdown voltage of the gate dielectric of the VDMOS transistor so that it acts as a voltage limiter.