Abstract: The present invention aims to enhance the reliability of a semiconductor device equipped with a Schottky barrier diode within the same chip, and its manufacturing technology. The semiconductor device includes an n-type n-well region formed over a p-type semiconductor substrate, an n-type cathode region formed in part thereof and higher in impurity concentration than the n-well region, a p-type guard ring region formed so as to surround the n-type cathode region, an anode conductor film formed so as to integrally cover the n-type cathode region and the p-type guard ring region and to be electrically coupled thereto, n-type cathode conduction regions formed outside the p-type guard ring region with each separation portion left therebetween, and a cathode conductor film formed so as to cover the n-type cathode conduction regions and to be electrically coupled thereto. The anode conductor film and the n-type cathode region are Schottky-coupled to each other.

Abstract: A low profile high power Schottky barrier bypass diode for solar cells and panels with the cathode and anode electrodes on the same side of the diode and a method of fabrication thereof are disclosed for generating a thin chip with both electrodes being on the same side of the chip. In an embodiment, a mesa isolation with a Zener diode over the annular region surrounding the central region of the mesa anode in the Epi of the substrate is formed. In an embodiment, a P-type Boron dopant layer is ion implanted in the annular region for the Zener Diode. This controls recovery from high voltage spikes from the diode rated voltage. A Schottky barrier contact for the anode and a contact for the cathode are simultaneously created on the same side of the chip.

Abstract: The present invention discloses a Schottky diode. The Schottky diode comprises a cathode region, an anode region and a guard ring region. The anode region may comprise a metal Schottky contact. The guard ring region may comprise an outer guard ring and a plurality of inner guard stripes inside the outer guard ring. And wherein the inner guard stripe has a shallower junction depth than the outer guard ring.

Abstract: An electrostatic discharge protection device includes a first bipolar transistor having a collector terminal connected with a first power supply terminal, an emitter terminal connected with the input/output terminal, and a base terminal connected with a second power supply terminal, a second bipolar transistor having a collector terminal connected with the second power supply terminal, an emitter terminal connected with the input/output terminal, and a base terminal connected with the first power supply terminal, one of the first and second bipolar transistors ensuring a continuity between the collector terminal and emitter terminal under such conditions that a potential difference between the first or second power supply terminal and the input/output terminal is lower than a breakdown voltage at a PN junction between the emitter terminal and the base terminal of the other bipolar transistor.

Abstract: A Schottky diode comprising a merged guard ring and field plate defining a Schottky contact region is provided. A Schottky metal is formed over at least partially over the Schottky contact region and at least partially over the merged guard ring and field plate.

Abstract: A superjunction semiconductor device includes an edge p pillar, an active region, and a termination region. The edge p pillar has a rectangular ring shape with rounded corners surrounding the active region. The active region includes an active n region and active p pillars having vertical stripe shapes disposed at regular intervals in the active n region. The top and bottom ends of the active p pillars are separated from the edge p pillar. The termination region includes termination n pillars and termination p pillars alternately arranged around the edge p pillar. Surplus p charges that are not used to balance the quantity of p charges and the quantity of n charges among p charges included in the upper and lower parts of the edge p pillar are eliminated or n charges are supplemented to balance the quantity of p charges and the quantity of n charges.

Abstract: Provided is a semiconductor device which includes a metal oxide semiconductor (MOS) transistor having high driving performance and high withstanding voltage with a thick gate oxide film. In the local oxidation-of-silicon (LOCOS) offset MOS transistor having high withstanding voltage, in order to prevent a gate oxide film (6) formed on a channel formation region (7) from being etched at a time of removing the gate oxide film (6) with a polycrystalline silicon gate electrode (8) being used as a mask to form a second conductivity type high concentration source region (4) and a second conductivity type high concentration drain region (5), a source field oxide film (14) is formed also on a source side of the channel formation region (7), and in addition, a length of a second conductivity type high concentration source field region (13) is optimized. Accordingly, it is possible to obtain a MOS transistor having high driving performance and high withstanding voltage with a thick gate oxide film.

Abstract: A Schottky diode optimizes the on state resistance, the reverse leakage current, and the reverse breakdown voltage of the Schottky diode by forming an insulated control gate over a region that lies between the metal-silicon junction of the Schottky diode and the n+ cathode contact of the Schottky diode.

Abstract: An SiC Schottky diode die or a Si Schottky diode die is mounted with its epitaxial anode surface connected to the best heat sink surface in the device package. This produces a substantial increase in the surge current capability of the device.

Abstract: A schottky diode may include a schottky junction including a well formed in a semiconductor substrate and a first electrode contacting the first well. The well may have a first conductivity type. A first ohmic junction may include a first junction region formed in the well and a second electrode contacting the first junction region. The first junction region may have a higher concentration of the first conductivity type than the well. A first device isolation region may be formed in the semiconductor substrate separating the schottky junction and the first ohmic junction. A well guard having a second conductivity type opposite to the first conductivity type may be formed in the well. At least a portion of the well guard may be formed under a portion of the schottky junction.

Abstract: A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.

Abstract: A TMBS diode is disclosed. In an active portion and a voltage withstanding structure portion of the diode, an end portion trench surrounds active portion trenches. An active end portion which is an outer circumferential side end portion of an anode electrode is in contact with conductive polysilicon inside the end portion trench. A guard trench is separated from the end portion trench and surrounds it. A field plate provided on an outer circumferential portion of the anode electrode is separated from the anode electrode, and contacts both part of a surface of an n-type drift layer in a mesa region between the end portion trench and the guard trench and the conductive polysilicon formed inside the guard trench. The semiconductor device is high in withstand voltage without injection of minority carriers, and electric field intensity of a trench formed in an end portion of an active portion is relaxed.

Abstract: An embodiment of the present invention is a technique to prevent reliability failures in semiconductor devices. A trench is patterned in a polyimide layer over a guard ring having a top metal layer. A passivation layer is etched at bottom of the trench. A capping layer is deposited on the trench over the etched passivation layer. The capping layer and the top metal layer form a mechanical strong interface to prevent a crack propagation.

Abstract: A wide bandgap semiconductor device with surge current protection and a method of making the device are described. The device comprises a low doped n-type region formed by plasma etching through the first epitaxial layer grown on a heavily doped n-type substrate and a plurality of heavily doped p-type regions formed by plasma etching through the second epitaxial layer grown on the first epitaxial layer. Ohmic contacts are formed on p-type regions and on the backside of the n-type substrate. Schottky contacts are formed on the top surface of the n-type region. At normal operating conditions, the current in the device flows through the Schottky contacts. The device, however, is capable of withstanding extremely high current densities due to conductivity modulation caused by minority carrier injection from p-type regions.

Abstract: A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.

Abstract: A fast recovery diode includes a base layer of a first conductivity type. The base layer has a cathode side and an anode side opposite the cathode side. An anode buffer layer of a second conductivity type having a first depth and a first maximum doping concentration is arranged on the anode side. An anode contact layer of the second conductivity type having a second depth, which is lower than the first depth, and a second maximum doping concentration, which is higher than the first maximum doping concentration, is also arranged on the anode side. A space charge region of the anode junction at a breakdown voltage is located in a third depth between the first and second depths. A defect layer with a defect peak is arranged between the second and third depths.

Abstract: According to an embodiment of the present invention, an electrostatic breakdown protection method protects a semiconductor device from a surge current impressed between a first terminal and a second terminal, the semiconductor device including: a diode impressing a forward-bias current from the first terminal to the second terminal; and a bipolar transistor impressing a current in a direction from the second terminal to the first terminal under an ON state, a continuity between a collector terminal and an emitter terminal of the bipolar transistor being attained before a potential difference between the first terminal and the second terminal reaches such a level that the diode is broken down.

Abstract: This invention discloses a gallium nitride based semiconductor power device disposed in a semiconductor substrate. The power device comprises a termination area disposed at a peripheral area of the semiconductor power device comprises a termination structure having at least a guard ring disposed in a trench filled with doped gallium-based epitaxial layer therein.

Abstract: An electronic device, including a substrate, a functional structure constituting a functional element formed on the substrate, and a cover structure forming a cavity portion in which the functional structure is disposed, is disclosed. In the electronic device, the cover structure includes a laminated structure of an interlayer insulating film and a wiring layer, the laminated structure being formed on the substrate in such a way that it surrounds the cavity portion, and the cover structure has an upside cover portion covering the cavity portion from above, the upside cover portion being formed with part of the wiring layer that is disposed above the functional structure.

Abstract: A trench Schottky rectifier device includes a substrate having a first conductivity type, a plurality of trenches formed in the substrate, and an insulating layer formed on sidewalls of the trenches. The trenches are filled with conductive structure. There is an electrode overlying the conductive structure and the substrate, and thus a Schottky contact forms between the electrode and the substrate. A plurality of embedded doped regions having a second conductivity type are formed in the substrate and located under the trenches. Each doped region and the substrate form a PN junction to pinch off current flowing toward the Schottky contact so as to suppress current leakage.

Abstract: A semiconductor device includes a semiconductor substrate, a photon avalanche detector in the semiconductor substrate. The photon avalanche detector includes an anode of a first conductivity type and a cathode of a second conductivity type. A guard ring is in the semiconductor substrate and at least partially surrounds the photon avalanche detector. A passivation layer of the first conductivity type is in contact with the guard ring to reduce an electric field at an edge of the photon avalanche detector.

Abstract: Disclosed is a seal-ring architecture that can minimize noise injection from noisy digital circuits to sensitive analog and/or radio frequency (RF) circuits in system-on-a-chip (SoC) applications. In order to improve the isolation, the seal-ring structure contains cuts and ground connections to the segment which is close to the analog circuits. The cuts are such that the architecture is fully compatible with standard design rules and that the mechanical strength of the seal rings is not significantly sacrificed. Some embodiments also include a grounded p-tap ring between the analog circuits and the inner seal ring in order to improve isolation. Some embodiments also include a guard strip between the analog circuits and the digital circuits to minimize the noise injection through the substrate.

Abstract: A silicon carbide semiconductor device includes a substrate; a drift layer having a first conductivity type; an insulating layer; a Schottky electrode; an ohmic electrode; a resurf layer; and second conductivity type layers. The drift layer and the second conductivity type layers provide multiple PN diodes. Each second conductivity type layer has a radial width with respect to a center of a contact region between the Schottky electrode and the drift layer. A radial width of one of the second conductivity type layers is smaller than that of another one of the second conductivity type layers, which is disposed closer to the center of the contact region than the one of the second conductivity type layers.

Abstract: An electronic device, including a substrate, a functional structure constituting a functional element formed on the substrate, and a cover structure forming a cavity portion in which the functional structure is disposed, is disclosed. In the electronic device, the cover structure includes a laminated structure of an interlayer insulating film and a wiring layer, the laminated structure being formed on the substrate in such a way that it surrounds the cavity portion, and the cover structure has an upside cover portion covering the cavity portion from above, the upside cover portion being formed with part of the wiring layer that is disposed above the functional structure.

Abstract: In a termination structure in which a JTE layer is provided, a level or defect existing at an interface between a semiconductor layer and an insulating film, or a minute amount of adventitious impurities that infiltrate into the semiconductor interface from the insulating film or from an outside through the insulating film becomes a source or a breakdown point of a leakage current, which deteriorates a breakdown voltage.

Abstract: The HVIC includes a dielectric layer and an SOI active layer stacked on a silicon substrate, a transistor formed in the surface of the SOI active layer, and a trench isolation region formed around the transistor. The dielectric layer includes a first buried oxide film formed in the surface of the silicon substrate, a shield layer formed below the first buried oxide film opposite the element area, a second buried oxide film formed around the shield layer, and a third buried oxide film formed below the shield layer and the second buried oxide film. Therefore, the potential distribution curves PC within the dielectric layer are low in density and a high withstand voltage is achieved.

Abstract: A semiconductor fabrication process according to the present invention defines an auxiliary structure with a plurality of spaces with a predetermined line-width in the oxide layer to prevent the conductive material in the spaces from being removed by etching or defined an auxiliary structure to rise the conductive structure so as to have the conductive structure being exposed by chemical mechanical polishing. Thus, the transmitting circuit can be defined without requiring an additional mask. Hence, the semiconductor fabrication process can reduce the number of required masks to lower the cost.

Abstract: A semiconductor device is disclosed. The device includes a substrate and a first wiring layer overlying the substrate. The first wiring layer comprises a first wiring area surrounded by a first seal ring. The first seal ring comprises a first monitor circuit isolated by a first dielectric layer embedded in the first seal ring. The first monitor circuit is responsive to a predetermined amount of deformation occurs in the third dielectric layer.

Abstract: In the diffusion region (3) of the second conductivity mode, a more highly doped region of the same conductivity mode (5) is introduced in such a manner that the region of the first conductivity mode (2) which is covered by the metal silicide (9) and of the second conductivity mode (3) are connected in a conductive manner. The region (3) of the second conductivity mode is diffused in such a manner that it reaches the more highly doped region (1) of the first doping type (1), with an outward diffusion of the doping from the more highly doped substrate layer (1) into the more weakly doped layer (2) of the same conductivity mode in the direction of the semiconductor surface taking place at the same time.

Abstract: A junction barrier Schottky diode has an N-type well having surface and a first impurity concentration; a p-type anode region in the surface of the well, and having a second impurity concentration; and an N-type cathode region in the surface of the well and horizontally abutting the anode region, and having a third impurity concentration. A first N-type region vertically abuts the anode and cathode regions, and has a fourth impurity concentration. An ohmic contact is made to the anode and a Schottky contact is made to the cathode. The fourth impurity concentration is less than the first, second and third impurity concentrations.

Abstract: A Schottky diode device includes a silicon substrate, an epitaxial silicon layer on the silicon substrate, an annular trench in a scribe line region that encompasses the epitaxial silicon layer, an insulation layer on interior sidewall of the annular trench, a silicide layer on the epitaxial silicon layer, a conductive layer on the silicide layer, and a guard ring in the epitaxial silicon layer, wherein the guard ring butts the insulation layer.

Abstract: A high-voltage Schottky diode including a deep P-well having a first width is formed on the semiconductor substrate. A doped P-well is disposed over the deep P-well and has a second width that is less than the width of the deep P-well. An M-type guard ring is formed around the upper surface of the second doped well, A Schottky metal is disposed on an upper surface of the second doped well and the N-type guard ring.

Abstract: A semiconductor device includes a semiconductor layer including a base region of a second conductive type formed in a first surface of the semiconductor layer, an emitter region of the first conductive type formed in the base region, a buffer layer of the first conductive type formed on a second surface of the semiconductor layer, and a collector layer of the second conductive type formed on the buffer layer. The buffer layer has a maximal concentration of the first conductive type impurity of approximately 5 ×1015 cm?3 or less, and the collector layer has a maximal concentration of the second conductive type impurity of approximately 1×1017 cm?3 or more. The ratio of the maximal concentration of the collector layer to that of the buffer layer is greater than 100. The collector layer has a thickness of approximately 1 ?m or more.

Abstract: A “tabbed” MOS device provides radiation hardness while supporting reduced gate width requirements. The “tabbed” MOS device also utilizes a body tie ring, which reduces field threshold leakage. In one implementation the “tabbed” MOS device is designed such that a width of the tab is based on at least a channel length of the MOS device such that a radiation-induced parasitic conduction path between the source and drain region of the device has a resistance that is higher than the device channel resistance.

Abstract: A device structure with preformed ring includes a sensor chip and a ring disposed and surrounded on periphery of sensitive area of an active surface thereof. The device structure with preformed ring may batchly bind and electrically connect to a carrier by a way of two-dimension array, and then a packaging process is performed. During the packaging process, the top portion of the ring can be used to against the inner side of a packaging mold, so as to stop the packaging material covering the device at outside of the ring and stick with the ring. Therefore, an opening is formed on the sensitive area surface of the device. Depending on the ring, the extra process for eliminating the packaging material on the sensitive area surface can be avoided in the conventional process.

Abstract: An integrated circuit structure includes a semiconductor substrate; a well region of a first conductivity type over the semiconductor substrate; a metal-containing layer on the well region, wherein the metal-containing layer and the well region form a Schottky barrier; an isolation region encircling the metal-containing layer; and a deep-well region of a second conductivity type opposite the first conductivity type under the metal-containing layer. The deep-well region has at least a portion vertically overlapping a portion of the metal-containing layer. The deep-well region is vertically spaced apart from the isolation region and the metal-containing layer by the well region.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type having a top surface and a bottom surface, a semiconductor layer of a first conductivity type formed on the top surface of the semiconductor substrate, and having an active region and an edge termination region surrounding the active region, a first semiconductor region of a second conductivity type formed in the edge termination region adjacent to an edge of the active region, a second semiconductor region of a second conductivity type buried in the edge termination region in a sheet shape or a mesh shape substantially in parallel with a surface of the semiconductor layer, a first electrode formed on the active region of the semiconductor layer and a part of the first semiconductor region, and a second electrode formed on the bottom surface of the semiconductor substrate.

Abstract: An integrated circuit includes a high voltage NPN bipolar transistor and a low voltage device. The NPN bipolar transistor includes a lightly doped p-well as the base region of the transistor while the low voltage devices are built using standard, more heavily doped p-wells. By using a process including a lightly doped p-well and a standard p-well, high and low voltage devices can be integrated onto the same integrated circuit. In one embodiment, the lightly doped p-well and the standard p-well are formed by performing ion implantation using a first dose to form the lightly doped p-well, masking the lightly doped p-well, and performing ion implantation using a second dose to form the standard p-well. The second dose is the difference of the dopant concentrations of the lightly doped p-well and the standard p-well. Other high voltage devices can also be built by incorporating the lightly doped p-well structure.

Abstract: A high-voltage Schottky diode including a deep P-well having a first width is fanned on the semiconductor substrate. A doped P-well is disposed over the deep P-well and has a second width that is less than the width of the deep P-well. An M-type guard ring is formed around the upper surface of the second doped well, A Schottky metal is disposed on an upper surface of the second doped well and the N-type guard ring.

Abstract: Trenches are formed in a semiconductor substrate, where the trenches include an outer trench and multiple inner trenches within the outer trench. A metal-oxide semiconductor (MOS) device and a trench MOS Schottky barrier (TMBS) device are also formed in the semiconductor substrate using the trenches. The MOS device could include the outer trench, and the TMBS device could include the inner trenches. At least one of the inner trenches may contact the outer trench, and/or at least one of the inner trenches may be electrically isolated from the outer trench. The MOS device could represent a trench vertical double-diffused metal-oxide semiconductor (VDMOS) device, and the TMBS device may be monolithically integrated with the trench VDMOS device in the semiconductor substrate. A guard ring that covers portions of the inner trenches and that is open over other portions of the inner trenches could optionally be formed in the semiconductor substrate.

Abstract: In a semiconductor device of the present invention, a protection diode for protecting a device is formed on an epitaxial layer formed on a substrate. A Schottky barrier metal layer is formed on a surface of the epitaxial layer and a P-type diffusion layer is formed at a lower portion of an end portion of the Schottky barrier metal layer. Then, a P-type diffusion layer is formed to be connected to a P-type diffusion layer and is extended to a cathode region. A metal layer to which an anode electrode is applied is formed above the P-type diffusion layer, thereby making it possible to obtain a field plate effect. This structure reduces a large change in a curvature of a depletion layer, thereby improving a withstand voltage characteristic of the protection diode.

Abstract: A semiconductor device of unipolar type has Schottky-contacts (6) laterally separated by regions in the form of additional layers (7, 7?) of semiconductor material on top of a drift layer (3). Said additional layers being doped according to a conductivity type being opposite to the one of the drift layer. At least one (7?) of the additional layers has a substantially larger lateral extension and thereby larger area of the interface to the drift layer than adjacent such layers (7) for facilitating the building-up of a sufficient voltage between that layer and the drift layer for injecting minority charge carriers into the drift layer upon surge for surge protection.

Abstract: A semiconductor device includes a semiconductor layer having a first conductivity type, a metal contact on the semiconductor layer and forming a Schottky junction with the semiconductor layer, and a semiconductor region in the semiconductor layer. The semiconductor region and the semiconductor layer form a first p-n junction in parallel with the Schottky junction. The first p-n junction is configured to generate a depletion region in the semiconductor layer adjacent the Schottky junction when the Schottky junction is reversed biased to thereby limit reverse leakage current through the Schottky junction. The first p-n junction is further configured such that punch-through of the first p-n junction occurs at a lower voltage than a breakdown voltage of the Schottky junction when the Schottky junction is reverse biased.

Abstract: An electronic device, including a substrate, a functional structure constituting a functional element formed on the substrate, and a cover structure forming a cavity portion in which the functional structure is disposed, is disclosed. In the electronic device, the cover structure includes a laminated structure of an interlayer insulating film and a wiring layer, the laminated structure being formed on the substrate in such a way that it surrounds the cavity portion, and the cover structure has an upside cover portion covering the cavity portion from above, the upside cover portion being formed with part of the wiring layer that is disposed above the functional structure.

Abstract: A semiconductor device having structures for reducing substrate noise coupled from through die vias (TDVs) is described. In one example, a semiconductor device has a substrate, at least one signal through die via (TDV), and ground TDVs. The substrate includes conductive interconnect formed on an active side thereof. The conductive interconnect includes ground conductors and digital signal conductors. Each signal TDV is formed in the substrate and is electrically coupled to at least one of the digital signal conductors. The ground TDVs are formed in the substrate in a ring around the at least one signal TDV. The ground TDVs are electrically coupled to the ground conductors. The ground TDVs provide a sink for noise coupled into the substrate from the signal TDVs. In this manner, the ground TDVs mitigate noise coupled to noise-sensitive components formed on the substrate.

Abstract: A vertical rectifying and protection power diode, formed in a lightly-doped semiconductor layer of a first conductivity type, resting on a heavily-doped substrate of the first conductivity type, having a first ring-shaped region, of the first conductivity type more heavily-doped than the layer and more lightly doped than the substrate, surrounding an area of the layer and extending to the substrate; and a second ring-shaped region, doped of the second conductivity type, extending at the surface of the first region and on either side thereof; a first electrode having a thin layer of a material capable of forming a Schottky diode with the layer, resting on the area of the layer and on at least a portion of the second ring-shaped region with which it forms an ohmic contact.

Abstract: Disclosed is a semiconductor device which has a circuit-forming region. The semiconductor device has a semiconductor substrate, a plurality of insulating interlayer films, a guard ring, and a first MIM capacitor. The insulating interlayer films, which are stacked one upon another, are provided over the semiconductor substrate. The guard ring is formed in the plurality of insulating interlayer films and surrounds the circuit-forming region. The guard ring is separated from an insulating interlayer film including a topmost interconnect. The MIM capacitor is provided between the guard ring and the insulating interlayer film including the topmost interconnect.

Abstract: Systems and methods for maximizing the breakdown voltage of a semiconductor device are described. In a multiple floating guard ring design, the spacing between two consecutive sets of floating guard rings may increase with their distance from the main junction while maintaining depletion region overlap, thereby alleviating crowding and optimally spreading the electric field leading to a breakdown voltage that is close to the intrinsic material limit. In another exemplary embodiment, fabrication of floating guard rings simultaneously with the formation of another semiconductor feature allows precise positioning of the first floating guard ring with respect to the edge of a main junction, as well as precise control of floating guard ring widths and spacings. In yet another exemplary embodiment, design of the vertical separation between doped regions of a semiconductor device adjusts the device's gate-to-source breakdown voltage without affecting the device's pinch-off voltage.

Abstract: In various embodiments, circuits and semiconductor devices and structures and methods to manufacture these structures and devices are disclosed. In one embodiment, a bidirectional polarity, voltage transient protection device is disclosed. The voltage transient protection device may include a bipolar PNP transistor having a turn-on voltage of VBE1, a bipolar NPN transistor having a turn-on voltage of VBE2, and a field effect transistor (FET) having a threshold voltage of VTH, wherein a turn-on voltage VTO of the voltage transient protection device is approximately equal to the sum of VBE1, VBE2, and VTH, that is, VTO?VBE1+VBE2+VTH. Other embodiments are described and claimed.

Abstract: A semiconductor device includes an SiC substrate, a normal direction of the substrate surface being off from a <0001> or <000-1> direction in an off direction, an SiC layer formed on the SiC substrate, a junction forming region formed in a substantially central portion of the SiC layer, a junction termination region formed to surround the junction forming region, and including a semiconductor region of a conductivity type different from the SiC layer formed as a substantially quadrangular doughnut ring, having two edges facing each other, each crossing a projection direction, which is obtained when the off direction is projected on the upper surface of the SiC layer, at a right angle, wherein a width of one of the two edges on an upper stream side of the off direction is L1, that of the other edge on a down stream side is L2, and a relation L1>L2 is satisfied.