Abstract: Methods for fabricating bipolar junction transistors with self-aligned emitter and extrinsic base, bipolar junction transistors made by the methods, and design structures for a BiCMOS integrated circuit. The bipolar junction transistor is fabricated using a sacrificial emitter pedestal that provides a sacrificial mandrel promoting self-alignment between the emitter and the extrinsic base. The sacrificial emitter pedestal is subsequently removed to open an emitter window extending to the intrinsic base. An emitter is formed in the emitter window that lands on the intrinsic base.

Abstract: A semiconductor device includes a substrate; a carrier traveling layer formed on the substrate, made of first group III nitride semiconductor, and containing carriers traveling in a direction along a principal surface of the substrate; a barrier layer formed on the carrier traveling layer and made of second group III nitride semiconductor having a wider band gap than the first group III nitride semiconductor; and an electrode formed on the barrier layer. The device further includes a cap layer formed on the barrier layer at a side of the electrode, and made of third group III nitride semiconductor containing a mixture of single crystals and polycrystals.

Abstract: According to an embodiment of a field-effect semiconductor device, the field-effect semiconductor device includes a semiconductor body and a source electrode. The semiconductor body includes a drift region, a gate region and a source region of a first semiconductor material having a first band-gap and an anode region of a second semiconductor material having a second band-gap lower than the first band-gap. The drift region is of a first conductivity type. The gate region forms a pn-junction with the drift region. The source region is of the first conductivity type and in resistive electric connection with the drift region and has a higher maximum doping concentration than the drift region. The anode region is of the second conductivity type, forms a heterojunction with the drift region and is spaced apart from the source region. The source metallization is in resistive electric connection with the source region and the anode region.

Abstract: It is an object to provide an epitaxial silicon wafer that is provided with an excellent gettering ability in which a polysilicon layer is formed on the rear face side of a silicon crystal substrate into which phosphorus (P) and germanium (Ge) have been doped. A silicon epitaxial layer is grown by a CVD method on the surface of a silicon crystal substrate into which phosphorus and germanium have been doped at a high concentration. After that, a PBS forming step for growing a polysilicon layer is executed on the rear face side of a silicon crystal substrate. By the above steps, the number of LPDs (caused by an SF) that occur on the surface of the epitaxial silicon wafer due to the SF can be greatly reduced.

Abstract: [Problem] To provide a substrate bonding technique having a wide range of application. [Solution] A silicon thin film is formed on a bonding surface, and the interface with the substrate is surface-treated using energetic particles/metal particles.

Abstract: The present invention relates to a semiconductor device including a circuit composed of thin film transistors having a novel GOLD (Gate-Overlapped LDD (Lightly Doped Drain)) structure. The thin film transistor comprises a first gate electrode and a second electrode being in contact with the first gate electrode and a gate insulating film. Further, the LDD is formed by using the first gate electrode as a mask, and source and drain regions are formed by using the second gate electrode as the mask. Then, the LDD overlapping with the second gate electrode is formed. This structure provides the thin film transistor with high reliability.

Abstract: To provide a method for producing a thin film transistor improved in stability, uniformity, reproducibility, heat resistance, durability or the like, a thin film transistor, a thin film transistor substrate, an image display apparatus, an image display apparatus and a semiconductor device. In the semiconductor device, a crystalline oxide is used as an N-type transistor and the electron carrier concentration of the crystalline oxide is less than 2×1017/cm3. Furthermore, the crystalline oxide is a polycrystalline oxide containing In and one or more positive divalent elements selected from Zn, Mg, Cu, Ni, Co and Ca, and the atomic ratio In [In] and the positive divalent element [X][X]/([X]+[In]) is 0.0001 to 0.13.

Abstract: An apparatus, method and products thereof provide an accelerated neutral beam derived from an accelerated gas cluster ion beam for processing materials.

Abstract: A thin film transistor is provided, which includes a gate insulating layer covering a gate electrode, a microcrystalline semiconductor layer provided over the gate insulating layer, an amorphous semiconductor layer overlapping the microcrystalline semiconductor layer and the gate insulating layer, and a pair of impurity semiconductor layers which are provided over the amorphous semiconductor layer and to which an impurity element imparting one conductivity type is added to form a source region and a drain region. The gate insulating layer has a step adjacent to a portion in contact with an end portion of the microcrystalline semiconductor layer. A second thickness of the gate insulating layer in a portion outside the microcrystalline semiconductor layer is smaller than a first thickness thereof in a portion in contact with the microcrystalline semiconductor layer.

Abstract: A method of manufacturing a compound semiconductor device, includes: forming a compound semiconductor lamination structure over a substrate; forming a metal film over the compound semiconductor lamination structure; forming a source electrode and a drain electrode over the metal film; forming one of a metal oxide film and a metal nitride film by one of oxidizing and nitriding a part of the metal film; and forming a gate electrode over the metal oxide film or the metal nitride film.

Abstract: Heterojunction bipolar transistors are provided that include at least one contact (e.g., collector, emitter, and/or base) formed by a heterojunction between a crystalline semiconductor material and a doped non-crystalline semiconductor material layer. An interfacial intrinsic non-crystalline semiconductor material layer is present at the heterojunction between the crystalline semiconductor material and the doped non-crystalline semiconductor material layer. The presence of the interfacial intrinsic non-crystalline semiconductor material layer improves the surface passivation of the crystalline semiconductor material by reducing the interface defect density at the heterojunction.

Abstract: Heterojunction bipolar transistors are provided that include at least one contact (e.g., collector, and/or emitter, and/or base) formed by a heterojunction between a crystalline semiconductor material and a doped non-crystalline semiconductor material layer. A highly doped epitaxial semiconductor layer comprising a highly doped hydrogenated crystalline semiconductor material layer portion is present at the heterojunction between the crystalline semiconductor material and the doped non-crystalline semiconductor material layer. Minority carriers within the highly doped epitaxial semiconductor layer have a diffusion length that is larger than a thickness of the highly doped epitaxial semiconductor layer.

Abstract: Methods, structures and devices are provided in which a crystalline silicon surface is passivated by an ultra-thin silicon oxide layer and an outer passivating dielectric layer, where the ultra-thin silicon oxide layer has a thickness on an Angstrom scale. In some embodiments, both layers are formed by low temperature processes. The outer passivating layer may be formed according to a PECVD process that employs hydrogen-containing precursor gases, such that hydrogen is incorporated into one or both of the silicon oxide layer and the passivating dielectric layer. The present methods may be employed for the passivation of a wide variety of structures and devices, including photovoltaic cells, MOSFET devices, flash memory devices, and thin-film silicon substrates that may contain such devices.

Abstract: The cost of liquid phase epitaxial growth of a monocrystalline silicon carbide is reduced. A feed material 11 is such that when a surface layer thereof containing a polycrystalline silicon carbide with a 3C crystal polymorph is subjected to X-ray diffraction, a diffraction peak corresponding to a (111) crystal plane and a diffraction peak other than the diffraction peak corresponding to the (111) crystal plane are observed as diffraction peaks corresponding to the polycrystalline silicon carbide with a 3C crystal polymorph.

Abstract: In a method for making a GaN article, an epitaxial nitride layer is deposited on a single-crystal substrate. A 3D nucleation GaN layer is grown on the epitaxial nitride layer by HVPE under a substantially 3D growth mode. A GaN transitional layer is grown on the 3D nucleation layer by HVPE under a condition that changes the growth mode from the substantially 3D growth mode to a substantially 2D growth mode. A bulk GaN layer is grown on the transitional layer by HVPE under the substantially 2D growth mode. A polycrystalline GaN layer is grown on the bulk GaN layer to form a GaN/substrate bi-layer. The GaN/substrate bi-layer may be cooled from the growth temperature to an ambient temperature, wherein GaN material cracks laterally and separates from the substrate, forming a free-standing article.

Abstract: A method of depositing polycrystalline silicon exclusively on monocrystalline first silicon surface portions of a substrate surface which besides the first surface portions additionally has insulator surface portions, comprising the steps of depositing boron on the first silicon surface portions in an amount which in relation to the first silicon surface portions respectively corresponds to more than a monolayer of boron, and depositing silicon on the first silicon surface portions treated in that way.

Abstract: By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished.

Abstract: Disclosed are a transistor (e.g., bipolar junction transistor (BJT) or a heterojunction bipolar transistor (HBT)) and a method of forming the transistor with a narrow in-substrate collector region for reduced base-collector junction capacitance. The transistor has, within a substrate, a collector region positioned laterally adjacent to a trench isolation region. A relatively thin seed layer covers the trench isolation region and collector region. This seed layer has a monocrystalline center, which is aligned above and wider than the collector region (e.g., due to a solid phase epitaxy regrowth process), and a polycrystalline outer section. An intrinsic base layer is epitaxially deposited on the seed layer such that it similarly has a monocrystalline center section that is aligned above and wider than the collector region. An extrinsic base layer is the intrinsic base layer and has a monocrystalline extrinsic base-to-intrinsic base link-up region that is offset vertically from the collector region.

Abstract: A semiconductor diode is provided. The semiconductor diode includes a monocrystalline silicon semiconductor body including a first semiconductor region of a first conductivity type extending to a first surface of the semiconductor body and having a first maximum doping concentration, and a second semiconductor region of a second conductivity type forming a pn-junction with the first semiconductor region. The semiconductor diode further includes a polycrystalline silicon semiconductor region of the first conductivity type having a second maximum doping concentration which is higher than the first maximum doping concentration and adjoining the first semiconductor region on the first surface, a first metallization arranged on the polycrystalline silicon semiconductor region and in electric contact with the polycrystalline semiconductor region, and an edge-termination structure arranged next to the first semiconductor region. Further, a method for producing a semiconductor diode is provided.

Abstract: A passivated germanium surface that is a germanium carbide material formed on and in contact with the germanium material. A semiconductor device structure having the passivated germanium having germanium carbide material on the substrate surface is also disclosed.

Abstract: Some embodiments of the present invention include providing carbon doped regions and raised source/drain regions to provide tensile stress in NMOS transistor channels.

Abstract: Disclosed are example bipolar transistors capable of reducing the area of a collector, reducing the distance between a base and a collector, and/or reducing the number of ion implantation processes. A bipolar transistor may includes a trench formed by etching a portion of a semiconductor substrate. A first collector may be formed on the inner wall of the trench. A second collector may be formed inside the semiconductor substrate in the inner wall of the trench. A first isolation film may be formed on the sidewall of the first collector. An intrinsic base may be connected to the third collector. An extrinsic base may be formed on the intrinsic base and inside the first isolation film. A second isolation film may be formed on the inner wall of the extrinsic base. An emitter may be formed by burying a conductive material inside the second isolation film.

Abstract: A nano-crystal diamond film synthesized on a substrate and containing, as a major component, nano-crystal diamond having a grain diameter from 1 nm to less than 1000 nm. This nano-crystal diamond film can be formed on a substrate by means of a plasma CVD method using a raw material gas containing a hydrocarbon and hydrogen, allowing the formation of the nano-crystal diamond film to take place outside the plasma region. This nano-crystal diamond film is applicable to the manufacture of an electrochemical device, an electrochemical electrode, a DNA chip, an organic electroluminescent device, an organic photoelectric receiving device, an organic thin film transistor, a cold electron-emission device, a fuel cell and a catalyst.

Abstract: A vertical PNP device in a silicon-germanium (SiGe) BiCMOS process is disclosed. The device is formed in a deep N-well and includes a collector region, a base region and an emitter region. The collector region has a two-dimensional L-shaped structure composed of a lightly doped first P-type ion implantation region and a heavily doped second P-type ion implantation region. The collector region is picked up by P-type pseudo buried layers formed at bottom of the shallow trench field oxide regions. A manufacturing method of vertical PNP device in a SiGe BiCMOS process is also disclosed. The method is compatible with the manufacturing processes of a SiGe heterojunction bipolar transistor in the SiGe BiCMOS process.

Abstract: A semiconductor device includes a substrate; a first nitride semiconductor layer provided over the substrate and having a nitride-polar surface; a gate electrode provided over the first nitride semiconductor layer; and a semiconductor layer provided on the first nitride semiconductor layer and only under the gate electrode, and exhibiting a polarization.

Abstract: According to one exemplary embodiment, a fin-based bipolar junction transistor (BJT) includes a wide collector situated in a semiconductor substrate. A fin base is disposed over the wide collector. Further, a fin emitter and an epi emitter are disposed over the fin base. A narrow base-emitter junction of the fin-based BJT is formed by the fin base and the fin emitter and the epi emitter provides increased current conduction and reduced resistance for the fin-based BJT. The epi emitter can be epitaxially formed on the fin emitter and can comprise polysilicon. Furthermore, the fin base and the fin emitter can each comprise single crystal silicon.

Abstract: A semiconductor device may include a semiconductor body of silicon carbide (SiC) and a field effect transistor. The field effect transistor has the semiconductor body that includes a drift region. A polycrystalline silicon layer is formed over or on the semiconductor body, wherein the polycrystalline silicon layer has an average particle size in the range of 10 nm to 5 ?m, and includes a source region and a body region. Furthermore, the field effect transistor includes a layer adjacent to the body region gate structure.

Abstract: A p-type SiC semiconductor includes a SiC crystal that contains Al and Ti as impurities, wherein the atom number concentration of Ti is equal to or less than the atom number concentration of Al. It is preferable that the concentration of Al and the concentration of Ti satisfy the following relations: (Concentration of Al)?5×1018/cm3; and 0.01%?(Concentration of Ti)/(Concentration of Al)?20%. It is more preferable that the concentration of Al and the concentration of Ti satisfy the following relations: (Concentration of Al)?5×1018/cm3; and 1×1017/cm3?(Concentration of Ti)?1×1018/cm3.

Abstract: A semiconductor device includes a semiconductor diode. The semiconductor diode includes a drift region and a first semiconductor region of a first conductivity type formed in or on the drift region. The first semiconductor region is electrically coupled to a first terminal via a first surface of a semiconductor body. The semiconductor diode includes a channel region of a second conductivity type electrically coupled to the first terminal, wherein a bottom of the channel region adjoins the first semiconductor region. A first side of the channel region adjoins the first semiconductor region.

Abstract: This disclosure provides systems, methods and apparatus for fabricating thin film transistor devices. In one aspect, a substrate including a silicon layer on the substrate surface is provided. A metal layer is formed on the silicon layer. A first dielectric layer is formed on the metal layer and exposed regions of the substrate surface. The metal layer and the silicon layer are treated, and the metal layer reacts with the silicon layer to form a silicide layer and a gap between the silicide layer and the dielectric layer. An amorphous silicon layer is formed on the first dielectric layer. The amorphous silicon layer is heated and cooled. The amorphous silicon layer overlying the substrate surface cools at a faster rate than the amorphous silicon layer overlying the gap.

Abstract: It is an object to provide a semiconductor device which has a large size and operates at high speed. A top gate transistor which includes a semiconductor layer of single-crystal and a bottom gate transistor which includes a semiconductor layer of amorphous silicon (microcrystalline silicon) are formed over the same substrate. Then, gate electrodes of each transistor are formed with the same layer, and source and drain electrodes are also formed with the same layer. Thus, manufacturing steps are reduced. In other words, two types of transistors can be manufactured by adding only a few steps to the manufacturing process of a bottom gate transistor.

Abstract: A semiconductor device includes an active body having two sidewalls facing each other in a lateral direction, a junction formed in a sidewall of the two sidewalls, a dielectric layer having an open portion to expose the junction and covering the active body, a junction extension portion having a buried region to fill the open portion, and a bit line coupled to the junction extension portion.

Abstract: Provided is a silicon wafer which is stabilized in quality exerting no adverse influence on device characteristics and manufactured by restricting a boron contamination from the environment, and a manufacturing process therefor. Concretely, the silicon wafer is characterized by an attached boron amount thereon being 1×1010 atoms/cm2 or less. In order to manufacture such a wafer as contains a small amount of boron attached on the wafer surface, the wafer is treated in an atmosphere of boron concentration of 15 ng/m3 or less. Boron-less filters and boron adsorbing filters are used as filters in a clean room and the like so as to lower the boron concentration in the atmosphere.

Abstract: A first single crystal substrate has a first side surface and it is composed of silicon carbide. A second single crystal substrate has a second side surface opposed to the first side surface and it is composed of silicon carbide. A bonding portion connects the first and second side surfaces to each other between the first and second side surfaces, and it is composed of silicon carbide. At least a part of the bonding portion has polycrystalline structure. Thus, a large-sized silicon carbide substrate allowing manufacturing of a semiconductor device with high yield can be provided.

Abstract: A photonic device, a method of making the device and a nano-scale antireflector employ a bramble of nanowires. The photonic device and the method include a first layer of a microcrystalline material provided on a substrate surface and a second layer of a microcrystalline material provided on the substrate surface horizontally spaced from the first layer by a gap. The photonic device and the method further include, and the nano-scale antireflector includes, the bramble of nanowires formed between the first layer and the second layer. The nanowires have first ends integral to crystallites in each of the first layer and the second layer. The nanowires of the bramble extend into the gap from each of the first layer and the second layer.

Abstract: A vertical heterojunction bipolar transistor (HBT) includes doped polysilicon having a doping of a first conductivity type as a wide-gap-emitter with an energy bandgap of about 1.12 eV and doped single crystalline Ge having a doping of the second conductivity type as the base having the energy bandgap of about 0.66 eV. Doped single crystalline Ge having of doping of the first conductivity type is employed as the collector. Because the base and the collector include the same semiconductor material, i.e., Ge, having the same lattice constant, there is no lattice mismatch issue between the collector and the base. Further, because the emitter is polycrystalline and the base is single crystalline, there is no lattice mismatch issue between the base and the emitter.

Abstract: Methods for fabricating bipolar junction transistors with self-aligned emitter and extrinsic base, bipolar junction transistors made by the methods, and design structures for a BiCMOS integrated circuit. The bipolar junction transistor is fabricated using a sacrificial emitter pedestal that provides a sacrificial mandrel promoting self-alignment between the emitter and the extrinsic base. The sacrificial emitter pedestal is subsequently removed to open an emitter window extending to the intrinsic base. An emitter is formed in the emitter window that lands on the intrinsic base.

Abstract: A method provides forming a photovoltaic (PV) cell. The PV cell may be, e.g. a heterojunction with intrinsic thin layer (HIT) cell. The method includes forming a crystalline semiconductor layer over a substrate. The crystalline semiconductor layer is heated above a melting temperature of the semiconductor. A portion of the crystalline semiconductor layer is thereby converted to a quenched amorphous semiconductor layer.

Abstract: Disclosed is a method of forming a heterojunction bipolar transistor (HBT), comprising depositing a first stack comprising an polysilicon layer (16) and a sacrificial layer (18) on a mono-crystalline silicon substrate surface (10); patterning the first stack to form a trench (22) extending to the substrate; depositing a silicon layer (24) over the resultant structure; depositing a silicon-germanium-carbon layer (26) over the resultant structure; selectively removing the silicon-germanium-carbon layer (26) from the sidewalls of the trench (22); depositing a boron-doped silicon-germanium-carbon layer (28) over the resultant structure; depositing a further silicon-germanium-carbon layer (30) over the resultant structure; depositing a boron-doped further silicon layer (32) over the resultant structure; forming dielectric spacers (34) on the sidewalls of the trench (22); filling the trench (22) with an emitter material (36); exposing polysilicon regions (16) outside the side walls of the trench by selectively remo

Abstract: An optoelectronic device including two spaced apart electrodes; and at least one layer containing ternary core/shell nanocrystals disposed between the spaced electrodes and having ternary semiconductor cores containing a gradient in alloy composition and wherein the ternary core/shell nanocrystals exhibit single molecule non-blinking behavior characterized by on times greater than one minute or radiative lifetimes less than 10 ns.

Abstract: Embodiments of the present invention generally relate to methods of forming epitaxial layers and devices having epitaxial layers. The methods generally include forming a first epitaxial layer including phosphorus and carbon on a substrate, and then forming a second epitaxial layer including phosphorus and carbon on the first epitaxial layer. The second epitaxial layer has a lower phosphorus concentration than the first epitaxial layer, which allows for selective etching of the second epitaxial layer and undesired amorphous silicon or polysilicon deposited during the depositions. The substrate is then exposed to an etchant to remove the second epitaxial layer and undesired amorphous silicon or polysilicon. The carbon present in the first and second epitaxial layers reduces phosphorus diffusion, which allows for higher phosphorus doping concentrations. The increased phosphorus concentrations reduce the resistivity of the final device.

Abstract: A hybrid silicon wafer which is a silicon wafer having a structure wherein the main plane orientation of polycrystalline silicon that is prepared by a unidirectional solidification/melting method is (311), and monocrystalline silicon is embedded in the polycrystalline silicon. The hybrid silicon wafer according to any one of claims 1 to 6, wherein the purity of the polycrystalline silicon portion excluding gas components is 6N or higher, the total amount of metal impurities is 1 wtppm or less, and, among the metal impurities, Cu, Fe, Ni, and Al are respectively 0.1 wtppm or less. Thus, a hybrid silicon wafer having the functions of both a polycrystalline silicon wafer and a monocrystalline silicon wafer is provided and the occurrence of polish bumps and macro-sized unevenness between the polycrystalline silicon and the monocrystalline silicon are prevented.

Abstract: Disclosed are methods and materials useful in the preparation of semiconductor devices. In particular embodiments, disclosed are methods for engineering polycrystalline aluminum nitride substrates that are thermally matched to further materials that can be combined therewith. For example, the polycrystalline aluminum nitride substrates can be engineered to have a coefficient of thermal expansion (CTE) that is closely matched to the CTE of a semiconductor material and/or to a material that can be used as a growth substrate for a semiconductor material. The invention also encompasses devices incorporating such thermally engineered substrates and semiconductor materials grown using such thermally engineered substrates. The thermally engineered substrates are advantageous for overcoming problems caused by damage arising from CTE mismatch between component layers in semiconductor preparation methods and materials.

Abstract: A semiconductor structure that is to be heated. The structure includes a substrate for the front face deposition of a useful layer intended to receive components for electronics, optics or optoelectronics. The structure contains doped elements that absorb infrared radiation so as to substantially increase infrared absorption by the structure so that the front face reaches a given temperature when a given infrared power is supplied to the structure. At least one part of the doped elements have insufficient electrical activity or localization in the structure, such that they cannot disturb the operation of the components. In addition, a method of producing this structure and a method of forming a useful layer of semiconductor material on the structure.

Abstract: The present disclosure reduces and, in some instances, eliminates the density of interface states in III-V compound semiconductor materials by providing a thin crystalline interlayer onto an upper surface of a single crystal III-V compound semiconductor material layer to protect the crystallinity of the single crystal III-V compound semiconductor material layer's surface atoms prior to further processing of the structure.

Abstract: A hetero-crystalline semiconductor device and a method of making the same include a non-single crystalline semiconductor layer and a nanostructure layer that comprises a single crystalline semiconductor nanostructure integral to a crystallite of the non-single crystalline semiconductor layer.

Abstract: A spin injection device and spin transistor including a spin injection device. A spin injection device includes different semiconductor materials and a spin-polarizing ferromagnetic material there between. The semiconductor materials may have different crystalline structures, e.g., a first material can be polycrystalline or amorphous silicon, and a second material can be single crystalline silicon. Charge carriers are spin-polarized when the traverse the spin-polarizing ferromagnetic material and injected into the second semiconductor material. A Schottky barrier height between the first semiconductor and ferromagnetic materials is larger than a second Schottky barrier height between the ferromagnetic and second semiconductor materials. A spin injection device may be a source of a spin field effect transistor.

Abstract: It is an object to provide an epitaxial silicon wafer that is provided with an excellent gettering ability in which a polysilicon layer is formed on the rear face side of a silicon crystal substrate into which phosphorus (P) and germanium (Ge) have been doped. A silicon epitaxial layer is grown by a CVD method on the surface of a silicon crystal substrate into which phosphorus and germanium have been doped at a high concentration. After that, a PBS forming step for growing a polysilicon layer is executed on the rear face side of a silicon crystal substrate. By the above steps, the number of LPDs (caused by an SF) that occur on the surface of the epitaxial silicon wafer due to the SF can be greatly reduced.

Abstract: A semiconductor light-emitting device which includes: a single-crystal substrate formed with a plurality of projection portions on a c-plane main surface; an intermediate layer which is formed to cover the main surface of the single-crystal substrate, in which a film thickness t2 on the projection portion is smaller than a film thickness t1 on the c-plane surface, in which the film thickness t2 on the projection portion is 60% or more of the film thickness t1 on the c-plane surface, and which includes AlN having a single-crystal phase on the c-plane surface and a polycrystalline phase on the projection portion; and a semiconductor layer which is formed on the intermediate layer and includes a group III nitride semiconductor.

Abstract: A method for simultaneous recrystallization and doping of semiconductor layers, in particular for the production of crystalline silicon thin layer solar cells. A substrate base layer 1 is produced, and subsequently, an intermediate layer system 2 which has at least one doped partial layer is deposited on the base layer. An absorber layer 3 which is undoped or likewise doped is deposited on the intermediate layer system 2, and in a recrystallisation step, the absorber layer 3 is heated, melted, cooled and tempered. Alternately, instead of an undoped capping layer, a capping layer system 4 which has at least one partial layer can also be applied on the absorber layer 3.