Non-single Crystal, Or Recrystallized, Material Forms Active Junction With Single Crystal Material (e.g., Monocrystal To Polycrystal Pn Junction Or Heterojunction) Patents (Class 257/51)
-
Patent number: 7132677Abstract: An GaN light emitting diode (LED) having a nanorod (or, nanowire) structure is disclosed. The GaN LED employs GaN nanorods in which a n-type GaN nanorod, an InGaN quantum well and a p-type GaN nanorod are subsequently formed in a longitudinal direction by inserting the InGaN quantum well into a p-n junction interface of the p-n junction GaN nanorod. In addition, a plurality of such GaN nanorods are arranged in an array so as to provide an LED having much greater brightness and higher light emission efficiency than a conventional laminated-film GaN LED.Type: GrantFiled: February 13, 2004Date of Patent: November 7, 2006Assignee: Dongguk UniversityInventors: Hwa-Mok Kim, Tae-Won Kang, Kwan-Soo Chung
-
Patent number: 7129123Abstract: In a method for producing an SOI wafer comprising steps of implanting ions from a bond wafer surface to form an ion-implanted layer inside the wafer, bonding the ion-implanted bond wafer surface and a surface of a base wafer via an oxide film or directly, and forming an SOI wafer by delaminating by heat treatment a part of the bond wafer at the ion-implanted layer, the bond wafer is a silicon wafer that consists of a silicon single crystal grown by Czochralski method, that is occupied by N region outside OSF generated in a ring shape and that has no defect region detected by Cu deposition method. Thereby, even an extremely thin SOI layer having a thickness of 200 nm or less, can provide an SOI wafer that has an excellent electric property without micro pits caused by acid cleaning, and can be produced without increasing the number of processes.Type: GrantFiled: October 24, 2003Date of Patent: October 31, 2006Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Masahiro Sakurada, Nobuaki Mitamura, Izumi Fusegawa, Tomohiko Ohta
-
Patent number: 7122864Abstract: A semiconductor substrate is disclosed which comprises a first single crystal silicon layer, an insulator formed to partially cover one main surface of the first single crystal silicon layer, a second single crystal silicon layer formed to cover a region of the first single crystal silicon layer which is not covered with the insulator, and to cover an edge portion of the insulator adjacent to the region, and a non-single crystal silicon layer formed on the insulator, the interface between the non-single crystal silicon layer and the second single crystal silicon layer being positioned on the insulator.Type: GrantFiled: May 16, 2003Date of Patent: October 17, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Hajime Nagano, Kiyotaka Miyano, Ichiro Mizushima
-
Patent number: 7109528Abstract: With a solar ball 10 serving as a light-receiving semiconductor apparatus, the outer surface of a spherical solar cell 1 is covered with a light-transmitting outer shell member 11, and electrode members 14, 15 are connected to electrodes 6, 7 of the solar cell 1. The outer shell member 11 comprises a capsule 12 produced by bonding together two halves, and a filler 13 that is packed inside this capsule and cured. A solar panel can be configured such that a plurality of the solar balls 10 are arrayed in a matrix and connected in parallel and in series, or a solar panel can be configured such that a multiplicity of spherical solar cells 1 are arrayed in a matrix and covered with a transparent outer shell member. A solar string in the form of a rod or cord can be configured such that a plurality of the solar cells 1 are arrayed in columns and connected in parallel, and then covered with a transparent outer shell member.Type: GrantFiled: December 25, 2001Date of Patent: September 19, 2006Inventor: Josuke Nakata
-
Patent number: 7105866Abstract: High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.Type: GrantFiled: August 5, 2004Date of Patent: September 12, 2006Assignee: Freescale Semiconductor, Inc.Inventors: Nada El-Zein, Jamal Ramdani, Kurt Eisenbeiser, Ravindranath Droopad
-
Patent number: 7098498Abstract: Hot-electron injection driven by hole impact ionization in the channel-to-drain junction of a p-channel MOSFET provides a new mechanism for writing a floating-gate memory. Various pFET floating-gate structures use a combination of this mechanism and electron tunneling to implement nonvolatile analog memory, nonvolatile digital memory, or on-line learning in silicon. The memory is nonvolatile because the devices use electrically isolated floating gates to store electronic charge. The devices enable on-line learning because the electron injection and tunneling mechanisms that write the memory can occur during normal device operation. The memory updates and learning are bidirectional because the injection and tunneling mechanisms add and remove electrons from the floating gate, respectively. Because the memory updates depend on both the stored memory and the pFETs terminal voltages, and because they are bidirectional, the devices can implement on-line learning functions.Type: GrantFiled: August 9, 2004Date of Patent: August 29, 2006Assignee: California Institute of TechnologyInventors: Christopher J. Diorio, Todd E. Humes
-
Patent number: 7078727Abstract: Nickel is selectively held in contact with a particular region of an amorphous silicon film. Crystal growth parallel with a substrate is effected by performing a heat treatment. A thermal oxidation film is formed on the silicon film by performing a heat treatment in an oxidizing atmosphere containing a halogen element. During this step, in the silicon film, impurities included such as oxygen or chlorine, are segregated with extending along the crystal growth, the crystallinity is improved, and the gettering of nickel element proceeds. A thin-film transistor is formed so that the direction connecting source and drain regions coincides with the above crystal growth direction. As a result, a TFT having superior characteristics such as a mobility larger than 200 cm2/Vs and an S value smaller than 100 mV/dec. can be obtained.Type: GrantFiled: October 29, 2002Date of Patent: July 18, 2006Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Satoshi Teramoto, Jun Koyama, Yasushi Ogata, Masahiko Hayakawa, Mitsuaki Osame, Hisashi Ohtani, Toshiji Hamatani
-
Patent number: 7074630Abstract: A light emitting layer including a quantum structure and the forming method of forming the same is provided. The forming method includes several steps. At first, a compound dielectric layer forms, including a dielectric layer and an impure dielectric layer, which comprises major elements and impurities. The compound dielectric layer is treated to drive the impurities to form the quantum structure in the dielectric layer according to the difference in characteristic between the major elements and impurities. For example, oxidizing the major elements to drive the impurities of the impure dielectric layer to form the quantum structure inside the dielectric layer, because the oxidizing capability of the major elements is stronger than that of the impurities. The quantum structure and compound dielectric layer construct the light emitting layer.Type: GrantFiled: May 20, 2003Date of Patent: July 11, 2006Assignee: United Microelectronics Corp.Inventors: Ting-Chang Chang, Po-Tsun Liu
-
Patent number: 7005676Abstract: There is here disclosed a semiconductor device manufacturing method comprising a step of forming an island region including a monocrystalline Si1-x-yGexCy layer (1>x>0, 1>y?0) and a peripheral region including an amorphous or polycrystalline Si1-x-yGexCy layer which surrounds the island region on a monocrystalline Si layer on an insulating film, a step of subjecting the respective Si1-x-yGexCy layers to heat treatment, and after the heat treatment and the removal of a surface oxide film, a step of forming a monocrystalline Si1-z-wGezCw layer (1>z?0, 1>w?0) which becomes an element formation region on the island region.Type: GrantFiled: July 29, 2003Date of Patent: February 28, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Tsutomu Tezuka, Shinichi Takagi
-
Patent number: 6982195Abstract: An amorphous silicon layer is formed on a substrate, and then a protective layer and a reflective layer are formed in turn to form a film stack on portions of the amorphous silicon layer. The reflective layer is a metal material with reflectivity of laser, and the protective layer is able to prevent metal diffusion. When an excimer laser heats the amorphous silicon layer to crystallize the amorphous silicon, nucleation sites are formed in the amorphous silicon layer under the film stack of the protective layer and the reflective layer. Next, laterally expanding crystallization occurs in the amorphous silicon layer to form poly-silicon having crystal grains with size of micrometers and high grain order.Type: GrantFiled: February 19, 2004Date of Patent: January 3, 2006Assignee: Industrial Technology Research InstituteInventors: Jia-Xing Lin, Chi-Lin Chen, Yu-Cheng Chen
-
Patent number: 6914307Abstract: A semiconductor device includes a semiconductor layer, a plurality of semiconductor elements formed on the semiconductor layer, and an isolation film provided in a surface of the semiconductor layer, semiconductor elements being electrically isolated from each other by the isolation film. The semiconductor device also includes a PN junction portion provided under the isolation film and formed by two semiconductor regions of different conductivity types in the semiconductor layer. The isolation film includes a nitride film provided in a position corresponding to a top of the PN junction portion and has a substantially uniform thickness across the two semiconductor regions and an upper oxide film and a lower oxide film which are provided in upper and lower portions of the nitride film. The surface of the semiconductor layer is silicidized in such a state that a surface of the isolation film is exposed.Type: GrantFiled: September 9, 2003Date of Patent: July 5, 2005Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Toshiaki Iwamatsu, Takashi Ipposhi, Hideki Naruoka, Nobuyoshi Hattori, Shigeto Maegawa, Yasuo Yamaguchi, Takuji Matsumoto
-
Patent number: 6909115Abstract: There is disclosed a semiconductor device and a method of fabricating the semiconductor device in which a heat treatment time required for crystal growth is shortened and a process is simplified. Two catalytic element introduction regions are arranged at both sides of one active layer and crystallization is made. A boundary portion where crystal growth from one catalytic element introduction region meets crystal growth from the other catalytic element introduction region is formed in a region which becomes a source region or drain region.Type: GrantFiled: March 14, 2003Date of Patent: June 21, 2005Assignee: Semiconductor Energy Laboratory Co. Ltd.Inventors: Chiho Kokubo, Hirokazu Yamagata, Shunpei Yamazaki
-
Patent number: 6903967Abstract: A memory having gate structures adjacent opposing sidewalls of a semiconductor structure including a channel region and a plurality of charge storage locations between the gate structures and the opposing sidewalls. The channel region is located between two current terminal regions, which in one example serve as the source/drain regions. A memory cell can be implemented in an array of memory cells wherein one gate structure is coupled to one word line and the other gate structure is coupled to another word line. In one example, each cell includes four charge storage locations, each for storing one bit of data.Type: GrantFiled: May 22, 2003Date of Patent: June 7, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Leo Mathew, Robert F. Steimle, Ramachandran Muralidhar
-
Patent number: 6903367Abstract: Various embodiments provide a decoder for a memory array, comprising an array of address and output lines, vertical pillars, vertical floating gate transistors, and buried source lines. Each pillar includes single crystalline first and second contact layers separated by an oxide layer. Each floating gate transistor is formed in a single crystalline layer, having a thickness less than 10 nanometers, selectively disposed on a side of one of the pillars. Each transistor includes first and second source/drain regions in contact with the first and second contact layers, respectively, a body region opposing the oxide layer and contacting the first and second source/drain regions, and a floating gate opposing the body region. The source lines are disposed below the pillars and interconnect the first contact layer of pillars. Each of the address lines is disposed between rows of pillars and serves as a control gate.Type: GrantFiled: August 8, 2003Date of Patent: June 7, 2005Assignee: Micron Technology Inc.Inventor: Leonard Forbes
-
Patent number: 6864520Abstract: A method (and structure) for an electronic chip having at least one layer of material for which a carrier mobility of a first carrier type is higher in a first crystal surface than in a second crystal surface and for which a carrier mobility of a second carrier type is higher in the second crystal surface than the first crystal surface includes a first device having at least one component fabricated on the first crystal surface of the material, wherein an activity of the component of the first device involves primarily the first carrier type, and a second device having at least one component fabricated on the second crystal surface of the material, wherein an activity of the component of the second device involves primarily the second carrier type.Type: GrantFiled: April 4, 2002Date of Patent: March 8, 2005Assignee: International Business Machines CorporationInventors: Massimo V. Fischetti, Steven E. Laux, Paul M. Solomon, Hon-Sum Philip Wong
-
Patent number: 6825491Abstract: The present invention concerns an integrated variable capacitance device comprising at least one membrane (12) forming at least one mobile armature and having at least one principal face facing at least one fixed armature. In accordance with the invention, the membrane has at least one rigidity rib (32) lying in a perpendicular direction to said principal face. Application in the production of resonant filters.Type: GrantFiled: October 15, 2002Date of Patent: November 30, 2004Assignee: Commissariat a l'Energie AtomiqueInventor: Gilles Delapierre
-
Patent number: 6812490Abstract: The present invention provide an LDD type TFT having excellent properties, particularly for a liquid crystal display unit. For this purpose, a top gate type LDDTFT gate electrode is converted into a two-stage structure by use of a chemical reaction or plating, and furthermore, into a shape in which an upper portion or a lower portion slightly protrudes on the source electrode side, or the drain electrode side relative to the other portions. Impurities are injected by using this electrode having this structure and shape as a mask. Prior to injection of impurities, the gate insulating film is removed, and a Ti film is formed for preventing hydrogen for dilution from coming in. This is also the case with the LDD-TFT on the bottom gate side.Type: GrantFiled: June 30, 2003Date of Patent: November 2, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Shin-itsu Takehashi, Shigeo Ikuta, Tetsuo Kawakita, Mayumi Inoue, Keizaburo Kuramasu
-
Patent number: 6809012Abstract: The present invention is characterized in that gettering is performed such that impurity regions to which a noble gas element is added are formed in a semiconductor film and the metallic element included in the semiconductor film is segregated into the impurity regions by laser annealing. Also, a reflector is provided under a substrate on which a semiconductor film is formed. When laser light transmitted through the semiconductor film substrate is irradiated from the front side of the substrate, the laser beam is reflected by the reflector and thus the laser light can be irradiated to the semiconductor film from the read side thereof. Laser light can be also irradiated to low concentration impurity regions overlapped with a portion the gate electrode. Thus, an effective energy density in the semiconductor film is increased to thereby effect recovery of crystallinity and activation of the impurity element.Type: GrantFiled: January 3, 2002Date of Patent: October 26, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Satoshi Murakami, Hideto Ohnuma, Osamu Nakamura, Koichiro Tanaka, Yasuyuki Arai
-
Patent number: 6765229Abstract: A silicon film provided on a blocking film 102 on a substrate 101 is made amorphous by doping Si+, and in a heat-annealing process, crystallization is started in parallel to a substrate from an area 100 where nickel serving as a crystallization-promoting catalyst is introduced.Type: GrantFiled: November 2, 2001Date of Patent: July 20, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hongyong Zhang, Yasuhiko Takemura, Toru Takayama
-
Patent number: 6734499Abstract: An insulated gate field effect transistor comprises a non-single-crystalline semiconductor layer formed on a substrate, a gate electrode is formed on a portion of the surface of said semiconductor layer, and a gate insulating film is disposed between said gate electrode and said semiconductor layer. A non-single-crystalline channel region is defined within said semiconductor layer just below said gate electrode. A source region and a drain region are transformed from and defined within said semiconductor layer immediately adjacent to said channel region in an opposed relation, said source and drain regions being crystallized to a higher degree than that of said channel region by selectively irradiating portions of said semiconductor layer using said gate electrode as a mask.Type: GrantFiled: September 28, 1999Date of Patent: May 11, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
-
Patent number: 6720575Abstract: An insulating film 103 for making an under insulating layer 104 is formed on a quartz or semiconductor substrate 100. Recesses 105a to 105d corresponding to recesses 101a to 101d of the substrate 100 are formed on the surface of the insulating film 103. The surface of this insulating film 103 is flattened to form the under insulating layer 104. By this flattening process, the distance L1, L2, . . . , Ln between the recesses 106a, 106b, 106d of the under insulating layer 104 is made 0.3 &mgr;m or more, and the depth of the respective recesses is made 10 nm or less. The root-mean-square surface roughness of the surface of the under insulating film 104 is made 0.3 nm or less. By this, in the recesses 106a, 106b, 106d, it can be avoided to block crystal growth of the semiconductor thin film, and crystal grain boundaries can be substantially disappeared.Type: GrantFiled: October 4, 2002Date of Patent: April 13, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Akiharu Miyanaga, Toru Mitsuki, Hisashi Ohtani
-
Patent number: 6717178Abstract: A thin film transistor includes an active silicon layer deposited by physical vapor deposition (PVD), wherein a silicon precursor is doped with impurities prior to use as a target in the PVD chamber, wherein the precursor has a resistivity in the range of about 0.5 &OHgr;-cm<&rgr;s<60 &OHgr;-cm; and wherein the target includes plural, rectangular tiles wherein all individual tiles are larger than 8.5 inches square.Type: GrantFiled: August 13, 2002Date of Patent: April 6, 2004Assignee: Sharp Laboratories of America, Inc.Inventors: Yukihiko Nakata, Apostolos Voutsas, John Hartzell
-
Patent number: 6713819Abstract: An integrated circuit formed in semiconductor-on-insulator format. The integrated circuit includes a layer of semiconductor material disposed on an insulating layer, where the insulating layer disposed on a substrate. A first and a second MOSFET are provided such that one of a source and a drain of the first MOSFET is disposed adjacent one of a source and a drain of the second MOSFET. An amorphous region is formed in the layer of semiconductor material and extending from an upper surface of the layer of semiconductor material to the isolation layer. The amorphous region is formed between a crystalline portion of the one of the source and the drain of the first MOSFET and a crystalline portion of the one of the source and the drain of the second MOSFET.Type: GrantFiled: April 8, 2002Date of Patent: March 30, 2004Assignee: Advanced Micro Devices, Inc.Inventors: William G. En, Dong-Hyuk Ju, Srinath Krishnan
-
Patent number: 6700133Abstract: A film having a high thermal conductivity material such as aluminum nitride is formed on a substrate, and then a silicon film is formed. When a laser light or an intense light corresponding to the laser light is irradiated to the silicon film, since the aluminum nitride film absorbs heat, a portion of the silicon film near the aluminum nitride film is solidified immediately. However, since a solidifying speed is slow in another portion of the silicon film, crystallization progresses from the portion near the aluminum nitride film. When a substrate temperature is 400° C. or higher at laser irradiation, since a solidifying speed is decreased, a crystallinity of the silicon film is increased. Also, when the substrate is thin, the crystallinity of the silicon film is increased.Type: GrantFiled: September 18, 2000Date of Patent: March 2, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hisashi Ohtani, Yasuhiko Takemura, Akiharu Miyanaga, Shunpei Yamazaki
-
Publication number: 20040012019Abstract: A compact light weight printhead capable of direct quasi contact printing includes an OLED Color Filter structure deposited onto a substrate. The OLED-Color Filter structure includes an OLED structure emitting over a broad range of wavelengths and color filter arrays that selectively transmit radiation in different distinct ranges of wavelengths. The printhead is designed for contact or quasi-contact printing printing, without additional optical elements. The printhead design ensures that the desired pixel sharpness and reduced crosstalk is achieved. Two possible different arrangements for the printhead are disclosed. One arrangement includes at least one array of OLED elements and at least one color filter array. Each color filter array in this arrangement includes at least one triplet if color filters, and each element in each the triplet is capable of transmitting radiation in a distinct wavelength range different from the distinct wavelength range of the other two color filters in the same triplet.Type: ApplicationFiled: July 9, 2003Publication date: January 22, 2004Applicant: Polaroid CorporationInventors: Russell A. Gaudiana, Richard G. Egan
-
Publication number: 20040012020Abstract: A compact light weight printhead capable of direct quasi-contact printing includes an OLED-Color Filter structure deposited onto a substrate. The OLED-Color Filter structure includes an OLED structure emitting over a broad range of wavelengths and color filter arrays that selectively transmit radiation in different distinct ranges of wavelengths. The printhead is designed for contact or quasi-contact printing printing, without additional optical elements. The printhead design ensures that the desired pixel sharpness and reduced crosstalk is achieved. Two possible different arrangements for the printhead are disclosed. One arrangement includes at least one array of OLED elements and at least one color filter array. Each color filter array in this arrangement includes at least one triplet of color filters, and each element in each the triplet is capable of transmitting radiation in a distinct wavelength range different from the distinct wavelength range of the other two color filters in the same triplet.Type: ApplicationFiled: July 9, 2003Publication date: January 22, 2004Applicant: Polaroid CorporationInventors: Russell A. Gaudiana, Richard G. Egan
-
Patent number: 6680487Abstract: There is disclosed a semiconductor device and a method of fabricating the semiconductor device in which a heat time required for crystal growth is shortened and a process is simplified. Two catalytic element introduction regions are arranged at both sides of one active layer and crystallization is made. A boundary portion where crystal growth from one catalytic element introduction region meets crystal growth from the other catalytic element introduction region is formed in a region which becomes a source region or drain region.Type: GrantFiled: May 8, 2000Date of Patent: January 20, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Chiho Kokubo, Hirokazu Yamagata, Shunpei Yamazaki
-
Patent number: 6664566Abstract: A photoelectric conversion device has a non-single-crystal semiconductor laminate member formed on a substrate having a conductive surface, and a conductive layer formed on the non-single-crystal semiconductor laminate member. The non-single-crystal semiconductor laminate member has such a structure that a first non-single-crystal semiconductor layer having a P or N first conductivity type, an I-type second non-single-crystal semiconductor layer and a third non-single-crystal semiconductor layer having a second conductivity type opposite the first conductivity type are laminated in this order. The first (or third) non-single-crystal semiconductor layer is disposed on the side on which light is incident, and is P-type. The I-type non-single-crystal semiconductor layer has introduced thereinto a P-type impurity, such as boron which is distributed so that its concentration decreases towards the third (or first) non-single-crystal semiconductor layer in the thickwise direction of the I-type layer.Type: GrantFiled: January 30, 2001Date of Patent: December 16, 2003Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
-
Patent number: 6627919Abstract: A thermally stable nickel germanosilicide on SiGe integrated circuit device, and a method of making the same, is disclosed. During fabrication of the device iridium or cobalt is added at the Ni/SiGe interface to decrease the sheet resistance of the device. The device comprising nickel silicide with iridium on SiGe shows thermal stability at temperatures up to 800° C. The device comprising nickel silicide with cobalt on SiGe shows a decrease in the sheet resistance with temperature, i.e., the resistance remains low when annealing temperatures extend up to and beyond 800° C.Type: GrantFiled: December 12, 2002Date of Patent: September 30, 2003Assignee: Sharp Laboratories of America, Inc.Inventors: Jer-shen Maa, Douglas James Tweet, Sheng Teng Hsu
-
Publication number: 20030160232Abstract: A nitride semiconductor substrate including (a) a supporting substrate, (b) a first nitride semiconductor layer having a periodical T-shaped cross-section, having grown from periodically arranged stripe-like, grid-like or island-like portions on the supporting substrate, and (c) a second nitride semiconductor substrate covering said supporting substrate, having grown from the top and side surfaces of said first nitride semiconductor layer, wherein a cavity is formed under the second nitride semiconductor layer.Type: ApplicationFiled: March 18, 2003Publication date: August 28, 2003Applicant: Nichia CorporationInventors: Tokuya Kozaki, Hiroyuki Kiyoku, Kazuyuki Chocho, Hitoshi Maegawa
-
Patent number: 6605840Abstract: The scalable multi-bit flash memory cell includes three regions: the first-side region, the gate region, and the second-side region, in which the gate region includes two stack-gate transistors and one select-gate transistor. The first-side/second-side region comprises a sidewall-oxide spacer formed over the gate region and from top to bottom comprises a planarized thick-oxide layer, a silicided conductive layer formed on a flat bed, and a common-diffusion region. The stack-gate transistor comprises from top to bottom a sidewall dielectric spacer, an elongated control-gate layer formed over an intergate dielectric layer, and an integrated floating-gate layer. The select-gate transistor comprises a planarized conductive island formed over a gate-dielectric layer and is connected to a word line. A plurality of scalable multi-bit flash memory cells are alternately arranged to form a scalable multi-bit flash memory cell array.Type: GrantFiled: February 7, 2002Date of Patent: August 12, 2003Inventor: Ching-Yuan Wu
-
Publication number: 20030127652Abstract: An active matrix organic electroluminescent display device of the present invention is fabricated through a six-mask process unlike the related art that uses eight masks. In the present invention, since the ground line and the power line are entirely or over substantially disposed above the substrate, the resistance of the power line is reduced and thermal damage that may occur in the power line during driving the device is prevented. Therefore, the image quality increases and the uniformity in the display can be obtained. Furthermore, due to the reduction of the mask process, the occurrence of defects is reduced and the production yield can be raised. Additionally, the principle of the present invention can be applied to either the top emission type organic electroluminescent display device or the bottom emission type organic electroluminescent display device. When it is utilized for the top emission type, the active matrix organic electroluminescent display device can have a high aperture ratio.Type: ApplicationFiled: December 30, 2002Publication date: July 10, 2003Inventors: Jae-Yong Park, Joon-Kyu Park
-
Publication number: 20030098458Abstract: Nickel is selectively held in contact with a particular region of an amorphous silicon film. Crystal growth parallel with a substrate is effected by performing a heat treatment. A thermal oxidation film is formed on the silicon film by performing a heat treatment in an oxidizing atmosphere containing a halogen element. During this step, in the silicon film, impurities included such as oxygen or chlorine, are segregated with extending along the crystal growth, the crystallinity is improved, and the gettering of nickel element proceeds. A thin-film transistor is formed so that the direction connecting source and drain regions coincides with the above crystal growth direction. As a result, a TFT having superior characteristics such as a mobility larger than 200 cm2/Vs and an S value smaller than 100 mV/dec. can be obtained.Type: ApplicationFiled: January 13, 2003Publication date: May 29, 2003Applicant: Semiconductor Energy Laboratory Co. Ltd.Inventors: Shunpei Yamazaki, Satoshi Teramoto, Jun Koyama, Yasushi Ogata, Masahiko Hayakawa, Mitsuaki Osame, Hisashi Ohtani, Toshiji Hamatani
-
Patent number: 6566682Abstract: Structures and method for programmable memory address and decode circuits with ultra thin vertical body transistors are provided. The memory address and decode circuits includes a number of address lines and a number of output lines such that the address lines and the output lines form an array. A number of vertical pillars extend outwardly from a semiconductor substrate at intersections of output lines and address lines. Each pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer. A number of single crystalline ultra thin vertical floating gate transistors that are selectively disposed adjacent the number of vertical pillars.Type: GrantFiled: February 9, 2001Date of Patent: May 20, 2003Assignee: Micron Technology, Inc.Inventor: Leonard Forbes
-
Patent number: 6548370Abstract: A laser annealing method for obtaining a crystalline semiconductor film having a large grain size is provided. Laser light is irradiated to the top surface and the bottom surface of an amorphous semiconductor film when crystallizing the amorphous semiconductor film by laser light irradiation.Type: GrantFiled: August 17, 2000Date of Patent: April 15, 2003Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kenji Kasahara, Ritsuko Kawasaki, Hisashi Ohtani, Shunpei Yamazaki
-
Patent number: 6538268Abstract: A semiconductor device has a MOSFET formed on a single crystalline silicon layer in an SOI structure in which the silicon layer is laminated along with an insulator on a handle wafer. To prevent the body floating effect, a recombination center region is formed connecting to the lower surfaces of source and drain regions of the MOSFET. Consequently, the holes generated within the single crystalline silicon layer just beneath a channel of the MOSFET are injected into the recombination center region by way of the single crystalline silicon layer beneath the source diffusion region and eliminated so that the body floating effect is prevented.Type: GrantFiled: September 20, 1999Date of Patent: March 25, 2003Assignee: Hitachi, Ltd.Inventor: Masatada Horiuchi
-
Patent number: 6531710Abstract: An ULSI MOSFET formed using silicon on insulator (SOI) principles includes masking regions of an amorphous silicon film on a substrate and exposing intended active regions. Laser energy is directed against the intended active regions to anneal these regions without annealing the masked regions, thereby increasing production throughput and decreasing defect density.Type: GrantFiled: May 10, 2001Date of Patent: March 11, 2003Assignee: Advanced Micro Devices, Inc.Inventor: Bin Yu
-
Patent number: 6528820Abstract: There is disclosed a method of fabricating a thin-film transistor having excellent characteristics. Nickel element is held in contact with selected regions of an amorphous silicon film. Then, thermal processing is performed to crystallize the amorphous film. Subsequently, thermal processing is carried out in an oxidizing ambient containing a halogen element to form a thermal oxide film. At this time, the crystallinity is improved. Also, gettering of the nickel element proceeds. This crystalline silicon film consists of crystals grown radially from a number of points. Consequently, the thin-film transistor having excellent characteristics can be obtained.Type: GrantFiled: January 17, 1997Date of Patent: March 4, 2003Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Satoshi Teramoto, Jun Koyama, Yasushi Ogata, Masahiko Hayakawa, Mitsuaki Osame, Hisashi Ohtani, Toshiji Hamatani
-
Patent number: 6515299Abstract: An insulating film 103 for making an under insulating layer 104 is formed on a quartz or semiconductor substrate 100. Recesses 105a to 105d corresponding to recesses 101a to 101d of the substrate 100 are formed on the surface of the insulating film 103. The surface of this insulating film 103 is flattened to form the under insulating layer 104. By this flattening process, the distance L1, L2, . . . , Ln between the recesses 106a, 106b, 106d of the under insulating layer 104 is made 0.3 &mgr;m or more, and the depth of the respective recesses is made 10 nm or less. The root-mean-square surface roughness of the surface of the under insulating film 104 is made 0.3 nm or less. By this, in the recesses 106a, 106b, 106d, it can be avoided to block crystal growth of the semiconductor thin film, and crystal grain boundaries can be substantially disappeared.Type: GrantFiled: June 16, 2000Date of Patent: February 4, 2003Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Akiharu Miyanaga, Toru Mitsuki, Hisashi Ohtani
-
Publication number: 20030020137Abstract: Various semiconductor device structures that include an inductor or balun can be formed using a semiconductor structure having a monocrystalline silicon substrate, an amorphous oxide material overlying the monocrystalline silicon substrate, a monocrystalline perovskite oxide material overlying the amorphous oxide material; and a monocrystalline compound semiconductor material overlying the monocrystalline perovskite oxide material, and/or other types of material such as metals and non-metals.Type: ApplicationFiled: July 25, 2001Publication date: January 30, 2003Applicant: MOTORLA, INC.Inventors: Bruce Allen Bosco, Rudy M. Emrick, Steven James Franson, Nestor Javier Escalera
-
Publication number: 20030020063Abstract: Composite semiconductor structures and devices are presented in which digital processing systems are formed. The structures and devices include a first semiconductor material (which can be a Group IV semiconductor such as silicon), an accommodating layer (which can be an oxide or nitride), and a second semiconductor material (which can be a compound semiconductor such as gallium arsenide). The first and second semiconductor materials and accommodating layer can be fabricated as a single integrated circuit chip. Computationally intensive functions, such as arithmetic logic functions, and other digital processing functions requiring high speed operation, such as information transfer, can be formed in the second semiconductor material while other functions, such as control and memory, can be formed in the first semiconductor material. Such formation of digital processing systems improves system performance.Type: ApplicationFiled: July 25, 2001Publication date: January 30, 2003Applicant: MOTOROLA, INC.Inventors: Steven F. Gillig, Barry W. Herold
-
Patent number: 6509650Abstract: The electronic device (1) has a layer (11) of a material comprising a first and a second element. This material has an amorphous and a crystalline state. A transition from the amorphous to the crystalline state can be effected by heating of the material to above a crystallization temperature, for example with a laser. As a result, the layer (11) has a first electrically conducting areas (21), comprising the material in the crystalline state, which are insulated from each other by the first electrically insulating area (23), comprising the material in the amorphous state. The layer (11) may be present as an interconnect layer, but also as a covering layer. Preferably, the material is aluminum-germanium. In the method of patterning a layer (11), electrically conductive areas of the layer can be strengthened by electroplating.Type: GrantFiled: June 1, 2001Date of Patent: January 21, 2003Assignee: Koninklijke Philips Electronics N.V.Inventors: Jan Johannes Van Den Broek, Coen Theodorus Hubertus Franciscus Liedenbaum, Andreas Hubertus Montree, Arjen Boogaard, Willem Reindert De Wild, Johannes Nicolaas Huiberts
-
Patent number: 6479885Abstract: An electrical device such as a diode usable in high voltage applications wherein the electrical device is fabricated from a method which yields a plurality of high voltage electrical devices, the present method including providing a substrate of a semiconductor material having a predetermined substrate conductive type, the substrate being typically formed from a monocrystalline growth method, forming a second epitaxial layer contiguous with the upper surface of the substrate, the epitaxial layer having a predetermined second layer conductive type, and thereafter forming a top layer of dopant, material in a predetermined pattern upon the upper surface of the second epitaxial layer. This predetermined pattern of dopant material typically takes the form of an array of patches which can be achieved through either a masking and etching process, or through a screen printing process.Type: GrantFiled: March 28, 2002Date of Patent: November 12, 2002Assignee: Fabtech, Inc.Inventors: Walter R. Buchanan, Roman J. Hamerski
-
Patent number: 6478263Abstract: Nickel is selectively held in contact with a particular region of an amorphous silicon film. Crystal growth parallel with a substrate is effected by performing a heat treatment. A thermal oxidation film is formed on the silicon film by performing a heat treatment in an oxidizing atmosphere containing a halogen element. During this step, in the silicon film, impurities included such as oxygen or chlorine, are segregated with extending along the crystal growth, the crystallinity is improved, and the gettering of nickel element proceeds. A thin-film transistor is formed so that the direction connecting source and drain regions coincides with the above crystal growth direction. As a result, a TFT having superior characteristics such as a mobility larger than 200 cm2/Vs and an S value smaller than 100 mV/dec. can be obtained.Type: GrantFiled: October 28, 1999Date of Patent: November 12, 2002Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Satoshi Teramoto, Jun Koyama, Yasushi Ogata, Masahiko Hayakawa, Mitsuaki Osame, Hisashi Ohtani, Toshiji Hamatani
-
Patent number: 6465805Abstract: Structures and method for programmable memory address and decode circuits with ultra thin vertical body transistors are provided. The memory address and decode circuits includes a number of address lines and a number of output lines such that the address lines and the output lines form an array. A number of vertical pillars extend outwardly from a semiconductor substrate at intersections of output lines and address lines. Each pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer. A number of single crystalline ultra thin vertical floating gate transistors that are selectively disposed adjacent the number of vertical pillars.Type: GrantFiled: February 9, 2001Date of Patent: October 15, 2002Assignee: Micron Technology, Inc.Inventor: Leonard Forbes
-
Patent number: 6448627Abstract: An improved antifuse design has been achieved by using a structure comprising a region of heavily doped N type silicon coated with a layer of ONO (oxide-nitride-oxide). Top contact to the ONO is made through a layer of tungsten silicide sandwiched between two layers of N type polysilicon. A cost effective method for manufacturing said antifuse structure is described.Type: GrantFiled: May 15, 1997Date of Patent: September 10, 2002Assignee: Chartered Semiconductor Manufacturing Ltd.Inventor: Calvin Leung Yat Chor
-
Patent number: 6448601Abstract: A decoder for a memory device is provided. The decoder array includes a number of address lines and a number of output lines. The address lines and the output lines form an array. The decoder includes a number of vertical pillars extending outwardly from a semiconductor substrate at intersections of output lines and address lines. Each pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer. The decoder further includes a number of single crystalline ultra thin vertical transistor that are selectively disposed adjacent the number of vertical pillars. Each single crystalline vertical transistor includes an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer, an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer, and an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions.Type: GrantFiled: February 9, 2001Date of Patent: September 10, 2002Assignee: Micron Technology, Inc.Inventors: Leonard Forbes, Kie Y. Ahn
-
Patent number: 6441396Abstract: A method is presented for measuring and monitoring the mechanical stress at the device level which occurs intrinsically during the fabrication process or which is induced via extrinsic means. The method applies the fact that the current-voltage (I-V) characteristics of a diode change as the diode is subjected to mechanical stress. The method is applicable to monitoring stress at the microscopic and device levels at various stages in the semiconductor wafer fabrication process. Apparatus for implementing the method is also presented.Type: GrantFiled: October 24, 2000Date of Patent: August 27, 2002Assignee: International Business Machines CorporationInventors: Edward D. Adams, Arne W. Ballantine, Richard S. Kontra, Alain Loiseau, James A. Slinkman
-
Patent number: 6437366Abstract: A thin film transistor of reversed stagger type having improved characteristics and yet obtained by a simple process, which is fabricated by selectively doping the semiconductor region on the gate dielectric to form the source, drain, and channel forming regions by using ion implantation, ion doping, or doping a plasma of ions; and then effecting rapid thermal annealing by irradiating a ultraviolet radiation, a visible light, or a near-infrared radiation for a short period of time. The source, drain, and channel forming regions are formed substantially within a single plane.Type: GrantFiled: November 17, 1999Date of Patent: August 20, 2002Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Yasuhiko Takemura
-
Publication number: 20020109138Abstract: Structures and method for programmable memory address and decode circuits with ultra thin vertical body transistors are provided. The memory address and decode circuits includes a number of address lines and a number of output lines such that the address lines and the output lines form an array. A number of vertical pillars extend outwardly from a semiconductor substrate at intersections of output lines and address lines. Each pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer. A number of single crystalline ultra thin vertical floating gate transistors that are selectively disposed adjacent the number of vertical pillars.Type: ApplicationFiled: February 9, 2001Publication date: August 15, 2002Applicant: Micron Technology, Inc.Inventor: Leonard Forbes