Abstract: A package includes a device die, a molding material molding the device die therein, a through-via penetrating through the molding material, and an alignment mark penetrating through the molding material. A redistribution line is on a side of the molding material. The redistribution line is electrically coupled to the through-via.

Abstract: A photodetector based on PtSe2 and a silicon nanopillar array includes a PMMA light-transmitting protective layer, a graphene transparent top electrode, a silicon nanopillar array structure coated with few-layer PtSe2, and metal electrodes of the graphene transparent top electrode and the silicon nanopillar array structure. A method for preparing the photodetector includes steps of: preparing graphene with a CVD method; preparing a silicon nanopillar array structure through dry etching; coating few-layer PtSe2 on surfaces of the silicon nano-pillar array structure through laser interference enhanced induction CVD; preparing graphene transparent top electrode; and magnetron-sputtering metal electrodes. The photodetector prepared by the present invention has a detection range from visible light to near-infrared wavebands. The silicon nanopillar array structure enhances light absorption of the detector, so that the detector has high sensitivity, simple structure and strong practicability.

Abstract: Disclosed is a metal source/drain-based field effect transistor having a structure that replaces a portion of a semiconductor of a source/drain with a metal and a method of manufacturing the same. By replacing the source/drain region with the source/drain metal region, increase of the parasitic resistance of a conventional three-dimensional MOSFET of several tens of nanometers, lattice mismatch of the source/drain during selective epitaxial growth, and self-heating effect can be fundamentally solved. Further, since the metal is deposited after the partial etching of the source/drain region or the selective epitaxial growth is partially performed under the conventional CMOS process, the process can be performed without using any additional mask.

Abstract: An organic EL device including a first barrier film that contains primarily silicon nitride, a second barrier film that contains primarily silicon nitride, an organic EL element that is disposed between the first barrier film and the second barrier film, a first flexible substrate that is disposed opposite the organic EL element with the first barrier film interposed therebetween, a second flexible substrate that is disposed opposite the organic EL element with the second barrier film interposed therebetween, and a third barrier film that is disposed between the second barrier film and the organic EL element, and contains primarily silicon nitride.

Abstract: A memory device includes a memory cell, a selector layer and a first work function metal layer. The selector layer is disposed between a first electrode and a second electrode over the memory cell. The first work function metal layer is disposed between the selector layer and the first electrode.

Abstract: The present disclosure provides a display panel and a display device, comprising: a flexible base substrate comprising a first flexible substrate, a second flexible substrate, and metal signal lines located between the first flexible substrate and the second flexible substrate; a display unit disposed on the flexible base substrate; a touch unit disposed on a light-exiting side of the display unit and covering the display unit; and a processing chip connected to the flexible base substrate for receiving and feeding back signals from the display unit and/or the touch unit. The metal signal lines are electrically connected to the processing chip and the touch unit transmits a touch signal to the metal signal lines through a conductive adhesive. By transmitting the touch signal to the processing chip through the conductive adhesive, the touch unit and the display unit can share one processing chip.

Abstract: There is provided a semiconductor device including a first conductive layer formed on a substrate; a second conductive layer serving as a wiring layer and a barrier layer provided between the first conductive layer and the second conductive layer, wherein the barrier layer is made of a graphene film, and the second conductive layer includes a metal silicide compound, the metal silicide compound being provided so as to be in contact with the graphene film constituting the barrier layer.

Abstract: An object is to provide a display device which operates stably with use of a transistor having stable electric characteristics. In manufacture of a display device using transistors in which an oxide semiconductor layer is used for a channel formation region, a gate electrode is further provided over at least a transistor which is applied to a driver circuit. In manufacture of a transistor in which an oxide semiconductor layer is used for a channel formation region, the oxide semiconductor layer is subjected to heat treatment so as to be dehydrated or dehydrogenated; thus, impurities such as moisture existing in an interface between the oxide semiconductor layer and the gate insulating layer provided below and in contact with the oxide semiconductor layer and an interface between the oxide semiconductor layer and a protective insulating layer provided on and in contact with the oxide semiconductor layer can be reduced.

Abstract: An integrated circuit (IC) provides high performance and high functional density. A first back-end-of-line (BEOL) interconnect structure and a second BEOL interconnect structure are respectively under and over a semiconductor substrate. A first electronic device and a second electronic device are between the semiconductor substrate and respectively a bottom of the first BEOL interconnect structure and a top of the second BEOL interconnect structure. A through substrate via (TSV) extends through the semiconductor substrate, from the first BEOL interconnect structure to the second BEOL interconnect structure. A method for manufacturing the IC is also provided.

Abstract: An integrated circuit (IC) provides high performance and high functional density. A first back-end-of-line (BEOL) interconnect structure and a second BEOL interconnect structure are respectively under and over a semiconductor substrate. A first electronic device and a second electronic device are between the semiconductor substrate and respectively a bottom of the first BEOL interconnect structure and a top of the second BEOL interconnect structure. A through substrate via (TSV) extends through the semiconductor substrate, from the first BEOL interconnect structure to the second BEOL interconnect structure. A method for manufacturing the IC is also provided.

Abstract: Disclosed is a metal oxide thin film transistor and a manufacturing method thereof. By disposing a portion of the source and a portion of the drain in the same layer as the first insulating layer, the reflection of the ultraviolet light by the source, the drain and the first insulating layer can be blocked from entering the conductive channel. Therefore, a threshold voltage shift of the metal oxide thin film transistor under irradiation of ultraviolet light to the conductive channel can be prevented, and the threshold voltage stability and display quality are improved.

Abstract: A semiconductor device includes a substrate, a device isolation layer on the substrate, the device isolation layer defining a first active pattern, a pair of first source/drain patterns on the first active pattern, the pair of first source/drain patterns being spaced apart from each other in a first direction, and each of the pair of first source/drain patterns having a maximum first width in the first direction, a first channel pattern between the pair of first source/drain patterns, a gate electrode on the first channel pattern and extends in a second direction intersecting the first direction, and a first amorphous region in the first active pattern, the first amorphous region being below at least one of the pair of first source/drain patterns, and having a maximum second width in the first direction that is less than the maximum first width.

Abstract: A display device includes a substrate which includes a display area and a non-display area, a pixel unit which is provided in the display area and includes a plurality of pixel columns, and data lines which are respectively connected to the pixel columns and apply data signals to the pixel columns. The non-display area includes a fanout area, a bent area, and a pad area which are sequentially arranged. The respective data lines are disposed on different layers in the fanout area and the pad area. A resulting display device can reduce resistance deviation between data signals in a first data line and a second data line, thereby reducing vertical line defects.

Abstract: A memory device includes a bottom electrode, a resistance switching element, a capping layer, a top electrode, a first spacer, and a second spacer. The resistance switching element is over the bottom electrode. The capping layer is over the resistance switching element. The top electrode is over the capping layer. The first spacer extends along a sidewall of the resistance switching element. The second spacer extends along a sidewall of the first spacer and beyond a top of the first spacer, in which the second spacer is in contact with the capping layer.

Abstract: A method includes forming a first transistor including forming a first gate stack, epitaxially growing a first source/drain region on a side of the first gate stack, and performing a first implantation to implant the first source/drain region. The method further includes forming a second transistor including forming a second gate stack, forming a second gate spacer on a sidewall of the second gate stack, epitaxially growing a second source/drain region on a side of the second gate stack, and performing a second implantation to implant the second source/drain region. An inter-layer dielectric is formed to cover the first source/drain region and the second source/drain region. The first implantation is performed before the inter-layer dielectric is formed, and the second implantation is performed after the inter-layer dielectric is formed.

Abstract: In a method for manufacturing a semiconductor device, a first interlayer dielectric layer is formed over a substrate. First recesses are formed in the first interlayer dielectric layer. First metal wirings are formed in the first recesses. A first etch-resistance layer is formed in a surface of the first interlayer dielectric layer between the first metal wirings but not on upper surfaces of the first metal wirings. A first insulating layer is formed on the first etch-resistance layer and the upper surfaces of the first metal wirings.

Abstract: A method for fabricating a memory device includes forming a resistance switching element over a bottom electrode; forming a top electrode over the resistance switching element; forming a first spacer covering a sidewall of the resistance switching element; forming a second spacer surrounding the first spacer and exposing the top electrode; and forming a metallization pattern connected with the top electrode and the second spacer.

Abstract: Provided is a semiconductor device includes a gate stack, a first doped region, a second doped region, a first lightly doped region and a second lightly doped region. The gate stack is disposed on a substrate. The first doped region is located in the substrate at a first side of the gate stack. The second doped region is located in the substrate at a second side of the gate stack. The first lightly doped region is located in the substrate between the gate stack and the first doped region. The second lightly doped region is located in the substrate between the gate stack and the second doped region. A property of the first lightly doped region is different from a property of the second lightly doped region.

Abstract: A method for manufacturing a bonded SOI wafer, including depositing a polycrystalline silicon layer on a base wafer, forming an insulator film on a bond wafer, bonding the bond wafer and a polished surface of the silicon layer with the insulator film interposed, and thinning the bond wafer, wherein a silicon single crystal wafer having a resistivity of 100 ?·cm or more is the base wafer, the step of depositing the silicon layer includes a stage of forming an oxide film on the surface of the base wafer, and the silicon layer is deposited between 1050° C. and 1200° C. Accordingly, the method enables a polycrystalline silicon layer to be deposited while preventing the progress of single crystallization even through a heat treatment step in the SOI wafer manufacturing process or a heat treatment step in the device manufacturing process and can improve throughput in the polycrystalline silicon layer depositing step.

Abstract: A multilayer structure is provided, the multilayer structure comprising a semiconductor on insulator structure comprises an insulating layer that enhances the stability of the underlying charge trapping layer.

Abstract: Disclosed are an oxide thin film transistor (TFT), a method of manufacturing the same, a display panel including the oxide TFT, and a display device including the display panel, in which a crystalline oxide semiconductor is provided on a metal insulation layer including metal through a metal organic chemical vapor deposition (MOCVD) process. The oxide TFT includes a metal insulation layer including metal, a crystalline oxide semiconductor adjacent to the metal insulation layer, a gate including metal, a gate insulation layer between the crystalline oxide semiconductor and the gate, a first conductor in one end of the crystalline oxide semiconductor, and a second conductor in another end of the crystalline oxide semiconductor.

Abstract: A display device includes a substrate which includes a display area and a non-display area, a pixel unit which is provided in the display area and includes a plurality of pixel columns, and data lines which are respectively connected to the pixel columns and apply data signals to the pixel columns. The non-display area includes a fanout area, a bent area, and a pad area which are sequentially arranged. The respective data lines are disposed on different layers in the fanout area and the pad area. A resulting display device can reduce resistance deviation between data signals in a first data line and a second data line, thereby reducing vertical line defects.

Abstract: An object of the present invention to provide a highly reliable semiconductor device. Another object is to provide a manufacturing method of a highly reliable semiconductor device. Still another object is to provide a semiconductor device having low power consumption. Yet another object is to provide a manufacturing method of a semiconductor device having low power consumption. Furthermore, another object is to provide a semiconductor device which can be manufactured with high mass productivity. Another object is to provide a manufacturing method of a semiconductor device which can be manufactured with high mass productivity. An impurity remaining in an oxide semiconductor layer is removed so that the oxide semiconductor layer is purified to have an extremely high purity. Specifically, after adding a halogen element into the oxide semiconductor layer, heat treatment is performed to remove an impurity from the oxide semiconductor layer. The halogen element is preferably fluorine.

Abstract: An object of the present invention to provide a highly reliable semiconductor device. Another object is to provide a manufacturing method of a highly reliable semiconductor device. Still another object is to provide a semiconductor device having low power consumption. Yet another object is to provide a manufacturing method of a semiconductor device having low power consumption. Furthermore, another object is to provide a semiconductor device which can be manufactured with high mass productivity. Another object is to provide a manufacturing method of a semiconductor device which can be manufactured with high mass productivity. An impurity remaining in an oxide semiconductor layer is removed so that the oxide semiconductor layer is purified to have an extremely high purity. Specifically, after adding a halogen element into the oxide semiconductor layer, heat treatment is performed to remove an impurity from the oxide semiconductor layer. The halogen element is preferably fluorine.

Abstract: There is provided a Group III nitride semiconductor light-emitting device exhibiting improved crystallinity while suppressing abnormal growth of semiconductor layer due to pits and a production method therefor. In forming an n-side electrostatic breakdown preventing layer, pits are generated from the n-side electrostatic breakdown preventing layer. In forming an n-side superlattice layer, the layer is formed by alternately depositing a first InGaN layer and a GaN layer having an In composition ratio lower than that of the first InGaN layer, so that the In composition ratio and the total thickness of the first InGaN layers satisfy the following equation: 0<Y?180X+22, 0<X?0.1, X: In composition ratio of InGaN layers, and Y: Total thickness of InGaN layers (nm).

Abstract: The present disclosure provides a substrate structure for an electronic element, which includes a supporting carrier; a release layer having a first microstructure on a surface thereof, and the release layer having first adhesion to the supporting carrier; and a flexible substrate for disposing the supporting carrier and the release layer thereon, wherein the flexible substrate has second adhesion to the release layer, the first adhesion is greater than the second adhesion, and the surface of the flexible substrate in contact with the surface of the release layer has a second microstructure opposing to the first microstructure. The present disclosure further provides a method for fabricating the substrate structure.

Abstract: A display substrate and a fabrication method thereof and a display device. The display substrate includes: a plurality of pixels disposed on a lower substrate; and a pixel defining layer disposed between adjacent pixels of the plurality of pixels, the pixel defining layer contacting with an upper substrate of the plurality of pixels, the pixel defining layer configured for defining each pixel and supporting a gap between the upper substrate and the lower substrate.

Abstract: Provided is a novel semiconductor device. The semiconductor device comprises a first transistor and a second transistor. The first transistor comprises a first gate electrode; a first insulating film over the first gate electrode; a first oxide semiconductor film over the first insulating film; a first source electrode and a first drain electrode over the first oxide semiconductor film; a second insulating film over the first oxide semiconductor film, the first source electrode, and the first drain electrode; and a second gate electrode over the second insulating film.

Abstract: A system and method of ion milling performed in a plasma etch system including a plasma etch chamber, multiple process gas sources coupled to the plasma etch chamber, a radio frequency bias source and a controller. The plasma etch chamber including a substrate support. The substrate support being a non-pivoting and non-rotating substrate support. The substrate support capable of supporting a substrate to be processed on a top surface of the substrate support without use of a mechanical clamp device. The plasma etch chamber also including an upper electrode disposed opposite from the top surface of the substrate support. The radio frequency bias source is coupled to the substrate support. The controller is coupled to the plasma etch chamber, the multiple process gas sources and the radio frequency bias source. The controller including logic stored on computer readable media for performing an ion milling process in the plasma etch chamber.

Abstract: An organic light emitting display apparatus includes a base substrate, an active pattern disposed on the base substrate, a data line disposed on the base substrate, and a driving voltage line disposed on the base substrate. The active pattern includes a first transistor including a source area, a drain area and a channel. The active pattern also includes a first capacitor area and a second capacitor area. The data line extends in a first direction. The data line is overlapped with the first capacitor area. The driving voltage line extends in a second direction substantially perpendicular to the first direction. The driving voltage line is overlapped with the second capacitor area.

Abstract: An object is to provide a display device which operates stably with use of a transistor having stable electric characteristics. In manufacture of a display device using transistors in which an oxide semiconductor layer is used for a channel formation region, a gate electrode is further provided over at least a transistor which is applied to a driver circuit. In manufacture of a transistor in which an oxide semiconductor layer is used for a channel formation region, the oxide semiconductor layer is subjected to heat treatment so as to be dehydrated or dehydrogenated; thus, impurities such as moisture existing in an interface between the oxide semiconductor layer and the gate insulating layer provided below and in contact with the oxide semiconductor layer and an interface between the oxide semiconductor layer and a protective insulating layer provided on and in contact with the oxide semiconductor layer can be reduced.

Abstract: Some embodiments include an integrated structure having semiconductor material within a region between two parallel surfaces. The semiconductor material has grain boundaries parallel to the parallel surfaces. At least one circuit component utilizes a region of the semiconductor material in a gated device. The semiconductor material has little if any metal therein so that the gated device has Ion/Ioff characteristics similar to if the semiconductor material had no metal therein. Some embodiments include a method in which semiconductor material is provided between a pair of parallel surfaces, and in which the parallel surfaces and semiconductor material extend between a first end and a second end. Metal is formed adjacent the first end, and gettering material is formed adjacent the second end. Thermal processing induces crystallization of the semiconductor material and drives the metal along the semiconductor material and into the gettering material. The gettering material is then removed.

Abstract: A chip part is provided that includes a substrate 2 in which an element region 5 and an electrode region 16 are set, an insulating film (a first insulating film 9 and a second insulating film 3) which is formed on the substrate 2 and which selectively includes an internal concave/convex structure 18 in the electrode region 16 on a surface, a first connection electrode 3 and a second connection electrode 4 which include, at a bottom portion, an anchor portion 24 entering the concave portion 17 of the internal concave/convex structure 18 and which include an external concave/convex structure 6, 7 on a surface on the opposite side and a circuit element which is disposed in the element region 5 and which is electrically connected to the first connection electrode 3 and the second connection electrode 4.

Abstract: An electrical contact structure for an integrated circuit device is described. A first patterned dielectric layer comprising at least one contact hole, the contact hole including a bottom surface, and sidewalls extending from the bottom surface to a top surface is provided. A tungsten via is disposed within the at least one contact hole, the tungsten via having a bottom surface in contact with a lower layer of the device and a top surface. A selectively deposited metal layer is disposed on the top surface of the tungsten via to repair etch damage.

Abstract: A display device including: a first base substrate including a display area and a non-display area adjacent to the display area; a plurality of signal lines disposed in the display area; a plurality of pixels disposed in the display area and connected to the signal lines; and a driving circuit disposed in the non-display area and configured to provide driving signals to the signal lines. Each of the pixels includes a switching transistor connected to a corresponding signal line, and a display element connected to the switching transistor.

Abstract: The present disclosure provides an array substrate, its manufacturing method and a display device. The method includes forming a source electrode and a drain electrode of a thin film transistor, an active layer and a first transparent electrode in the array substrate by a masking step. The active layer and the first transparent electrode are formed by an identical metal oxide layer, and the source electrode and the drain electrode are arranged above the active layer. The first transparent electrode corresponds to a first semi-transparent region of a mask, a channel region of the thin film transistor corresponds to a second semi-transparent region of the mask, the source electrode and drain electrode of the thin film transistor correspond to a non-transparent region of the mask, and the first semi-transparent region of the mask is of transmittance greater than that of the second semi-transparent region of the mask.

Abstract: A device has a microelectromechanical system (MEMS) component with at least one surface and a coating disposed on at least a portion of the surface. The coating has a compound of the formula M(CnF2n+1Or), wherein M is a polar head group and wherein n?2r. The value of n may range from 2 to about 20, and the value of r may range from 1 to about 10. The value of n plus r may range from 3 to about 30, and a ratio of n:r may have a value of about 2:1 to about 20:1.

Abstract: Provided is a thin film transistor which is provided with an oxide semiconductor thin film layer and has a threshold voltage that does not change much due to light, a bias stress or the like, thereby exhibiting excellent stress stability. A thin film transistor of the present invention is provided with a gate electrode, an oxide semiconductor layer composed of a single layer which is used as a channel layer, an etch stopper layer to protect a surface of the oxide semiconductor layer, a source-drain electrode, and a gate insulator layer arranged between the gate electrode and the channel layer. The metal elements constituting the oxide semiconductor layer comprise In, Zn and Sn. The hydrogen concentration in the gate insulator layer in direct contact with the oxide semiconductor layer is controlled to 4 atomic % or lower.

Abstract: A semiconductor device may include: a first semiconductor layer having a first band gap; a second semiconductor layer including first and second regions separately disposed on an upper surface of the first semiconductor layer and having a second band gap wider than the first band gap; and a third semiconductor layer disposed between the first and second regions of the second semiconductor layer, extending up to at least a portion of the first semiconductor layer. The third semiconductor layer may have a channel region doped with an impurity.

Abstract: Various methods include: forming an optical waveguide in a bulk silicon layer, the optical waveguide including a set of shallow trench isolation (STI) regions overlying a silicon substrate region; ion implanting the silicon substrate to amorphize a portion of the silicon substrate; forming a set of trenches through the STI regions and into the underlying silicon substrate region; undercut etching the silicon substrate region under the STI regions through the set of trenches to form a set of cavities, wherein the at least partially amorphized portion of the silicon substrate etches at a rate less than an etch rate of the silicon substrate; and sealing the set of cavities.

Abstract: A photovoltaic device may be provided having a semiconductor substrate, an i-type amorphous layer or an i-type amorphous layer formed over a front surface or a back surface of the semiconductor substrate, and a p-type amorphous layer or an n-type amorphous layer formed over the i-type amorphous layer or the i-type amorphous layer. The i-type amorphous layer or the i-type amorphous layer has an oxygen concentration profile in which a concentration is reduced in a step-shape from a region near an interface with the semiconductor substrate and along a thickness direction.

Abstract: A photovoltaic device is provided having a semiconductor substrate, an i-type amorphous layer formed over a front surface of the semiconductor substrate, a p-type amorphous layer formed over the i-type amorphous layer, an i-type amorphous layer formed over a back surface of the semiconductor substrate, and an n-type amorphous layer formed over the i-type amorphous layer. The i-type amorphous layer and the i-type amorphous layer have oxygen concentration profiles in which concentrations are reduced in a step-shape from regions near interfaces with the semiconductor substrate and along a thickness direction, and an oxygen concentration in the step-shape portion of the i-type amorphous layer is higher than an oxygen concentration in the step-shape portion of the i-type amorphous layer.

Abstract: A flexible organic light-emitting display apparatus includes a flexible substrate, a barrier layer on the flexible substrate, a display portion on the barrier layer, an encapsulation layer covering the display portion, and a moisture absorption layer between the flexible substrate and the display portion.

Abstract: A semiconductor device in which a gettering layer is formed in a semiconductor substrate, and a method for forming the same are disclosed, resulting in increased reliability of the semiconductor substrate including the gettering layer. The semiconductor device includes a semiconductor substrate; a gettering layer formed of a first-type impurity and a second-type impurity in the semiconductor substrate so as to perform gettering of metal ion; and a deep-well region formed over the gettering layer in the semiconductor substrate.

Abstract: An object is to provide a display device which operates stably with use of a transistor having stable electric characteristics. In manufacture of a display device using transistors in which an oxide semiconductor layer is used for a channel formation region, a gate electrode is further provided over at least a transistor which is applied to a driver circuit. In manufacture of a transistor in which an oxide semiconductor layer is used for a channel formation region, the oxide semiconductor layer is subjected to heat treatment so as to be dehydrated or dehydrogenated; thus, impurities such as moisture existing in an interface between the oxide semiconductor layer and the gate insulating layer provided below and in contact with the oxide semiconductor layer and an interface between the oxide semiconductor layer and a protective insulating layer provided on and in contact with the oxide semiconductor layer can be reduced.

Abstract: An object is to provide a semiconductor device with high aperture ratio or a manufacturing method thereof. Another object is to provide semiconductor device with low power consumption or a manufacturing method thereof. A light-transmitting conductive layer which functions as a gate electrode, a gate insulating film formed over the light-transmitting conductive layer, a semiconductor layer formed over the light-transmitting conductive layer which functions as the gate electrode with the gate insulating film interposed therebetween, and a light-transmitting conductive layer which is electrically connected to the semiconductor layer and functions as source and drain electrodes are included.

Abstract: An organic light emitting diode (OLED) display device and a method of fabricating the same are provided. The OLED display device includes a substrate having a thin film transistor region and a capacitor region, a buffer layer disposed on the substrate, a gate insulating layer disposed on the substrate, a lower capacitor electrode disposed on the gate insulating layer in the capacitor region, an interlayer insulating layer disposed on the substrate, and an upper capacitor electrode disposed on the interlayer insulating layer and facing the lower capacitor electrode, wherein regions of each of the buffer layer, the gate insulating layer, the interlayer insulating layer, the lower capacitor electrode, and the upper capacitor electrode have surfaces in which protrusions having the same shape as grain boundaries of the semiconductor layer are formed. The resultant capacitor has an increased surface area, and therefore, an increased capacitance.

Abstract: An object of the present invention is to provide an electrooptical device having high operation performance and reliability, and a method of manufacturing the electrooptical device. Lov region 207 is disposed in n-channel TFT 302 that comprises a driver circuit, and a TFT structure which is resistant to hot carriers is realized. Loff regions 217 to 220 are disposed in n-channel TFT 304 that comprises a pixel section, and a TFT structure of low off current is realized. An input-output signal wiring 305 and gate wiring 306 are formed by laminating a first wiring and a second wiring having lower resistivity than the first wiring, and wiring resistivity is steeply reduced.

Abstract: Non-crystalline inorganic light emitting diode. In accordance with a first embodiment of the present invention, an article of manufacture includes a light emitting diode. The light emitting diode includes a non-crystalline inorganic light emission layer and first and second semiconducting non-crystalline inorganic charge transport layers surrounding the light emission layer. The light emission layer may be amorphous. The charge transport layers may be configured to inject one type of charge carrier and block the other type of charge carrier.

Abstract: To provide a miniaturized transistor having high electric characteristics. A conductive film to be a source electrode layer and a drain electrode layer is formed to cover an oxide semiconductor layer and a channel protection layer, and then a region of the conductive film, which overlaps with the oxide semiconductor layer and the channel protection layer, is removed by chemical mechanical polishing treatment. Precise processing can be performed accurately because an etching step using a resist mask is not performed in the step of removing part of the conductive film to be the source electrode layer and the drain electrode layer. With the channel protection layer, damage to the oxide semiconductor layer or a reduction in film thickness due to the chemical mechanical polishing treatment on the conductive film can be suppressed.