Abstract: A TFT 17 provided on a substrate 3 is provided. The TFT 17 includes a gate electrode 31, a gate insulating film 32, a semiconductor 33, a source electrode 34, a drain electrode 35, and a protection film 36. The semiconductor 33 includes a metal oxide semiconductor. The semiconductor 33 has a source portion 33a which is in contact with the source electrode 34, a drain portion 33b which is in contact with the drain electrode 35, and a channel portion 33c which is exposed through the source electrode 34 and the drain electrode 35. A conductive layer 37 having a relatively small electrical resistance is formed in each of the source portion 33a and the drain portion 33b. The conductive layer 37 is removed from the channel portion 33c.

Abstract: A sensor element array and method of fabricating the same are provided. The sensor element array is disposed on a substrate and includes a first patterned conductive layer, a channel layer, a first insulation layer, a second patterned conductive layer, a second insulation layer, and a third patterned conductive layer. The first patterned conductive layer includes a sensing line, a first power line, a source/drain pattern and a branch pattern. The channel layer includes a first channel and a second channel. Margins of the first insulation layer and the second patterned conductive layer are substantially overlapped. The second patterned conductive layer includes a selecting line, a gate pattern, and a gate connecting pattern. The second insulation layer has a first connecting opening for exposing the gate connecting pattern. The third patterned conductive layer includes a sensing electrode electrically connected to the gate connecting pattern.

Abstract: Provided is a bottom-gate transistor including an oxide semiconductor, in which electric-field concentration which might occur in the vicinity of an end portion of a drain electrode layer (and the vicinity of an end portion of a source electrode layer) when a high gate voltage is applied to a gate electrode layer is reduced and degradation of switching characteristics is suppressed, so that the reliability is improved. The cross-sectional shape of an insulating layer which overlaps over a channel formation region is a tapered shape. The thickness of the insulating layer which overlaps over the channel formation region is 0.3 ?m or less, preferably 5 nm or more and 0.1 ?m or less. The taper angle ? of a lower end portion of the cross-sectional shape of the insulating layer which overlaps over the channel formation region is 60° or smaller, preferably 45° or smaller, further preferably 30° or smaller.

Abstract: The present invention relates to a method for decreasing or increasing the band gap shift in the production of photovoltaic devices by means of coating a substrate with a formulation containing a silicon compound, e.g., in the production of a solar cell comprising a step in which a substrate is coated with a liquid-silane formulation, the invention being characterized in that the formulation also contains at least one germanium compound. The invention further relates to the method for producing such a photovoltaic device.

Abstract: Semiconductor devices are formed without zipper defects or channeling and through-implantation and with different silicide thicknesses in the gates and source/drain regions, Embodiments include forming a gate on a substrate, forming a nitride cap on the gate, forming a source/drain region in the substrate on each side of the gate, forming a wet cap fill layer on the source/drain region on each side of the gate, removing the nitride cap from the gate, and forming an amorphized layer in a top portion of the gate. Embodiments include forming the amorphized layer by implanting low energy ions.

Abstract: A device on a supporting substrate is provided including a semiconductor film, having two or more rectangular crystalline regions spaced from each other, wherein each of the two or more rectangular crystalline regions comprises one single crystal region. The device can further include two or more thin-film transistors, wherein each of the two or more thin-film transistors comprises one or more active-channel regions. Each of the one or more active-channel regions can comprise at least one of said two or more rectangular crystalline regions. The device can further include an integrated circuit which comprises of the two or more thin-film transistors.

Abstract: A method of forming a strained semiconductor material that in one embodiment includes forming a cleave layer in a host semiconductor substrate, and contacting a strain inducing material layer on a surface of a transfer portion of the host semiconductor substrate. A handle substrate is then contacted to an exposed surface of the stress inducing material layer. The transfer portion of the host semiconductor substrate may then be separated from the host semiconductor substrate along the cleave layer. A dielectric layer is formed directly on the transfer portion of the host semiconductor substrate. The handle substrate and the stress inducing material are then removed, wherein the transferred portion of the host semiconductor substrate provides a strained semiconductor layer that is in direct contact with a dielectric layer.

Abstract: A bio material receiving device includes a thin film transistor (“TFT”) including a drain electrode, and a nano well accommodating a bio material. The drain electrode includes the nano well. The TFT may be a bottom gate TFT or a top gate TFT. A nano well array may include a plurality of bio material receiving devices. In a method of operating the bio material receiving device, each of the bio material receiving devices may be individually selected in the nano well array. When the bio material is accommodated in the selected bio material receiving device, a voltage is applied so that another bio material is not accommodated.

Abstract: A semiconductor device includes a first conductive layer, a first insulating layer over the first conductive layer, first and second oxide semiconductor layers over the first insulating layer, a second conductive layer over the first oxide semiconductor layer, a third conductive layer over the second oxide semiconductor layer, a fourth conductive layer over the first oxide semiconductor layer and the second oxide semiconductor layer, a second insulating layer over the second conductive layer, the third conductive layer, and the fourth conductive layer, a fifth conductive layer electrically connected to the first conductive layer over the second insulating layer, and a sixth conductive layer over the second insulating layer. Each of the first and fifth conductive layers includes an area overlapping with the first oxide semiconductor layer. The sixth conductive layer includes an area overlapping with the second oxide semiconductor layer.

Abstract: This disclosure provides implementations of multi-gate transistors, structures, devices, apparatus, systems, and related processes. In one aspect, a device includes a thin-film semiconducting layer arranged over a substrate. A drain and source are coupled to the semiconducting layer. The device also includes first, second and third gates all arranged adjacent the semiconducting layer and configured to receive first, second, and third control signals, respectively. Dielectric layers insulate the gates from the semiconducting layer and from one another. In a first mode, the first, second, and third gates are configured such that charge is stored in a potential well in a region of the semiconducting layer adjacent the second gate. In a second mode, the first, second and third gate electrodes are configured such that the stored charge is transferred through the region of the semiconducting layer adjacent the third gate electrode and through the source to a load.

Abstract: An integrated circuit device includes a semiconductor substrate and a gate electrode on the semiconductor substrate. The gate electrode structure includes an insulating layer of a dielectric material on the semiconductor substrate, an oxygen barrier layer on the insulating layer, and a tungsten (W) metal layer on the oxygen barrier layer.

Abstract: Provided are a semiconductor device with less leakage current is reduced, a semiconductor device with both of high field effect mobility and low leakage current, an electronic appliance with low power consumption, and a manufacturing method of a semiconductor device in which leakage current can be reduced without an increase in the number of masks. The side surface of a semiconductor layer formed of a semiconductor film having high carrier mobility is not in contact with any of a source electrode and a drain electrode. Further, such a transistor structure is formed without an increase in the number of photomasks and can be applied to an electronic appliance.

Abstract: A through-substrate via structure including a substrate, a conductive layer, and a parasitic capacitance modulation layer is provided. The substrate has at least one opening. The opening is filled with the conductive layer. The parasitic capacitance modulation layer is disposed between the conductive layer and the substrate. The parasitic capacitance modulation layer is placed around the through-substrate via to reduce the depletion capacitance and further reduce the parasitic capacitance of the through-substrate via. Therefore, during transmission of signals with high frequency, the parasitic capacitance around the through-substrate via is rather small and thereby the operation speed of devices is increased.

Abstract: A p-type oxide which is amorphous and is represented by the following compositional formula: xAO.yCu2O where x denotes a proportion by mole of AO and y denotes a proportion by mole of Cu2O and x and y satisfy the following expressions: 0?x<100 and x+y=100, and A is any one of Mg, Ca, Sr and Ba, or a mixture containing at least one selected from the group consisting of Mg, Ca, Sr and Ba.

Abstract: A thin film transistor is provided, which includes a gate insulating layer covering a gate electrode, a microcrystalline semiconductor layer provided over the gate insulating layer, an amorphous semiconductor layer overlapping the microcrystalline semiconductor layer and the gate insulating layer, and a pair of impurity semiconductor layers which are provided over the amorphous semiconductor layer and to which an impurity element imparting one conductivity type is added to form a source region and a drain region. The gate insulating layer has a step adjacent to a portion in contact with an end portion of the microcrystalline semiconductor layer. A second thickness of the gate insulating layer in a portion outside the microcrystalline semiconductor layer is smaller than a first thickness thereof in a portion in contact with the microcrystalline semiconductor layer.

Abstract: Provided are a thin film transistor (TFT) including a selectively crystallized channel layer, and a method of manufacturing the TFT. The TFT includes a gate, the channel layer, a source, and a drain. The channel layer is formed of an oxide semiconductor, and at least a portion of the channel layer contacting the source and the drain is crystallized. In the method of manufacturing the TFT, the channel layer is formed of an oxide semiconductor, and a metal component is injected into the channel layer so as to crystallize at least a portion of the channel layer contacting the source and the drain. The metal component can be injected into the channel layer by depositing and heat-treating a metal layer or by ion-implantation.

Abstract: The present invention generally comprises a semiconductor film and the reactive sputtering process used to deposit the semiconductor film. The sputtering target may comprise pure zinc (i.e., 99.995 atomic percent or greater), which may be doped with aluminum (about 1 atomic percent to about 20 atomic percent) or other doping metals. The zinc target may be reactively sputtered by introducing nitrogen and oxygen to the chamber. The amount of nitrogen may be significantly greater than the amount of oxygen and argon gas. The amount of oxygen may be based upon a turning point of the film structure, the film transmittance, a DC voltage change, or the film conductivity based upon measurements obtained from deposition without the nitrogen containing gas. The reactive sputtering may occur at temperatures from about room temperature up to several hundred degrees Celsius. After deposition, the semiconductor film may be annealed to further improve the film mobility.

Abstract: A composite substrate having silicon substrate with excellent crystallinity and a method of manufacturing the composite substrate and an electronic component using the composite substrate are provided. A composite substrate (1) is configured to bond a support substrate (10) having electrical insulating property, and a silicon substrate (20) which is overlaid on the support substrate (10). The semiconductor substrate (20) of the composite substrate (1) includes a plurality of first regions (20x) in which a device function unit functioning as a semiconductor device is formed, and a second region (20y) located between these first regions (20x). In the semiconductor substrate (20) of the composite substrate (1), an amorphous form (22) containing silicon and a metal is present in the second region (20y).

Abstract: Disclosed is a wiring structure that attains excellent low-contact resistance even if eliminating a barrier metal layer that normally is disposed between a Cu alloy wiring film and a semiconductor layer, and wiring structure with excellent adhesion. The wiring structure is provided with a semiconductor layer, and a Cu alloy layer, on a substrate in this order from the substrate side. A laminated structure is included between the semiconductor layer, and the Cu alloy layer. The laminated structure is composed of a (N, C, F, O) layer which contains at least one element selected from among a group composed of nitrogen, carbon, fluorine, and oxygen, and a Cu—Si diffusion layer which includes Cu and Si, in this order from the substrate side. At least one element selected from among the group composed of nitrogen, carbon, fluorine, and oxygen that composes the (N, C, F, O) layer is bonded to Si in the semiconductor layer.

Abstract: Post programming resistance of a semiconductor fuse is enhanced by using an implantation to form an amorphous silicon layer and to break up an underlying high-?/metal gate. Embodiments include forming a shallow trench isolation (STI) region in a silicon substrate, forming a high-? dielectric layer on the STI region, forming a metal gate on the high-? dielectric layer, forming a polysilicon layer over the metal gate, performing an implantation to convert the polysilicon layer into an amorphous silicon layer, wherein the implantation breaks up the metal gate, and forming a silicide on the amorphous silicon layer. By breaking up the metal gate, electrical connection of the fuse contacts through the metal gate is eliminated.

Abstract: Provided is a method for manufacturing a semiconductor device. Also provided are: a semiconductor device which can be obtained by the method; and a dispersion that can be used in the method. A method for manufacturing a semiconductor device (500a) of the present invention comprises the steps (a)-(c) described below. (a) A dispersion which contains doped particles is applied to a specific part of a layer or a base. (b) An unsintered dopant implanted layer is obtained by drying the applied dispersion. (c) The specific part of the layer or the base is doped with a p-type or n-type dopant by irradiating the unsintered dopant implanted layer with light, and the unsintered dopant implanted layer is sintered, thereby obtaining a dopant implanted layer that is integrated with the layer or the base.

Abstract: Methods of forming and tuning a multilayer select device are provided, along with apparatus and systems which include them. As is broadly disclosed in the specification, one such method can include forming a first region having a first conductivity type; forming a second region having a second conductivity type and located adjacent to the first region; and forming a third region having the first conductivity type and located adjacent to the second region and, such that the first, second and third regions form a structure located between a first electrode and a second electrode, wherein each of the regions have a thickness configured to achieve a current density in a range from about 1×e4 amps/cm2 up to about 1×e8 amps/cm2 when a voltage in a selected voltage range is applied between the first electrode and the second electrode.

Abstract: An embodiment is a thin film transistor which includes a gate electrode layer, a gate insulating layer provided so as to cover the gate electrode layer; a first semiconductor layer entirely overlapped with the gate electrode layer; a second semiconductor layer provided over and in contact with the first semiconductor layer and having a lower carrier mobility than the first semiconductor layer; an impurity semiconductor layer provided in contact with the second semiconductor layer; a sidewall insulating layer provided so as to cover at least a sidewall of the first semiconductor layer; and a source and drain electrode layers provided in contact with at least the impurity semiconductor layer. The second semiconductor layer may consist of parts which are apart from each other over the first semiconductor layer.

Abstract: Disclosed is an organic light-emitting display device including a transparent substrate which includes a display portion and a pad portion formed in a region around the display portion, a first semiconductor layer formed on the display portion, a second semiconductor layer formed on the pad portion, and a transparent electrode formed on each of the first the second semiconductor layers, where the first and second semiconductor layers include the same material.

Abstract: A non-contact charge sensor includes a semiconductor detector having a first surface and an opposing second surface. The detector includes a high resistivity electrode layer on the first surface and a low resistivity electrode on the high resistivity electrode layer. A portion of the low resistivity first surface electrode is deleted to expose the high resistivity electrode layer in a portion of the area. A low resistivity electrode layer is disposed on the second surface of the semiconductor detector. A voltage applied between the first surface low resistivity electrode and the second surface low resistivity electrode causes a free charge to drift toward the first or second surface according to a polarity of the free charge and the voltage. A charge sensitive preamplifier coupled to a non-contact electrode disposed at a distance from the exposed high resistivity electrode layer outputs a signal in response to movement of free charge within the detector.

Abstract: Surfaces are provided comprising an array of partially embedded nano-fibers. Two such surfaces may contact each other such that the respective nano-fibers contact at orthogonal angles, resulting in ultra-low friction and ultra-low adhesion contact. Such configurations are useful in several NEMS or MEMS applications, as well as macro-sized applications. Alternatively, the surfaces may contact each other such that the respective nano-fibers are parallel. These configurations are useful in micro-stage or high-order three-dimensional self assembly applications.

Abstract: A schottky diode, a resistive memory device including the schottky diode and a method of manufacturing the same. The resistive memory device includes a semiconductor substrate including a word line, a schottky diode formed on the word line, and a storage layer formed on the schottky diode. The schottky diode includes a first semiconductor layer, a conductive layer formed on the first semiconductor layer and having a lower work function than the first semiconductor layer, and a second semiconductor layer formed on the to conductive layer.

Abstract: A high voltage semiconductor device includes a substrate, an insulating layer positioned on the substrate, and a silicon layer positioned on the insulating layer. The silicon layer further includes at least a first doped strip, two terminal doped regions formed respectively at two opposite ends of the silicon layer and electrically connected to the first doped strip, and a plurality of second doped strips. The first doped strip and the terminal doped regions include a first conductivity type, the second doped strips include a second conductivity type, and the first conductivity type and the second conductivity type are complementary. The first doped strip and the second doped strips are alternately arranged.

Abstract: A semiconductor component includes a thinned semiconductor substrate having a back side and a circuit side containing integrated circuits and associated circuitry. The semiconductor component also includes at least one lasered feature on the back side configured to provide selected electrical or physical characteristics for the substrate. The lasered feature can cover the entire back side or only selected areas of the back side, and can be configured to change electrical properties, mechanical properties or gettering properties of the substrate.

Abstract: The method for forming wavelike coherent nanostructures by irradiating a surface of a material by a homogeneous flow of ions is disclosed. The rate of coherency is increased by applying preliminary preprocessing steps.

Abstract: A thin film transistor including a substrate, a semiconductor layer, a patterned doped semiconductor layer, a source and a drain, a gate insulation layer, and a gate is provided. The semiconductor layer is disposed on the substrate. The patterned doped semiconductor layer is disposed on opposite sides of the semiconductor layer. The source and the drain are disposed on the patterned doped semiconductor layer and the opposite sides of the semiconductor layer, wherein a part of the semiconductor layer covered by the source and the drain has a first thickness, a part of the semiconductor layer disposed between the source and the drain and not covered by the source and the drain has a second thickness ranging from 200 ? to 800 ?. The gate insulation layer is disposed on the source, the drain and the semiconductor layer. The gate is disposed on the gate insulation layer.

Abstract: An array for an in-plane switching (IPS) mode liquid crystal display device includes a gate line formed on a substrate to extend in a first direction, a common line formed on the substrate to extend in the first direction, a data line formed to extend in a second direction, a thin film transistor formed at an intersection between the gate line and the data line, wherein the thin film transistor includes a gate line, a gate insulating layer, an active layer, a source electrode, and a drain electrode, a passivation film formed on the substrate including the thin film transistor, a pixel electrode formed on the passivation film located on a pixel region defined by the gate line and the data line, the pixel electrode being electrically connected to the drain electrode, a common electrode formed on the passivation film, and a common electrode connection line connected to the common electrode and the common line, wherein the common electrode connection line overlaps with the common line and the drain electrode.

Abstract: A dual resistance heater for a phase change material region is formed by depositing a resistive material. The heater material is then exposed to an implantation or plasma which increases the resistance of the surface of the heater material relative to the remainder of the heater material. As a result, the portion of the heater material approximate to the phase change material region is a highly effective heater because of its high resistance, but the bulk of the heater material is not as resistive and, thus, does not increase the voltage drop and the current usage of the device.

Abstract: To provide a highly reliable semiconductor device in which a transistor including an oxide semiconductor film has stable electric characteristics. The semiconductor device includes a gate electrode layer over a substrate, a gate insulating film over the gate electrode layer, an oxide semiconductor film over the gate insulating film, a drain electrode layer which is over the oxide semiconductor film so as to overlap with the gate electrode layer, and a source electrode layer provided so as to cover part of an outer edge portion of the oxide semiconductor film. An outer edge portion of the drain electrode layer is on an inner side than an outer edge portion of the gate electrode layer.

Abstract: An object is to improve reliability of a semiconductor device. A semiconductor device including a driver circuit portion and a display portion (also referred to as a pixel portion) over the same substrate is provided. The driver circuit portion and the display portion include thin film transistors in which a semiconductor layer includes an oxide semiconductor; a first wiring; and a second wiring. The thin film transistors each include a source electrode layer and a drain electrode layer which each have a shape whose end portions are located on an inner side than end portions of the semiconductor layer. In the thin film transistor in the driver circuit portion, the semiconductor layer is provided between a gate electrode layer and a conductive layer. The first wiring and the second wiring are electrically connected in an opening provided in a gate insulating layer through an oxide conductive layer.

Abstract: A method of manufacturing a semiconductor wafer of the present invention includes the steps of: obtaining a composite base by forming a base surface flattening layer having a surface RMS roughness of not more than 1.0 nm on a base; obtaining a composite substrate by attaching a semiconductor crystal layer to a side of the composite base where the base surface flattening layer is located; growing at least one semiconductor layer on the semiconductor crystal layer of the composite substrate; and obtaining the semiconductor wafer including the semiconductor crystal layer and the semiconductor layer by removing the base surface flattening layer by wet etching and thereby separating the semiconductor crystal layer from the base.

Abstract: An integrated circuit includes a first trench disposed in a semiconductor material, wherein a width of the first trench in an upper portion of the first trench adjacent to a surface of the semiconductor material is smaller than a width of the first trench in a lower portion of the first trench, the lower portion being disposed within the semiconductor material, each width being measured in a plane parallel to a surface of the semiconductor material, each width denoting a distance between inner faces of remaining semiconductor material portions or between outer faces of a filling disposed in the first trench, or between an inner face of a remaining semiconductor material portion and an outer face of a filling disposed in the first trench.

Abstract: One object is to provide a deposition technique for forming an oxide semiconductor film. By forming an oxide semiconductor film using a sputtering target including a sintered body of a metal oxide whose concentration of hydrogen contained is low, for example, lower than 1×1016 atoms/cm3, the oxide semiconductor film contains a small amount of impurities such as a compound containing hydrogen typified by H2O or a hydrogen atom. In addition, this oxide semiconductor film is used as an active layer of a transistor.

Abstract: A method of manufacturing a phase change memory (PCM) includes forming a pinch plate layer transversely to a PCM layer that is insulated from the pinch plate layer by a dielectric layer. Biasing the pinch plate layer causes a depletion region to form in the PCM layer. During a read of the PCM in a reset or partial reset state the depletion region increases the resistance of the PCM layer significantly.

Abstract: A silicon carbide substrate includes: an n type drift layer having a first surface and a second surface opposite to each other; a p type body region provided in the first surface of the n type drift layer; and an n type emitter region provided on the p type body region and separated from the n type drift layer by the p type body region. A gate insulating film is provided on the p type body region so as to connect the n type drift layer and the n type emitter region to each other. A p type Si collector layer is directly provided on the silicon carbide substrate to face the second surface of the n type drift layer.

Abstract: A device is provided. The device includes a first electrode, an organic layer disposed over the first electrode and a second electrode disposed over the organic layer. The second electrode further includes a first conductive layer having an extinction coefficient and an index of refraction, a first separation layer disposed over the first conductive layer, and a second conductive layer disposed over the first separation layer. The first separation layer has an extinction coefficient that is at least 10% different from the extinction coefficient of the first conductive layer at 500 nm, or an index of refraction that is at least 10% different from the index of refraction of the first conductive layer at 500 nm. The device also includes a barrier layer disposed over the second conductive layer.

Abstract: Crack formation and propagation in a silicon substrate may be reduced by forming a crack reducing portion. The silicon substrate includes a silicon main portion and a silicon edge portion formed around the silicon main portion. The crack reducing portion is formed on the silicon edge portion of the silicon substrate such that the directions of crystal faces in the crack reducing portion are randomly oriented.

Abstract: Provided are a crystallization apparatus and method, which prevent cracks from being generated, a method of manufacturing a thin film transistor (TFT), and a method of manufacturing an organic light emitting display apparatus. The crystallization apparatus includes a chamber for receiving a substrate, a first flash lamp and a second flash lamp, which are disposed facing each other within the chamber, wherein amorphous silicon layers are disposed on a first surface of the substrate facing the first flash lamp and a second surface of the substrate facing the second flash lamp, respectively.

Abstract: High yield substrate assembly. In accordance with a first method embodiment, a plurality of piggyback substrates are attached to a carrier substrate. The edges of the plurality of the piggyback substrates are bonded to one another. The plurality of piggyback substrates are removed from the carrier substrate to form a substrate assembly. The substrate assembly is processed to produce a plurality of integrated circuit devices on the substrate assembly. The processing may use manufacturing equipment designed to process wafers larger than individual instances of the plurality of piggyback substrates.

Abstract: Provided are a sensor array substrate and a method of fabricating the same. The sensor array substrate includes: a substrate in which a switching element region and a sensor region that senses light are defined; a first semiconductor layer which is formed in the sensor region; a first gate electrode which is formed on the first semiconductor layer and overlaps the first semiconductor layer; a second gate electrode which is formed in the switching element region; a second semiconductor layer which is formed on the second gate electrode and overlaps the second gate electrode; and a light-blocking pattern which is formed on the second semiconductor layer and overlaps the second semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer are disposed on different layers, and the second gate electrode and the light-blocking pattern are electrically connected to each other.

Abstract: A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate, forming an epitaxial layer on a top surface of the semiconductor substrate and having a predetermined thickness, and forming a plurality of trenches in the epitaxial layer. The trenches are formed in the epitaxial layer and have a predetermined depth, top width, and bottom width. Further, the method includes performing a first trench filling process to form a semiconductor layer inside of the trenches using a mixture gas containing at least silicon source gas and halogenoid gas, stopping the first trench filling process when at least one trench is not completely filled, and performing a second trench filling process, different from the first trench filling process, to fill the plurality of trenches completely.

Abstract: The invention relates to a process for producing an oxygen-containing surface or interface of a silicon layer, which is arranged on a substrate, especially in the production of photovoltaic units.

Abstract: To provide a miniaturized transistor having high electric characteristics. A conductive film to be a source electrode layer and a drain electrode layer is formed to cover an oxide semiconductor layer and a channel protection layer, and then a region of the conductive film, which overlaps with the oxide semiconductor layer and the channel protection layer, is removed by chemical mechanical polishing treatment. Precise processing can be performed accurately because an etching step using a resist mask is not performed in the step of removing part of the conductive film to be the source electrode layer and the drain electrode layer. With the channel protection layer, damage to the oxide semiconductor layer or a reduction in film thickness due to the chemical mechanical polishing treatment on the conductive film can be suppressed.

Abstract: An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit included in an LSI, a CPU, or a memory is manufactured using the transistor which is formed using an oxide semiconductor which is an intrinsic or substantially intrinsic semiconductor obtained by removal of impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than a silicon semiconductor, and is formed over a semiconductor substrate. With the transistor which is formed over the semiconductor substrate and includes the highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device whose power consumption due to leakage current is low can be realized.

Abstract: A semiconductor device may include a composite represented by Formula 1 below as an active layer. x(Ga2O3).y(In2O3).z(ZnO)??Formula 1 wherein, about 0.75?x/z?about 3.15, and about 0.55?y/z?about 1.70. Switching characteristics of displays and driving characteristics of driving transistors may be improved by adjusting the amounts of a gallium (Ga) oxide and an indium (In) oxide mixed with a zinc (Zn) oxide and improving optical sensitivity.