With Bipolar Transistor Structure Patents (Class 257/526)
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Patent number: 8501572Abstract: The present disclosure provides a bipolar junction transistor (BJT) device and methods for manufacturing the BJT device. In an embodiment, the BJT device includes: a semiconductor substrate having a collector region, and a material layer disposed over the semiconductor layer. The material layer has a trench therein that exposes a portion of the collector region. A base structure, spacers, and emitter structure are disposed within the trench of the material layer. Each spacer has a top width and a bottom width, the top width being substantially equal to the bottom width.Type: GrantFiled: September 2, 2010Date of Patent: August 6, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Tsung Kuo, Shih-Chang Liu, Chia-Shiung Tsai
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Publication number: 20130175589Abstract: A semiconductor substrate has at least two active regions, each having at least one active device that includes a gate electrode layer, and a shallow trench isolation (STI) region between the active regions. A decoupling capacitor comprises first and second dummy conductive patterns formed in the same gate electrode layer over the STI region. The first and second dummy conductive regions are unconnected to any of the at least one active device. The first dummy conductive pattern is connected to a source of a first potential. The second dummy conductive pattern is connected to a source of a second potential. A dielectric material is provided between the first and second dummy conductive patterns.Type: ApplicationFiled: January 5, 2012Publication date: July 11, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventor: Chung-Hui CHEN
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Publication number: 20130134550Abstract: A semiconductor device according to the present invention includes a p-type semiconductor substrate, a first n-type collector diffusion layer formed in the p-type semiconductor substrate, a deep trench formed in the p-type semiconductor substrate so as to surround the first n-type collector diffusion layer, a p-type channel stopper layer formed beneath the deep trench, and an n-type diffusion layer formed between a sidewall of the deep trench and the first n-type collector diffusion layer.Type: ApplicationFiled: December 21, 2012Publication date: May 30, 2013Applicant: PANASONIC CORPORATIONInventor: PANASONIC CORPORATION
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Publication number: 20130099351Abstract: A bipolar transistor is disclosed, which includes a collector region, a base region, an emitter region and field plates. Each field plate is present in a structure of a flat sidewall covering one side face of the active region so that it also covers the collector region from one side. The field plate has its surface parallel to the side face of the active region and is isolated from the side face of the active region by a pad oxide layer. The field plate has its top lower than the surface of the active region. The bipolar transistor is capable of improving the breakdown voltage of the device without increasing the collector resistance or deteriorating the frequency characteristic. A method of manufacturing bipolar transistor is also disclosed.Type: ApplicationFiled: October 23, 2012Publication date: April 25, 2013Applicant: SHANGHAI HUA HONG NEC ELECTRONICS CO., LTDInventor: SHANGHAI HUA HONG NEC ELECTRONICS CO., LTD
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Patent number: 8420475Abstract: This invention published a parasitic vertical PNP bipolar transistor in BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) process; the bipolar transistor comprises a collector, a base and an emitter. Collector is formed by active region with p-type ion implanting layer. It connects a p-type buried layer which formed in the bottom region of STI (Shallow Trench Isolation). The collector terminal connection is through the p-type buried layer and the adjacent active region. The base is formed by active region with n type ion implanting which is on the collector. Its connection is through the original p-type epitaxy layer after converting to n-type. The emitter is formed by the p-type epitaxy layer on the base region with heavy p-type doped. This invention also comprises the fabrication method of this parasitic vertical PNP bipolar in BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) process.Type: GrantFiled: December 22, 2010Date of Patent: April 16, 2013Assignee: Shanghai Hua Hong Nec Electronics Company, LimitedInventors: Tzuyin Chiu, TungYuan Chu, Wensheng Qian, YungChieh Fan, Donghua Liu, Jun Hu
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Patent number: 8421185Abstract: A parasitic vertical PNP device in one type of BiCMOS process with shallow trench isolation (STI) comprises a collector formed by a p type impurity ion implantation layer inside active area, the bottom of collector connects to a p type buried layer, the p type pseudo buried layer is formed in bottom of shallow trench at both sides of collector active region through ion implantation, deep contacts through field oxide to connect pseudo buried layers and to pick up the collector; a base, formed by n type impurity ion implantation layer which sits on top of above stated collector; an emitter, a p type epitaxy layer lies above base and is connected out directly by a metal contact. Part of the p type epitaxy layer is converted into n type, which serves as connection path of base. Present invented PNP can be used as output device of BiCMOS high frequency circuit. It has a small device area and conduction resistance.Type: GrantFiled: December 25, 2010Date of Patent: April 16, 2013Assignee: Shanghai Hua Hong NEC Electronics Company, LimitedInventors: Tzuyin Chiu, TungYuan Chu, Wensheng Qian, YungChieh Fan, Donghua Liu, Jun Hu
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Patent number: 8415663Abstract: System and method for test structure on a wafer. According to an embodiment, the present invention provides a test structure for testing a chip. For example, the test structure and the chip are manufactured on a same substrate material and the testing being conducted is in a temperature-controlled environment. The test structure includes a top structure positioned above the chip. For example, the top structure can be characterized by a first surface area. The top structure includes a first metal material occupying less than 60% of the surface area. The test structure also includes a bottom structure positioned below the chip. For example, the bottom structure can be characterized by a second surface area. The second surface area is substantially equal to the first surface area. The bottom structure includes a first silicon material. The first silicon material occupies substantially all of the second surface area.Type: GrantFiled: November 11, 2009Date of Patent: April 9, 2013Assignee: Semiconductor Manufacturing International (Shanghai)Inventors: Wang Jian Ping, Chin Chang Liao, Waisum Wong
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Patent number: 8405186Abstract: Disclosed are embodiments of an improved transistor structure (e.g., a bipolar transistor (BT) structure or heterojunction bipolar transistor (HBT) structure) and a method of forming the transistor structure. The structure embodiments can incorporate a dielectric layer sandwiched between an intrinsic base layer and a raised extrinsic base layer to reduce collector-base capacitance Ccb, a sidewall-defined conductive strap for an intrinsic base layer to extrinsic base layer link-up region to reduce base resistance Rb and a dielectric spacer between the extrinsic base layer and an emitter layer to reduce base-emitter Cbe capacitance. The method embodiments allow for self-aligning of the emitter to base regions and further allow the geometries of different features (e.g., the thickness of the dielectric layer, the width of the conductive strap, the width of the dielectric spacer and the width of the emitter layer) to be selectively adjusted in order to optimize transistor performance.Type: GrantFiled: June 17, 2010Date of Patent: March 26, 2013Assignee: International Business Machines CorporationInventors: Renata Camillo-Castillo, Mattias E. Dahlstrom, Peter B. Gray, David L. Harame, Russell T. Herrin, Alvin J. Joseph, Andreas D. Stricker
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Patent number: 8384154Abstract: A bidirectional power transistor formed horizontally in a semiconductor layer disposed on a heavily-doped semiconductor wafer with an interposed insulating layer, the wafer being capable of being biased to a reference voltage, the product of the average dopant concentration and of the thickness of the semiconductor layer ranging between 5·1011 cm?2 and 5·1012 cm?2.Type: GrantFiled: November 22, 2010Date of Patent: February 26, 2013Assignees: STMicroelectronics (Tours) SAS, Universite Francois Rabelais UFR Sciences et TechniquesInventors: Jean-Baptiste Quoirin, Luong Viêt Phung, Nathalie Batut
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Publication number: 20120313216Abstract: An example embodiment is a complementary transistor inverter circuit. The circuit includes a semiconductor-on-insulator (SOI) substrate, a lateral PNP bipolar transistor fabricated on the SOI substrate, and a lateral NPN bipolar transistor fabricated on the SOI substrate. The lateral PNP bipolar transistor includes a PNP base, a PNP emitter, and a PNP collector. The lateral NPN bipolar transistor includes a NPN base, a NPN emitter, and a NPN collector. The PNP base, the PNP emitter, the PNP collector, the NPN base, the NPN emitter, and the NPN collector abut the buried insulator of the SOI substrate.Type: ApplicationFiled: June 12, 2011Publication date: December 13, 2012Applicant: International Business Machines CorporationInventors: Jin Cai, Robert H. Dennard, Wilfried E. Haensch, Tak H. Ning
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Patent number: 8264036Abstract: A semiconductor device according to the invention includes n-type semiconductor substrate 1; trenches 15 formed in the surface portion of semiconductor substrate 1; a protruding semiconductor region between trenches 15; p-type base layer 2 in the protruding semiconductor region, p-type base layer 2 being positioned as deep as or shallower than trench 15; an n++-type emitter region or a source region in the surface portion of p-type base layer 2; gate insulator film 4a on the first side wall of the protruding semiconductor region; and gate electrode 6 on gate insulator film 4a. Trench 15 is from 0.5 ?m to 3.0 ?m deep and the short side of trench 15 is 1.0 ?m or longer. The short side of the protruding semiconductor region is from 0.5 ?m to 3.0 ?m long. Gate electrode 6 contains electrically conductive polycrystalline silicon as its main component. Gate electrode 6 is from 0.2 ?m to 1.0 ?m thick.Type: GrantFiled: November 12, 2009Date of Patent: September 11, 2012Assignee: Fuji Electric Co., Ltd.Inventor: Manabu Takei
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Patent number: 8188568Abstract: A semiconductor circuit includes: a first diffusion layer formed on a substrate; a second diffusion layer formed in an upper part of the first diffusion layer; a third diffusion layer formed in an upper part of the second diffusion layer; a fourth diffusion layer formed in the upper part of the first diffusion layer; and a fifth diffusion formed below the third diffusion layer. A sum of a shortest distance from the third diffusion layer to the fifth diffusion layer and a shortest distance from the fifth diffusion layer or the lower end of the first diffusion layer to the fourth diffusion layer is smaller than a shortest distance from the third diffusion layer to the fourth diffusion layer. The substrate, the second and the fifth diffusion layer are a first conductivity type and the others are a second conductivity type.Type: GrantFiled: February 7, 2011Date of Patent: May 29, 2012Assignee: Panasonic CorporationInventor: Manabu Imahashi
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Publication number: 20120049319Abstract: A parasitic PIN device in a BiCMOS process is disclosed. The device is formed on a silicon substrate, in which an active region is isolated by shallow trenches. The device includes: an N-type region, consisting of N-type pseudo buried layers respectively formed at the bottom of shallow trench isolation oxide layers and extending into the active region; an I-type region, consisting of an N-type collector implantation region formed in the active region and contacting with the N-type region; a P-type region, consisting of a P-doped intrinsic base epitaxial layer on a surface of the active region and contacting with the I-type region. The device of the present invention has a low insertion loss and a high isolation. A manufacturing method of parasitic PIN device in compatible with existing BiCMOS process is also disclosed.Type: ApplicationFiled: August 25, 2011Publication date: March 1, 2012Inventors: Wensheng Qian, Ju Hu
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Publication number: 20110309471Abstract: Disclosed are embodiments of an improved transistor structure (e.g., a bipolar transistor (BT) structure or heterojunction bipolar transistor (HBT) structure) and a method of forming the transistor structure. The structure embodiments can incorporate a dielectric layer sandwiched between an intrinsic base layer and a raised extrinsic base layer to reduce collector-base capacitance Ccb, a sidewall-defined conductive strap for an intrinsic base layer to extrinsic base layer link-up region to reduce base resistance Rb and a dielectric spacer between the extrinsic base layer and an emitter layer to reduce base-emitter Cbe capacitance. The method embodiments allow for self-aligning of the emitter to base regions and further allow the geometries of different features (e.g., the thickness of the dielectric layer, the width of the conductive strap, the width of the dielectric spacer and the width of the emitter layer) to be selectively adjusted in order to optimize transistor performance.Type: ApplicationFiled: June 17, 2010Publication date: December 22, 2011Applicant: International Business Machines CorporationInventors: Renata Camillo-Castillo, Mattias E. Dahlstrom, Peter B. Gray, David L. Harame, Russell T. Herrin, Alvin J. Joseph, Andreas D. Stricker
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Publication number: 20110254120Abstract: A semiconductor integrated circuit includes: a substrate of a first conductivity type; a first diffusion layer of a second conductivity type formed on the substrate; a second diffusion layer of the first conductivity type formed in an upper part of the first diffusion layer; a third diffusion layer of the second conductivity type formed in an upper part of the second diffusion layer; a fourth diffusion layer of the second conductivity type formed in the upper part of the first diffusion layer; and a fifth diffusion layer of the first conductivity type formed below the third diffusion layer. A sum of a shortest distance from the third diffusion layer to the fifth diffusion layer and a shortest distance from the fifth diffusion layer or the lower end of the first diffusion layer to the fourth diffusion layer is smaller than a shortest distance from the third diffusion layer to the fourth diffusion layer.Type: ApplicationFiled: February 7, 2011Publication date: October 20, 2011Inventor: Manabu IMAHASHI
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Publication number: 20110156151Abstract: This invention disclosed a kind of electrode pick up structure in shallow trench isolation process. The active region is isolated by shallow trench. A pseudo-buried layer under the bottom of shallow trench is formed. The pseudo-buried layer extends into active region and connects to doping region one which needs to be picked up by an electrode. The pick up is realized by deep trench contacts which etch through STI and get in touch with pseudo buried layer. This invention can reduce the device size, pick up electrode resistance, collector parasitic capacitance, and increase device cut off frequency.Type: ApplicationFiled: December 28, 2010Publication date: June 30, 2011Inventors: Tzuyin CHIU, TungYuan Chu, YungChieh Fan, Wensheng Qian, Jiong Xu, Fan Chen, Haifang Zhang
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Publication number: 20110156202Abstract: A parasitic vertical PNP device in one type of BiCMOS process with shallow trench isolation (STI) comprises a collector formed by a p type impurity ion implantation layer inside active area, the bottom of collector connects to a p type buried layer, the p type pseudo buried layer is formed in bottom of shallow trench at both sides of collector active region through ion implantation, deep contacts through field oxide to connect pseudo buried layers and to pick up the collector; a base, formed by n type impurity ion implantation layer which sits on top of above stated collector; an emitter, a p type epitaxy layer lies above base and is connected out directly by a metal contact. Part of the p type epitaxy layer is converted into n type, which serves as connection path of base. Present invented PNP can be used as output device of BiCMOS high frequency circuit. It has a small device area and conduction resistance.Type: ApplicationFiled: December 25, 2010Publication date: June 30, 2011Inventors: Tzuyin CHIU, TungYuan Chu, Wensheng Qian, YungChieh Fan, Donghua Liu, Jun Hu
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Patent number: 7968914Abstract: A mechanical construction of an electrical module includes two or more electrical components (102-105). Each of the electrical components has a contact surface (106-109) that is capable of forming a galvanic contact with an external electrical conductor. The electrical module includes a holder element (101) that includes flexible material arranged to flexibly support the electrical components with respect to each other in such a way that the contact surfaces of the electrical components are capable of aligning with external surfaces independently of each other.Type: GrantFiled: February 5, 2009Date of Patent: June 28, 2011Assignee: ABB OyInventors: Matti Laitinen, Markku Talja, Jukka Sikanen, Christoph Haederli
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Publication number: 20110140233Abstract: A parasitic vertical PNP bipolar transistor in BiCMOS process comprises a collector, a base and an emitter. The collector is formed by active region with p-type ion implanting layer (P type well in NMOS). It connects a P-type conductive region, which formed in the bottom region of shallow trench isolation (STI). The collector terminal connection is through the P-type buried layer and the adjacent active region. The base is formed by N type ion implanting layer above the collector which shares a N-type lightly doped drain (NLDD) implanting of NMOS. Its connection is through the N-type poly on the base region. The emitter is formed by the P-type epitaxy layer on the base region with heavy p-type doped, and connected by the extrinsic base region of NPN bipolar transistor device. This invention also includes the fabrication method of this parasitic vertical PNP bipolar transistor in BiCMOS process.Type: ApplicationFiled: December 8, 2010Publication date: June 16, 2011Inventors: Wensheng QIAN, Jun Hu, Donghua Liu
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Publication number: 20110101486Abstract: A bipolar transistor comprising an emitter region, a base region and a collector region, and a guard region spaced from and surrounding the base. The guard region can be formed in the same steps that form the base, and can serve to spread out the depletion layer in operation.Type: ApplicationFiled: November 2, 2009Publication date: May 5, 2011Applicant: Analog Devices, Inc.Inventors: William Allan Lane, Andrew David Bain, Derek Frederick Bowers, Paul Malachy Daly, Anne Maria Deignan, Michael Thomas Dunbar, Patrick Martin McGuiness, Bernard Patrick Stenson
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Patent number: 7911024Abstract: The present invention provides a “collector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped collector. Instead, the inventive vertical SOI BJT uses a back gate-induced, minority carrier inversion layer as the intrinsic collector when it operates. In accordance with the present invention, the SOI substrate is biased such that an inversion layer is formed at the bottom of the base region serving as the collector. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS.Type: GrantFiled: February 17, 2010Date of Patent: March 22, 2011Assignee: International Business Machines CorporationInventors: Herbert L. Ho, Mahender Kumar, Qiqing Ouyang, Paul A. Papworth, Christopher D. Sheraw, Michael D. Steigerwalt
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Patent number: 7906403Abstract: Consistent with an example embodiment, there is a bipolar transistor with a reduced collector series resistance integrated in a trench of a standard CMOS shallow trench isolation region. The bipolar transistor includes a collector region manufactured in one fabrication step, therefore having a shorter conductive path with a reduced collector series resistance, improving the high frequency performance of the bipolar transistor. The bipolar transistor further includes a base region with a first part on a selected portion of the collector region (6, 34), which is on the bottom of the trench, and an emitter region on a selected portion of the first part of the base region. A base contact electrically contacts the base region on a second part of the base region, which is on an insulating region. The collector region is electrically contacted on top of a protrusion with a collector contact.Type: GrantFiled: January 12, 2006Date of Patent: March 15, 2011Assignee: NXP B.V.Inventors: Johannes JTM Donkers, Wibo D. Van Noort, Philippe Meunier-Beillard, Sebastien Nuttinck, Erwin Hujzen, Francois Neuilly
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Patent number: 7906829Abstract: A semiconductor device includes: a semiconductor substrate having a first surface and a second surface; a first insulation separation region disposed on the first surface of the semiconductor substrate; a second insulation separation region surrounded with the first insulation separation region and electrically isolated from the first insulation separation region; a semiconductor element disposed in the second insulation separation region; and an electrode connecting to the first insulation separation region for energizing and generating heat in the first insulation separation region. The first insulation separation region functions as a heater so that the semiconductor element in the second insulation separation region is locally heated.Type: GrantFiled: June 6, 2006Date of Patent: March 15, 2011Assignee: Denso CorporationInventor: Akira Tai
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Publication number: 20110057289Abstract: An integrated circuit containing a bipolar transistor including an emitter diffused region with a peak doping density higher than 1·1020 atoms/cm3, and an emitter-base junction less than 40 nanometers deep in a base layer. A process of forming the bipolar transistor, which includes forming an emitter dopant atom layer between a base layer and an emitter layer, followed by a flash or laser anneal step to diffuse dopant atoms from the emitter dopant atom layer into the base layer.Type: ApplicationFiled: March 5, 2010Publication date: March 10, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Rick L. Wise, Hiroshi Yasuda
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Patent number: 7855421Abstract: An embedded memory required for a high performance, multifunction SOC, and a method of fabricating the same are provided. The memory includes a bipolar transistor, a phase-change memory device and a MOS transistor, adjacent and electrically connected, on a substrate. The bipolar transistor includes a base composed of SiGe disposed on a collector. The phase-change memory device has a phase-change material layer which is changed from an amorphous state to a crystalline state by a current, and a heating layer composed of SiGe that contacts the lower surface of the phase-change material layer.Type: GrantFiled: December 4, 2006Date of Patent: December 21, 2010Assignee: Electronics and Telecommunications Research InstituteInventors: Seung-Yun Lee, Sangouk Ryu, Sung Min Yoon, Young Sam Park, Kyu-Jeong Choi, Nam-Yeal Lee, Byoung-Gon Yu
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Publication number: 20100207683Abstract: The present invention provides a “collector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped collector. Instead, the inventive vertical SOI BJT uses a back gate-induced, minority carrier inversion layer as the intrinsic collector when it operates. In accordance with the present invention, the SOI substrate is biased such that an inversion layer is formed at the bottom of the base region serving as the collector. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS.Type: ApplicationFiled: February 17, 2010Publication date: August 19, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Herbert L. Ho, Mahender Kumar, Qiqing Ouyang, Paul A. Papworth, Christopher D. Sheraw, Michael D. Steigerwalt
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Patent number: 7763518Abstract: The present invention provides a “collector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped collector. Instead, the inventive vertical SOI BJT uses a back gate-induced, minority carrier inversion layer as the intrinsic collector when it operates. In accordance with the present invention, the SOI substrate is biased such that an inversion layer is formed at the bottom of the base region serving as the collector. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS.Type: GrantFiled: April 8, 2008Date of Patent: July 27, 2010Assignee: International Business Machines CorporationInventors: Herbert L. Ho, Mahender Kumar, Qiqing Ouyang, Paul A. Papworth, Christopher D. Sheraw, Michael D. Steigerwalt
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Patent number: 7759759Abstract: An integrated circuit includes a high voltage NPN bipolar transistor and a low voltage device. The NPN bipolar transistor includes a lightly doped p-well as the base region of the transistor while the low voltage devices are built using standard, more heavily doped p-wells. By using a process including a lightly doped p-well and a standard p-well, high and low voltage devices can be integrated onto the same integrated circuit. In one embodiment, the lightly doped p-well and the standard p-well are formed by performing ion implantation using a first dose to form the lightly doped p-well, masking the lightly doped p-well, and performing ion implantation using a second dose to form the standard p-well. The second dose is the difference of the dopant concentrations of the lightly doped p-well and the standard p-well. Other high voltage devices can also be built by incorporating the lightly doped p-well structure.Type: GrantFiled: July 25, 2005Date of Patent: July 20, 2010Assignee: Micrel IncorporatedInventor: Hideaki Tsuchiko
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Patent number: 7759764Abstract: A semiconductor structure includes a substrate; an isolation structure in the substrate, wherein the isolation structure defines a region therein; a first semiconductor region having at least a portion in the region defined by the isolation structure, wherein the first semiconductor region is of a first conductivity type; a second semiconductor region on the first semiconductor region, wherein the second semiconductor region is of a second conductivity type opposite the first conductivity type; and a third semiconductor region of the first conductivity type on the second semiconductor region, wherein the third semiconductor region has at least a portion higher than a top surface of the isolation structure.Type: GrantFiled: January 26, 2007Date of Patent: July 20, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chuan-Ying Lee, Denny Duan-lee Tang
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Patent number: 7679164Abstract: Embodiments of the invention provide a semiconductor device including a collector in an active region; a first and a second sub-collector, the first sub-collector being a heavily doped semiconductor material adjacent to the collector and the second sub-collector being a silicided sub-collector next to the first sub-collector; and a silicided reach-through in contact with the second sub-collector, wherein the first and second sub-collectors and the silicided reach-through provide a continuous conductive pathway for electrical charges collected by the collector from the active region. Embodiments of the invention also provide methods of fabricating the same.Type: GrantFiled: January 5, 2007Date of Patent: March 16, 2010Assignee: International Business Machines CorporationInventors: Francois Pagette, Christian Lavoie, Anna Topol
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Publication number: 20100025809Abstract: An integrated circuit having a substrate with a first conductivity type of semiconductor material. A buried layer is formed in the substrate. The buried layer has a second conductivity type of semiconductor material. A first semiconductor layer is formed over the buried layer. The first semiconductor layer has the second conductivity type of semiconductor material. A trench is formed through the first semiconductor layer and buried layer and extends into the substrate. The trench is lined with an insulating layer and filled with an insulating material. A second semiconductor layer is formed in the first semiconductor layer. The second semiconductor layer has the first conductivity type of semiconductor material. A third semiconductor layer is formed in the second semiconductor layer. The third semiconductor layer has the second conductivity type of semiconductor material. The first, second, and third semiconductor layers form the collector, base, and emitter of a bipolar transistor.Type: ApplicationFiled: July 30, 2008Publication date: February 4, 2010Applicant: TRION TECHNOLOGY, INC.Inventor: Ronald R. Bowman
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Publication number: 20100025808Abstract: The invention provides a bipolar transistor with a reduced collector series resistance integrated in a trench (4, 44) of a standard CMOS shallow trench isolation region. The bipolar transistor includes a collector region (6, 34) manufactured in one fabrication step, therefore having a shorter conductive path with a reduced collector series resistance, improving the high frequency performance of the bipolar transistor. The bipolar transistor further includes a base region (8, 22, 38) with a first part on a selected portion of the collector region (6, 34), which is on the bottom of the trench (4, 44), and an emitter region (10, 24, 39) on a selected portion of the first part of the base region (8, 22, 38). A base contact (11, 26, 51) electrically contacts the base region (8, 22, 38) on a second part of the base region (8, 22, 38), which is on an insulating region (2, 42). The collector region (6, 34) is electrically contacted on top of a protrusion (5, 45) with a collector contact (13, 25, 50).Type: ApplicationFiled: January 12, 2006Publication date: February 4, 2010Applicant: NXP B.V.Inventors: Johannes J. T. M. Donkers, Wibo D. Van Noort, Philippe Meunier-Beillard
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Publication number: 20100001369Abstract: A semiconductor device is provided that includes a semiconductor substrate having a first region and a second region, transistors having metal gates formed in the first region, an isolation structure formed in the second region, at least one junction device formed proximate the isolation structure in the second region, and a stopping structure formed overlying the isolation structure in the second region.Type: ApplicationFiled: May 22, 2009Publication date: January 7, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Harry Chuang, Kong-Beng Thei, Chiung-Han Yeh, Mong-Song Liang, Hou-Ju Li, Ming-Yuan Wu
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Publication number: 20090315084Abstract: A semiconductor device includes a semiconductor substrate, a gate pattern disposed on the semiconductor substrate, a body region disposed on the gate pattern and a first impurity doping region and a second impurity doping region. The gate pattern is disposed below the body region and the first impurity doping region and the second impurity doping region.Type: ApplicationFiled: May 27, 2009Publication date: December 24, 2009Inventors: Dae-kil Cha, Won-Joo Kim, Tae-Hee Lee, Yoon-Dong Park
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Publication number: 20090267689Abstract: A semiconductor amplifier is provided comprising, a substrate and one or more unit amplifying cells (UACs) formed on the substrate, wherein each UAC is laterally surrounded by a first lateral dielectric filled trench (DFT) isolation wall extending at least to the substrate and multiple UACs are surrounded by a second lateral DFT isolation wall of similar depth outside the first isolation walls, and further semiconductor regions lying between the first isolation walls when two or more unit cells are present, and/or lying between the first and second isolation walls, are electrically floating with respect to the substrate. This reduces the parasitic capacitance of the amplifying cells and improves the power added efficiency. Excessive leakage between buried layer contacts when using high resistivity substrates is avoided by providing a further semiconductor layer of intermediate doping between the substrate and the buried layer contacts.Type: ApplicationFiled: April 25, 2008Publication date: October 29, 2009Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Dragan Zupac, Brian D. Griesbach, Theresa M. Keller, Joel E. Keys, Sandra J. Wipf, Evan F. Yu
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Publication number: 20090250785Abstract: The disclosed subject matter provides a method of forming a bipolar transistor. The method includes depositing a first insulating layer over a first layer of material that is doped with a dopant of a first type. The first layer is formed over a substrate. The method also includes modifying a thickness of the first oxide layer based on a target dopant profile and implanting a dopant of the first type in the first layer. The dopant is implanted at an energy selected based on the modified thickness of the first insulating layer and the target dopant profile.Type: ApplicationFiled: April 2, 2008Publication date: October 8, 2009Inventors: Thomas Joseph Krutsick, Christopher J. Speyer
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Patent number: 7576406Abstract: A plurality of the same kind of npn-type bipolar transistors are disposed regularly on a semiconductor layer that is provided over an insulation layer. The plurality of unit bipolar transistors are connected in parallel, thereby to form a plurality of desired bipolar transistors. A deep trench isolation surrounds a group of or the whole of the plurality of unit bipolar transistors that are connected in parallel, for a plurality of desired bipolar transistor that require thermal stability.Type: GrantFiled: February 9, 2004Date of Patent: August 18, 2009Assignee: Hitachi, Ltd.Inventors: Yoichi Tamaki, Hideaki Nonami, Masato Hamamoto
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Publication number: 20090160016Abstract: A semiconductor device having a bipolar transistor improved with heat dissipation. A semiconductor device having bipolar transistors formed in a plurality of device forming regions electrically isolated from each other by device isolation trenches traversing the semiconductor layer, in which a device isolation trench for each of unit bipolar transistors connected in parallel is removed and the plurality of unit bipolar transistors connected in series are entirely surrounded with one device isolation trench.Type: ApplicationFiled: February 18, 2009Publication date: June 25, 2009Inventors: Mitsuru ARAI, Shinichiro Wada, Hideaki Nonami
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Publication number: 20090127628Abstract: A structure includes a substrate. A trench structure is arranged within the substrate. A film is placed under an interlevel dielectric pad and between portions of the trench structure.Type: ApplicationFiled: October 22, 2008Publication date: May 21, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ephrem G. GEBRESELASIE, William T. Motsiff, Wolfgang Sauter, Steven H. Voldman
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Patent number: 7521772Abstract: A heterostructure bipolar transistor (HBT) and related methods are disclosed. In one embodiment, the HBT includes a heterostructure bipolar transistor (HBT) including: a substrate; a monocrystalline emitter atop the substrate; a collector in the substrate; at least one isolation region adjacent to the collector; a monocrystalline silicon germanium (SiGe) intrinsic base extending over each isolation region; and a monocrystalline silicon extrinsic base. A method may include forming the intrinsic and extrinsic base and the emitter as monocrystalline, with the extrinsic base (and emitter) formed in a self-aligned fashion utilizing selective-epitaxial growth on porous silicon. As a result, some mask levels can be omitted, making this an inexpensive alternative to conventional processing.Type: GrantFiled: November 8, 2006Date of Patent: April 21, 2009Assignee: International Business Machines CorporationInventors: Thomas N Adam, Thomas A. Wallner
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Patent number: 7492031Abstract: A semiconductor device comprises a first base layer of a first conductive type which has a first surface and a second surface; a second base layer of a second conductive type which is formed on the first surface; first and second gate electrodes which are formed by embedding an electrically conductive material into a plurality of trenches via gate insulating films, the plurality of trenches being formed such that bottoms of the trenches reach the first base layer; source layers of the first conductive type which are formed on a surface area of the second base layer so as to be adjacent to both side walls of the trench provided with the first gate electrode and one side wall of the trench provided with the second gate electrode, respectively; an emitter layer of the second conductive type which is formed on the second surface; emitter electrodes which are formed on the second base layer and the source layers; a collector electrode which is formed on the emitter layer; and first and second terminals which are eType: GrantFiled: May 16, 2006Date of Patent: February 17, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Koichi Sugiyama, Tomoki Inoue, Hideaki Ninomiya, Masakazu Yamaguchi
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Patent number: 7466008Abstract: A BiCMOS device with enhanced performance by mechanical uniaxial strain is provided. A first embodiment of the present invention includes an NMOS transistor, a PMOS transistor, and a bipolar transistor formed on different areas of the substrate. A first contact etch stop layer with tensile stress is formed over the NMOS transistor, and a second contact etch stop layer with compressive stress is formed over the PMOS transistor and the bipolar transistor, allowing for an enhancement of each device. Another embodiment has, in addition to the stressed contact etch stop layers, strained channel regions in the PMOS transistor and the NMOS transistor, and a strained base in the BJT.Type: GrantFiled: March 13, 2007Date of Patent: December 16, 2008Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hsin Ko, Tzu-Juei Wang, Hung-Wei Chen, Chung-Hu Ke, Wen-Chin Lee
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Publication number: 20080258211Abstract: In a MIS-type semiconductor device having a trench gate structure, a withstand voltage is ensured without changing the thickness of a drift layer and on-resistance can be reduced without applying a high gate drive voltage. The lower half of a trench extending through a p-base region into an n-drift region is filled with a high-permittivity dielectric having a relative permittivity that is higher than that of a silicon oxide film, preferably a silicon nitride film, and an insulated gate structure including a gate insulator and a gate electrode is fabricated on the high-permittivity dielectric. The depth d2 of the deepest portion of the high-permittivity dielectric is designed to be deeper than the depth d1 of a depletion layer in the semiconductor region away from the high-permittivity dielectric.Type: ApplicationFiled: January 31, 2008Publication date: October 23, 2008Applicant: FUJI ELECTRIC HOLDINGS CO., LTD.Inventors: Akio SUGI, Tatsuji NAGAOKA, Hong-fei LU
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Patent number: 7439607Abstract: A method of forming semiconductor device treating a surface of a substrate to produce a discontinuous growth of a material on the surface through rapid thermal oxidation of the substrate surface at a temperature of less than about 700° C.Type: GrantFiled: October 11, 2005Date of Patent: October 21, 2008Assignee: International Business Machines CorporationInventors: Arne W. Ballantine, Douglas D. Coolbaugh, Steve S. Williams
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Publication number: 20080230869Abstract: The present invention provides a “collector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped collector. Instead, the inventive vertical SOI BJT uses a back gate-induced, minority carrier inversion layer as the intrinsic collector when it operates. In accordance with the present invention, the SOI substrate is biased such that an inversion layer is formed at the bottom of the base region serving as the collector. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS.Type: ApplicationFiled: April 8, 2008Publication date: September 25, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Herbert L. Ho, Mahender Kumar, Qiqing Ouyang, Paul A. Papworth, Christopher D. Sheraw, Michael D. Steigerwalt
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Patent number: 7420228Abstract: A bipolar transistor comprising a collector region of a first conduction type, and a subcollector region of the first conduction type at a first side of the collector region. The transistor further includes a base region of the second conduction type provided at a second side of the collector region, and an emitter region of the first conduction type which is provided above the base region on the side remote from the collection region. A carbon-doped semiconductor region is provided on the first side alongside the collector region. The bipolar transistor is characterized in that the carbon-doped semiconductor region has a carbon concentration of 1019-1021 cm?3 and the base region has a smaller cross section than the collector region and the collector region has, in the overlap region with the base region, a region having an increased doping compared with the remaining region.Type: GrantFiled: October 7, 2005Date of Patent: September 2, 2008Assignee: Infineon Technologies AGInventors: Josef Bock, Thomas Meister, Reinhard Stengl, Herbert Schafer
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Patent number: 7397070Abstract: In one embodiment, a transistor is formed to use two conductors to make electrical connection to one of the active regions of the transistor.Type: GrantFiled: September 28, 2007Date of Patent: July 8, 2008Assignee: Semiconductor Components Industries, L.L.C.Inventor: Gordon M. Grivna
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Patent number: 7375410Abstract: The present invention provides a “collector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped collector. Instead, the inventive vertical SOI BJT uses a back gate-induced, minority carrier inversion layer as the intrinsic collector when it operates. In accordance with the present invention, the SOI substrate is biased such that an inversion layer is formed at the bottom of the base region serving as the collector. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS.Type: GrantFiled: February 25, 2004Date of Patent: May 20, 2008Assignee: International Business Machines CorporationInventors: Herbert L. Ho, Mahender Kumar, Qiqing Ouyang, Paul A. Papworth, Christopher D. Sheraw, Michael D. Steigerwalt
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Patent number: 7355263Abstract: A semiconductor device and method of manufacturing the same includes an n?-single crystal silicon substrate, with an oxide film selectively formed thereon. On the oxide film, gate polysilicon is formed. The surface of the gate polysilicon is covered with a gate oxide film whose surface is covered with a cathode film doped in an n-type with an impurity concentration higher than that of the substrate as an n?-drift layer. In the cathode film, a section in contact with the substrate becomes an n+-buffer region with a high impurity concentration, next to which a p-base region is formed. Next to the p-base region, an n+-source region is formed. On the cathode film, an interlayer insulator film is selectively formed on which an emitter electrode is formed. A semiconductor device such as an IGBT is obtained with a high rate of acceptable products, an excellent on-voltage to turn-off loss tradeoff and an excellent on-voltage to breakdown voltage tradeoff.Type: GrantFiled: June 14, 2007Date of Patent: April 8, 2008Assignee: Fuji Electric Holdings Co., Ltd.Inventor: Manabu Takei
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Patent number: 7342293Abstract: The present invention relates to bipolar junction transistors (BJTS). The collector region of each BJT is located in a semiconductor substrate surface and adjacent to a first shallow trench isolation (STI) region. A second STI region is provided, which extends between the first STI region and the collection region and undercuts a portion of the active base region with an undercut angle of not more than about 90°. For example, the second STI region may a substantially triangular cross-section with an undercut angle of less than about 90°, or a substantially rectangular cross-section with an undercut angle of about 90°. Such a second STI region can be fabricated using a porous surface section formed in an upper surface of the collector region.Type: GrantFiled: December 5, 2005Date of Patent: March 11, 2008Assignee: International Business Machines CorporationInventors: Thomas A. Wallner, Thomas N. Adam, Stephen W. Bedell, Joel P. De Souza