Abstract: Embodiments discussed herein relate to processes of producing a field stop zone within a semiconductor substrate by implanting dopant atoms into the substrate to form a field stop zone between a channel region and a surface of the substrate, at least some of the dopant atoms having energy levels of at least 0.15 eV below the energy level of the conduction band edge of semiconductor substrate; and laser annealing the field stop zone.

Abstract: According to an exemplary embodiment, a structure includes a silicon-on-insulator substrate including a buried oxide layer situated over a bulk silicon substrate and a silicon layer situated over the buried oxide layer. The structure further includes a trench formed in the silicon layer and the buried oxide layer, where the trench has a bottom surface and a first and a second sidewall, and where the trench is situated adjacent to an optical region of the silicon-on-insulator substrate. According to this exemplary embodiment, the structure further includes an epitaxial layer situated in the trench and situated on the bulk silicon substrate, where the epitaxial layer and the bulk silicon substrate form a bulk silicon electronic region of the silicon-on-insulator substrate. The structure further includes a base of a bipolar transistor situated on the epitaxial layer, where the base can be silicon-germanium.

Abstract: An optoelectronic circuit includes a resonant cavity formed on a substrate and into which is injected an input digital optical signal that encodes bits of information (each bit representing an OFF logic level or an ON logic level). A heterojunction thyristor device, formed in the resonant cavity, produces an output digital electrical signal corresponding to the input digital optical signal. A sampling clock defines sampling periods that overlap the bits (e.g., ON/OFF pulse durations) in the input digital optical signal. The sampling clock can be in the form of electrical pulses supplied to the n-channel injector terminal(s) and/or p-channel injector terminals of the heterojunction thyristor device. Alternatively, the sampling clock can be in the form of optical pulses that are part of the Optical IN signal that is resonantly absorbed by the device. The heterojunction thyristor device operates in an OFF state and an ON state.

Abstract: In one embodiment, a transistor is formed to use two conductors to make electrical connection to one of the active regions of the transistor.

Abstract: Present invention proposes a dramatic improvement of CMOS IC technology by providing high speed bipolar current amplifiers compatible with CMOS technological process while retaining the footprint compatible to one of standard CMOS devices. This invention promises further increase of speed of ICs as well as a reduction of power dissipation.

Abstract: A semiconductor device and method of manufacturing the same includes an n?-single crystal silicon substrate, with an oxide film selectively formed thereon. On the oxide film, gate polysilicon is formed. The surface of the gate polysilicon is covered with a gate oxide film whose surface is covered with a cathode film doped in an n-type with an impurity concentration higher than that of the substrate as an n?-drift layer. In the cathode film, a section in contact with the substrate becomes an n+-buffer region with a high impurity concentration, next to which a p-base region is formed. Next to the p-base region, an n+-source region is formed. On the cathode film, an interlayer insulator film is selectively formed on which an emitter electrode is formed. A semiconductor device such as an IGBT is obtained with a high rate of acceptable products, an excellent on-voltage to turn-off loss tradeoff and an excellent on-voltage to breakdown voltage tradeoff.

Abstract: A lateral bipolar transistor includes an emitter region, a base region, a collector region, and a gate disposed over the base region. A bias line is connected to the gate for applying a bias voltage thereto during operation of the transistor. The polarity of the bias voltage is such as to create an accumulation layer in the base under the gate. The accumulation layer provides a low-resistance path for the transistor base current, thus reducing the base resistance of the transistor.

Abstract: A semiconductor device is disclosed that reduces the reverse leakage current caused by reverse bias voltage application and reduces the on-voltage of the IGBT. A two-way switching device using the semiconductor devices is provided, and a method of manufacturing the semiconductor device is disclosed. The reverse blocking IGBT reduces the reverse leakage current and the on-voltage by bringing portions of an n?-type drift region 1 that extend between p-type base regions and an emitter electrode into Schottky contact to form Schottky junctions.

Abstract: The present invention provides a “subcollector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped subcollector. Instead, the inventive vertical SOI BJT uses a back gate-induced, majority carrier accumulation layer as the subcollector when it operates. The SOI substrate is biased such that the accumulation layer is formed at the bottom of the first semiconductor layer. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS. A back-gated CMOS device is also provided.

Abstract: A process for forming bipolar junction transistors having a plurality of different collector doping densities on a semiconductor substrate and an integrated circuit comprising bipolar junction transistors having a plurality of different collector doping densities. A first group of the transistors are formed during formation of a triple well for use in providing triple well isolation for complementary metal oxide semiconductor field effect transistors also formed on the semiconductor substrate. Additional bipolar junction transistors with different collector doping densities are formed during a second doping step after forming a gate stack for the field effect transistors. Implant doping through bipolar transistor emitter windows forms bipolar transistors having different doping densities than the previously formed bipolar transistors.

Abstract: A PMOS transistor (Q2) provided for developing a short circuit between the base and emitter of an N-type IGBT during turn-OFF includes a P diffusion region (5), a P diffusion region (6), and a conductive film (10) and a second gate electrode (15) provided via a gate oxide film (21) on a surface of an N? epitaxial layer (2) between the P diffusion regions (5 and 6). The gate oxide film (21) is formed in a thickness having a gate breakdown voltage higher than the element breakdown voltage of a typical field oxide film and the like.

Abstract: A semiconductor integrated circuit device according to the invention includes an N-type embedded diffusion region between a substrate and a first epitaxial layer in island regions serving as small signal section. The substrate and the first epitaxial layer are thus partitioned by the N-type embedded diffusion region having supply potential in the island regions serving as small signal section. This structure prevents the inflow of free carriers (electrons) generated from a power NPN transistor due to the back electromotive force of the motor into the small signal section, thus preventing the malfunction of the small signal section.

Abstract: The invention includes BIFETRAM devices. Such devices comprise a bipolar transistor in combination with a field effect transistor (FET) in a three-dimensional stacked configuration. The memory devices can be incorporated within semiconductor-on-insulator (SOI) constructions. The base region of the bipolar device can be physically and electrically connected to one of the source/drain regions of the FET to act as a storage node for the memory cell. The semiconductor material of the SOI constructions can comprise Si/Ge, and the active region of the FET can extend into the Si/Ge. The SOI constructions can be formed over any of a number of substrates, including, for example, semiconductive materials, glass, aluminum oxide, silicon dioxide, metals and/or plastics.

Abstract: A method of forming semiconductor device treating a surface of a substrate to produce a discontinuous growth of a material on the surface through rapid thermal oxidation of the substrate surface at a temperature of less than about 700° C.

Abstract: Complementary metal-oxide-semiconductor (CMOS) integrated circuits with bipolar transistors and methods for fabrication are provided. A bipolar transistor may have a lightly-doped base region. To reduce the resistance associated with making electrical contact to the lightly-doped base region, a low-resistance current path into the base region may be provided. The low-resistance current path may be provided by a base conductor formed from heavily-doped epitaxial crystalline semiconductor. Metal-oxide-semiconductor (MOS) transistors with narrow gates may be formed on the same substrate as bipolar transistors. The MOS gates may be formed using a self-aligned process in which a patterned gate conductor layer serves as both an implantation mask and as a gate conductor. A base masking layer that is separate from the patterned gate conductor layer may be used as an implantation mask for defining the lightly-doped base region.

Abstract: One embodiment is a method for fabricating the base of a bipolar transistor where the method comprises placing a first wafer in an undoped epi chamber. Next a first undoped base layer is grown over the first wafer. After growing the first undoped base layer, the first wafer is transferred from the undoped epi chamber into a separate doped epi chamber. A first doped base layer is then grown over the first undoped based layer in the doped epi chamber. While the first wafer is being processed in the doped epi chamber, a second wafer can be processed in the undoped epi chamber. Another embodiment is a structure produced by the disclosed method and yet another embodiment comprises a transfer chamber, a transfer arm, a bake chamber, and a separate undoped epi chamber and a doped epi chamber for practicing the disclosed method.

Abstract: A layout method of a semiconductor integrated circuit is provided which improves characteristics of the circuit by giving hierarchical structure of interconnections regularity. A pair of emitter followers is disposed symmetrically with respect to a center line of a differential amplifier. Thus, interconnections within a circuit block and a ground wiring can be made with a single metal layer, since an area where the interconnections cross with each other is eliminated. Herewith cross talk due to the intersection of the interconnections can be resolved. Also, the interconnections between the differential amplifier and the emitter follower circuits can be made equal in length. It is possible to assign a second metal layer to interconnections between circuit blocks and a third metal layer to a power supply so that characteristics of the semiconductor integrated circuit are improved.

Abstract: The present invention relates to a semiconductor device arranged at a surface of a semiconductor substrate having an initial doping having an electrical connection comprising at least one plug made of a material with a high conductivity, especially a material other than the substrate, especially a metal plug, between said initially doped substrate and said surface of the substrate. The device has at least one ground connection arranged to be connected to a ground pin on a package. The ground connection is arranged to be connected to said ground pin using said electrical connection, where the initially doped substrate is arranged to be connected to said ground pin via a reverse side of the substrate, opposite said surface, and thereby being arranged to establish a connection between said ground connection and said ground pin.

Abstract: A semiconductor device in which a vertical pnp-bipolar transistor is formed in a prescribed element region on a semiconductor substrate includes: a buried n+-layer of a high concentration formed in the prescribed element region; and a p-type collector layer formed on the buried n+-layer. By introducing impurities that has a larger diffusion coefficient than the buried n+-layer, the collector layer can be formed on the buried n+-layer formed in common with other element regions, without any special masking.

Abstract: A bipolar transistor in which the occurrence of Kirk effect is suppressed when a high current is injected into the bipolar transistor and a method of fabricating the bipolar transistor are described. The bipolar transistor includes a first collector region of a first conductive type having high impurity concentration, a second collector region of a first conductive type which has high impurity concentration and is formed on the first collector region, a base region of a second conductive type being formed a predetermined portion of the second collector region, and an emitter region of a first conductive type being formed in the base region. The bipolar transistor further includes the third collector region, which has higher impurity concentration than the second collector region, at the bottom of the base region.

Abstract: Disclosed is a bipolar complementary metal oxide semiconductor (BiCMOS) or NPN/PNP device that has a collector, an intrinsic base above the collector, shallow trench isolation regions adjacent the collector, a raised extrinsic base above the intrinsic base, a T-shaped emitter above the extrinic base, spacers adjacent the emitter, and a silicide layer that is separated from the emitter by the spacers.

Abstract: An ESD protection device encompassing a vertical bipolar transistor that is connected as a diode and has an additional displaced base area. The assemblage has a space-saving configuration and a decreased difference between snapback voltage and breakdown voltage.

Abstract: The forming of a contact with a deep region of a first conductivity type formed in a silicon substrate. The contact includes a doped silicon well region of the first conductivity type and an intermediary region connected between the deep layer and the well. This intermediary connection region is located under a trench. The manufacturing method enables forming of vertical devices, in particular fast bipolar transistors.

Abstract: An n-type well is formed in a p?-type semiconductor substrate and a p?-type epitaxial layer is formed on; the n-type well. An n?-type well is formed in the, p-type epitaxial layer on the n-type well so as to allow a RESURF operation. A p-type island is formed in the n?-type well at a position above the n-type well to form an island region for high withstand-voltage separation. Thus, the withstand voltage of the separated island is improved.

Abstract: A bipolar transistor includes the first group of transistors 610a, the second group of transistors 610b, the third group of transistors 610c and the fourth group of transistors 610d. The groups of transistors have unit transistors with emitters, bases and collectors that are connected electrically in parallel and the number of unit transistors is different from group to group and 2, 4, 8, and 16, respectively.

Abstract: A method and a BICMOS structure are provided. The BiCMOS structure includes an SOI substrate having a bottom Si-containing layer, a buried insulating layer located atop the bottom Si-containing layer, a top Si-containing layer atop the buried insulating layer and a sub-collector which is located in an upper surface of the bottom Si-containing layer. The sub-collector is in contact with a bottom surface of the buried insulating layer.

Abstract: An evaluation configuration has a first MOS evaluation stage, an isolation stage, and a bipolar evaluation stage. The isolation stage is connected between the first MOS evaluation stage and the bipolar evaluation stage. The isolation stage isolates the first MOS evaluation stage from the bipolar evaluation stage. The evaluation configuration can reliably detect very small read signals and allows a high integration density.

Abstract: A bipolar junction transistor (BJT) includes a dielectric layer formed on a predetermined region of a substrate, an opening formed in the dielectric layer and a portion of the substrate being exposed, a heavily doped polysilicon layer formed on a sidewall of the opening to define a self-aligned base region in the opening, an intrinsic base doped region formed within the substrate and in a bottom of the opening by implanting through the self-aligned base region, a spacer formed on the heavily doped polysilicon layer to define a self-aligned emitter region in the opening, and an emitter conductivity layer being filled with the self-aligned emitter region and a PN junction being formed between the emitter conductivity layer and the intrinsic base doped region.

Abstract: In a semiconductor device having a semiconductor element having a plurality of SOI-Si layers, the height of element isolation regions from the surface of the semiconductor substrate are substantially equal to each other. Alternatively, the element isolation regions are formed at the equal height on the semiconductor substrate and then a plurality of SOI-Si layers appropriately different in thickness are formed. In this manner, it is possible to obtain element isolation regions having substantially the same height from the semiconductor substrate and desired element regions having SOI-Si layers different in height. The thickness of a single crystalline silicon film (SOI-Si layer) may be appropriately changed by another method which includes depositing an amorphous silicon film and applying a heat processing to form an epi layer, and removing an unnecessary portion.

Abstract: The operating temperature range for a vertical PNP transistor can be extended by applying cancellation techniques. The vertical PNP generates a first leakage current from the base-collector region. Another vertical PNP transistor is configured to generate a second leakage current, which is coupled to a current-mirror circuit. The output of the current-mirror circuit is configured to provide a cancellation effect on the first leakage current. The current-mirror circuit and vertical PNP may be configured such that the first leakage current is cancelled in a judicious amount, whereby the effects of leakage current and flare-out in the vertical PNP transistor are minimized or cancelled. The cancellation technique is applicable to temperature sensor circuits, thermal voltage generators, and bandgap circuits.

Abstract: A method for manufacturing a semiconductor device includes forming a buried layer of a semiconductor substrate. An active region is formed adjacent at least a portion of the buried layer. At least part of the active region is removed to form a shallow trench opening. A dielectric layer is formed proximate the active region at least partially within the shallow trench opening. At least part of the dielectric layer is removed to form a collector contact region. A collector contact may be formed at the collector contact region. The collector contact may be operable to electrically contact the buried layer.

Abstract: High-voltage bipolar transistors (30, 60) in silicon-on-insulator (SOI) integrated circuits are disclosed. In one disclosed embodiment, an collector region (28) is formed in epitaxial silicon (24, 25) disposed over a buried insulator layer (22). A base region (32) and emitter (36) are disposed over the collector region (28). Buried collector region (31) are disposed in the epitaxial silicon (24) away from the base region (32). The transistor may be arranged in a rectangular fashion, as conventional, or alternatively by forming an annular buried collector region (31). According to another disclosed embodiment, a high voltage transistor (60) includes a central isolation structure (62), so that the base region (65) and emitter region (66) are ring-shaped to provide improved performance. A process for fabricating the high voltage transistor (30, 60) simultaneously with a high performance transistor (40) is also disclosed.

Abstract: An NPN bipolar transistor and a PNP bipolar transistor are formed in a semiconductor substrate. The NPN bipolar transistor has a p type emitter region, a p type collector region and an n type base region and is formed in an NPN forming region. The PNP bipolar transistor has an n type emitter region, an n type collector region and a p type base region and is formed in a PNP forming region. Only one conductive type burying region is formed in at least one of the NPN forming region and the PNP forming region. A current that flows from the p type emitter region to the n type base region flows in the n type base region in a direction perpendicular to the substrate.

Abstract: An electronic circuit comprises a bipolar transistor that includes a conductive back electrode, an insulator layer over the conductive back electrode and a semiconductor layer of either an n-type or p-type material over the insulator layer. The semiconductor layer includes a doped region, used as the collector and a heavily doped region, bordering the doped region, used as a reachthrough between the insulator layer and the collector contact electrode. A majority-carrier accumulation layer is induced adjacent to the insulator in the doped region of the collector by the application of a bias voltage to the back electrode.

Abstract: An integrated electronic device includes a semiconductor substrate layer having a major surface formed along a crystal plane. In one embodiment a first conductivity type region is formed in the substrate layer and a substantially monocrystalline semiconductor layer is deposited thereon. The deposited layer includes a first portion of a second conductivity type and a second portion of the first conductivity type formed over the first portion. The first portion and the first region form a pn junction. An upper-most substrate surface formed along a first plane and a first doped region of a first conductivity type is formed above the first plane. A second doped region of a second conductivity type is formed over the first doped region resulting in formation of a p-n junction in a second plane above the first plane. Electrical connection is provided to the first doped region with a conductor formed between the first and second planes.

Abstract: An integrated circuit including a buried layer of determined conductivity type in a plane substantially parallel to the plane of a main circuit surface, in which the median portion of this buried layer is filled with a metal-type material.

Abstract: The lateral pnp transistor encompasses a p-type semiconductor substrate, an n-type first buried region disposed on the semiconductor substrate, an n-type uniform base region disposed on the first buried region, an n-type first plug region disposed in the uniform base region, a p-type first emitter region and a first collector region disposed in and at the top surface of the uniform base region, a graded base region disposed in the uniform base region and a first base contact region disposed in the first plug region. The graded base region encloses the bottom and the side of the first main electrode region. The doping profile in the graded base region intervening between the first emitter region and the first collector region is such that the impurity concentration is gradually decreases towards the second main electrode region from the first main electrode region.

Abstract: In an element formation region, a surface of an N− epitaxial layer is inclined upward from an end of a field oxide film to a sidewall of an opening. An external base diffusion layer at the surface of the N− epitaxial layer is inclined upward from a side of the field oxide film to the sidewall of the opening, and is exposed at the sidewall of the opening. A portion of the sidewall of the opening exposing the external base diffusion layer is tapered. The depth of a lower end of the external base diffusion layer or the sidewall of the opening is substantially equal to or smaller than that of a bottom of the opening. A decrease in breakdown voltage between an emitter and a base is suppressed, and decrease and variation of current gain hFE is suppressed.

Abstract: An integrated circuit that includes a high breakdown voltage bipolar transistor. The bipolar transistor includes an emitter 36, a base 32, and a collector structure. The emitter 36 is adjacent to and overlies the base 32 and the base 32 is adjacent to and overlies a core portion 48 of the collector structure. The collector structure includes, in addition to the core portion 48, a collector contact region 31 and a lateral collector region 50 between the core portion 48 and the collector contact region 31. The lateral collector region 50 is thinner than said collector contact region at some point along its length.

Abstract: A process for forming at least one interface region between two regions of semiconductor material. At least one region of dielectric material comprising nitrogen is formed in the vicinity of at least a portion of a boundary between the two regions of semiconductor material, thereby controlling electrical resistance at the interface.

Abstract: A method for adjusting the gain or the sensitivity of a lateral component formed in the front surface of a semiconductor wafer, having a first conductivity type, includes not doping or overdoping, according to the first conductivity type, the back surface when it is desired to reduce the gain or sensitivity of the lateral component, and doping according to the second conductivity type, the back surface, when the gain or the sensitivity of the lateral component is to be increased.

Abstract: Existing polysilicon emitter technology is used to contact poly fill in a trench isolation structure. A standard single poly emitter window process is followed. An “emitter window” is masked directly over the polysilicon trench fill. Heavily doped single emitter poly is deposited and masked over the entire active region. The standard emitter drive then diffuses dopant through the emitter window into the undoped trench poly fill to provide an ohmic contact between the emitter poly and the trench poly fill. Contact to the emitter poly is made from overlying metal.

Abstract: A semiconductor device includes an epitaxial layer formed on a P type silicon substrate; a P+ diffusion layer for dividing the epitaxial layer into an N− epi layer, which constitutes a device formation region, and an N− epi layer, which constitutes an invalid area; and an aluminum wire for electrically connecting the N− epi layer (invalid area) to the P+ diffusion layer. Since the potential of the N− epi layer (invalid area) can be made equal to that of the P+ diffusion layer, it is possible to prevent the electron supply from the P+ diffusion layer to the invalid area even when electrons are supplied to the device formation region by a counterelectromotive force produced by a load having an inductance L.

Abstract: A silicon on insulator substrate is provided to include the following: a handle wafer; a layer of bonding material; a device wafer, the device wafer including at least one buried impurity region extending from the layer of bonding material upward into the device wafer; and an epitaxial silicon layer provided on a second surface of the device wafer. The silicon on insulator substrate with this configuration can be made with a minimal possible thickness.

Abstract: An integrated circuit device receiving signals from a signal pad that includes at least one silicon bipolar junction transistor responsive to the signals from the signal pad for providing electrostatic discharge protection, and a detection circuit for detecting the signals from the signal pad and providing a bias voltage to the at least one silicon bipolar junction transistor, wherein the at least one silicon bipolar junction transistor includes an emitter, collector and base formed in a single silicon layer and isolated from a substrate of the integrated circuit device, and wherein the base is coupled to the detection circuit to receive the bias voltage.

Abstract: A silicon-germanium base capable of use in heterojunction bipolar transistor includes a silicon substrate having a mesa surrounded by a trench. The mesa has a top surface and a silicon-germanium layer is disposed only on the top surface of the mesa. In addition, a heterojunction bipolar transistor includes the silicon-germanium base as described.

Abstract: Integrated circuit including a power component with vertical current flow and at least one low or medium voltage component, the at least one low or medium voltage component formed in a first semiconductor layer separated from a second semiconductor layer by an insulating material layer. The power component with vertical current flow is formed in the second semiconductor layer, and excavations are formed in the insulating material layer which extend from a free surface of the first semiconductor layer to the second semiconductor layer, said excavations having lateral walls of insulating material and being filled up with a conductor material in order to electrically contact active regions of the power component in the second semiconductor layer by electrodes placed on the free surface of the first semiconductor layer.

Abstract: Disclosed herein is a communication module, comprising a semiconductor chip in which channels for allowing signal converting means to convert current signals inputted from input terminals to voltage signals and outputting the same from output terminals respectively are arranged in parallel in plural form, and wherein the semiconductor chip is comprised principally of a semiconductor substrate in which a second semiconductor layer is provided on a first semiconductor layer with an insulating layer interposed therebetween, each of the signal converting means is formed in a channel forming region of the second semiconductor layer, which is defined for each channel, and the input and output terminals are formed on the channel forming regions of the second semiconductor layer with the insulating layer interposed therebetween.

Abstract: A semiconductor device for an integrated injection logic cell having a pnp bipolar transistor structure formed on a semiconductor substrate, wherein at least one layer of insulating films formed on a base region of the pnp bipolar transistor structure is comprised of a silicon nitride film. The semiconductor device of the present invention is advantageous in that the silicon nitride film constituting at least one layer of the insulating films formed on the base region of the pnp bipolar transistor prevents an occurrence of contamination on the surface of the base region, so that both the properties of the pnp bipolar transistor and the operation of the IIL cell can be stabilized. Further, by the process of the present invention, the above-mentioned excellent semiconductor device can be produced.

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials.