Abstract: One embodiment of the present disclosure provides a semiconductor package including a bottom chip package having a first side and a second side opposing the first side, and a top antenna package mounted on the first side of the bottom chip package. The bottom chip package further includes a semiconductor chip. The semiconductor chip may include a RFIC chip. The top antenna package has at least one radiative antenna element.

Abstract: A memory device includes a memory cell array including a plurality of memory cells and a memory controller to control the plurality of memory cells. The memory cell array has a first fuse region including a plurality of first fuse cells having a same structure as the plurality of memory cells and a second fuse region including a plurality of second fuse cells having a structure different from a structure of the plurality of memory cells. The memory controller has a fuse selection circuit selecting one of the first fuse region and the second fuse region.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to uniplanar (e.g., single layer) passive circuitry and methods of manufacture. The structure includes: passive circuitry comprising plural components each of which are formed on a same wiring level; and interconnects on the same wiring level connecting the plural components of the passive circuitry.

Abstract: A package structure includes a first redistribution layer, a molding material, a semiconductor device and an inductor. The molding material is located on the first redistribution layer. The semiconductor device is molded in the molding material. The inductor penetrates through the molding material and electrically connected to the semiconductor device.

Abstract: A package includes an Integrated Voltage Regulator (IVR) die, wherein the IVR die includes metal pillars at a top surface of the first IVR die. The package further includes a first encapsulating material encapsulating the first IVR die therein, wherein the first encapsulating material has a top surface coplanar with top surfaces of the metal pillars. A plurality of redistribution lines is over the first encapsulating material and the IVR die. The plurality of redistribution lines is electrically coupled to the metal pillars. A core chip overlaps and is bonded to the plurality of redistribution lines. A second encapsulating material encapsulates the core chip therein, wherein edges of the first encapsulating material and respective edges of the second encapsulating material are vertically aligned to each other. An interposer or a package substrate is underlying and bonded to the IVR die.

Abstract: An inductor device includes a conductive coil formed within a dielectric material and having a central core area within the coil. Particles are dispersed within the central core region to reduce eddy current loss and increase energy storage. The particles include magnetic properties.

Abstract: An e-fuse for a semiconductor device includes first and second electrodes; a gate metal electrically coupling the first and second electrodes with each other; a semiconductor layer formed under the gate metal, and forming a capacitor together with the gate metal; and a first oxide layer formed under the gate metal and on both sides of the semiconductor layer.

Abstract: A method for execution by a dispersed storage and task (DST) execution unit includes generating location weight data that includes a plurality of location weights assigned to a plurality of memory devices of the DST execution unit. A first one of the plurality of memory devices and a second one of the plurality of memory devices are selected for reallocation based on the location weight data. The reallocation is executed by removing a data slice from the first one of the plurality of memory devices and storing the data slice in the second one of the plurality of memory devices.

Abstract: Fabrication methods for a 3D multipath inductor, including forming a metal layer to form spiral turns about a center region, the spiral turns including segments that extend length-wise along the turns and having positions that vary from an innermost position and an outermost position relative to the center region; forming a lateral cross-over configured to couple portions of lateral segments in different relative positions from the center region to form lateral segment paths that have a substantially same length for all lateral segment paths in a grouping thereof; forming an additional metal layer to form spiral turns about the center region including corresponding geometry to the first metal layer; and forming a vertical cross-over configured to couple portions of segments on different metal layers to form vertical segment paths that have a substantially same length for all vertical segment paths in a grouping thereof.

Abstract: An inductance device includes a coil provided with at least one electrically conductive turn having a first portion of turn formed on a face of a first substrate, and a second portion of turn. A first end of the first portion is electrically connected to a first end of the second portion by a conductive connection, and the coil has a longitudinal axis, around which the at least one turn is formed, which is perpendicular to a dimension in thickness of the first substrate. The second portion is formed on a face of a second substrate different from the first substrate, with the face of the first substrate facing the face of the second substrate, with the conductive connection extending into an interstitial space located between the face of the first substrate and the face of the second substrate.

Abstract: An electronic device includes: a multilayered dielectric substrate including a plurality of dielectric layers; a planar magnetic device disposed on at least one internal dielectric layer of the plurality of dielectric layers; and an overlapping shield assembly including a first shield layer and a second shield layer separated by at least one of the plurality of dielectric layers.

Abstract: A package packaged with a cap. The package features trenches, through holes, and a non-conductive coupling element forming a locking mechanism integrated embedded or integrated within a substrate. The package has a cap coupled to the non-conductive coupling element through ultrasonic plastic welding. The package protects the dice from an outside environment or external stresses or both. A method is desired to form package to reduce glue overflow defects in the package. Fabrication of the package comprises drilling holes in a substrate; forming trenches in the substrate; forming a non-conductive coupling element in the through holes and the trenches to form a locking mechanism; allowing the non-conductive coupling element to harden and cure; coupling a die or dice to the substrate; and coupling a cap to the non-conductive coupling element to protect the die or dice from an outside environment or external stresses or both.

Abstract: A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode. A second insulating layer is formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, and bump electrodes are formed on both electrodes.

Abstract: A connection system of semiconductor packages includes: a printed circuit board; a first semiconductor package disposed on a first surface of the printed circuit board and connected to the printed circuit board through first electrical connection structures; a second semiconductor package disposed on a second surface of the printed circuit board and connected to the printed circuit board through second electrical connection structures; and a third semiconductor package disposed on the first semiconductor package and connected to the first semiconductor package through third electrical connection structures. The first semiconductor package includes an application processor (AP), the second semiconductor package includes a memory, and the third semiconductor package includes a power management integrated circuit (PMIC).

Abstract: A semiconductor device includes: a plurality of vertical conductive structures, wherein each of the plurality of vertical conductive structures extends through an isolation layer; and an insulated extension disposed horizontally between a first one and a second one of the plurality of vertical conductive structures.

Abstract: A semiconductor assembly with a package on package (POP) structure includes a first semiconductor package having a first lower substrate, a first upper substrate facing the first lower substrate, and a first semiconductor chip mounted on an area of the first lower substrate. The POP structure further includes a second semiconductor package having a second lower substrate stacked on the first semiconductor package and spaced apart from the first semiconductor package, and a second semiconductor chip mounted in an area of the second lower substrate. At least one passive element is disposed in one of the first upper substrate and the second lower substrate and electrically connected to the second semiconductor chip.

Abstract: A fan-out process using chemical mechanical planarization (CMP) reduces the step-height between a semiconductor die and the surrounding overmolding of a reconstituted wafer. The reconstituted wafer is formed by overmolding a back side of at least one die that is placed with an active side facing down. The reconstituted wafer is then oriented to expose the die and the active side. A polymer layer is then formed over the reconstituted wafer. A CMP process then removes a portion of the polymer layer until a certain thickness above the die surface is obtained, reducing the step-height between the polymer layer on top of the die surface and the polymer layer on the adjacent mold compound surface. The CMP process can also be performed after a subsequent redistribution layer is formed on the reconstituted wafer.

Abstract: An impedance circuit includes a poly-resistor and a controller. The poly-resistor has a first terminal and a second terminal. The controller generates a first control voltage and a second control voltage. The resistance between the first terminal and the second terminal of the poly-resistor is determined according to the first control voltage and the second control voltage. The second control voltage is different from the first control voltage. The proposed impedance circuit can improve the linearity of the poly-resistor.

Abstract: A semiconductor device includes a p-type semiconductor substrate; an n-type drift layer on the substrate; an n-type drain region in contact with the drift layer to be provided on the semiconductor substrate at a center of the drift layer; a p-type gate region on the substrate in an outer side of the drift layer, the gate region including U-shaped first and second concave patterns in a planar pattern, each having entrances of the U-shapes located with equal distances from the drain region, the bottoms of the U-shapes protruding toward an outer side of the planar pattern; n-type source regions in an inner side of the first concave patterns, each of the source regions contacts with the drift layer and the gate region; and n-type surge-current guiding-regions in an inner side of the second concave patterns, each of the surge-current guiding-regions contacts with the drift layer and the gate region.

Abstract: A Micro Electro-Mechanical System (MEMS) device package includes a first circuit layer, a partition wall, a MEMS component, a second circuit layer and a polymeric dielectric layer. The partition wall is disposed over the first circuit layer. The MEMS component is disposed over the partition wall and electrically connected to the first circuit layer. The first circuit layer, the partition wall and the MEMS component enclose a space. The second circuit layer is disposed over and electrically connected to the first circuit layer. The polymeric dielectric layer is disposed between the first circuit layer and the second circuit layer.

Abstract: A device with pillar-shaped components, includes a substrate; a wiring layer disposed on the substrate; and pillar-shaped components disposed on any of the substrate and the wiring layer, each of the pillar-shaped components having a bottom part connected to the substrate and/or the wiring layer, a top part opposed to the bottom part, and a lateral face part extending from the bottom part and connected to the top part; wherein each of the pillar-shaped components includes a first pillar-shaped part formed by plating, a second pillar-shaped part formed on the first pillar-shaped part by plating, and a ring-like projection part formed on the lateral face part to project outward and extend in a circumferential direction, and to be in a position higher than a joint position between the first pillar-shaped part and the second pillar-shaped part.

Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, the electrical package may include a first package layer. A plurality of signal lines with a first thickness may be formed on the first package layer. Additionally, a power plane with a second thickness may be formed on the first package layer. According to an embodiment, the second thickness is greater than the first thickness. Embodiments of the invention may form the power plane with a lithographic patterning and deposition process that is different than the lithographic patterning and deposition process used to form the plurality of signal lines. In an embodiment, the power plane may be formed concurrently with vias that electrically couple the signal lines to the next routing layer.

Abstract: Embodiments of the invention include a microelectronic device that includes an overmolded component having a first die with a silicon based substrate. A second die is coupled to the first die with the second die being formed with compound semiconductor materials in a different substrate. A substrate is coupled to the first die. The substrate includes an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher.

Abstract: An integrated circuit for a packaged device is proposed. The circuit comprises: a circuit having first and second electromagnetic radiating elements fabricated on a die; a package substrate comprising an upper surface and a lower surface; and a grounding layer provided on the lower surface of the package substrate, the grounding layer being adapted to connect to a grounding plane of a printed circuit board. The die is mounted on the upper surface of the package substrate. The grounding layer comprises a void, at least a portion of the void being positioned so as to at least partially electromagnetically isolate the first electromagnetic radiating element from the second electromagnetic radiating element.

Abstract: A semiconductor device includes a first electrode which includes a first main portion, and a first extension that extends from the first main portion, and a dielectric layer which surrounds a sidewall and a bottom surface of the first main portion, wherein the first main portion includes a first portion having a first depth, and a second portion having a second depth deeper than the first depth.

Abstract: Implementations of semiconductor packages may include: a prefabricated electrically conductive section; two or more metal oxide semiconductor field effect transistors (MOSFET) physically coupled together; and a back metal coupled to the two or more MOSFETs; wherein the electrically conductive section may be coupled to the back metal and may be configured to electrically couple the two or more MOSFETs together during operation of the two or more MOSFETs.

Abstract: Quantum computing assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a quantum computing assembly may include a plurality of dies electrically coupled to a package substrate, and lateral interconnects between different dies of the plurality of dies, wherein the lateral interconnects include a superconductor, and at least one of the dies of the plurality of dies includes quantum processing circuitry.

Abstract: An integrated circuit structure includes a fuse. The integrated circuit structure further includes a first dielectric layer and a patterned dummy. The fuse is disposed on a substrate. The first dielectric layer covers the fuse. The patterned dummy is disposed on the first dielectric layer and the patterned dummy has a first recess exposing a part of the first dielectric layer directly above the fuse. A method of forming the integrated circuit structure including a fuse is also provided.

Abstract: Some embodiments include a NAND memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. Charge-trapping material is along the control gate regions of the wordline levels, and is spaced form the control gate regions by charge-blocking material. The charge-trapping material along vertically adjacent wordline levels is spaced by intervening regions through which charge migration is impeded. Channel material extends vertically along the stack and is spaced from the charge-trapping material by charge-tunneling material. Some embodiments include methods of forming NAND memory arrays.

Abstract: A semiconductor substrate includes a dielectric layer, a first patterned conductive layer and a first connection element. The dielectric layer has a first surface. The first patterned conductive layer has a first surface and is disposed adjacent to the first surface of the dielectric layer. The first connection element is disposed on the first surface of the first patterned conductive layer. The first connection element includes a first portion, a second portion and a seed layer disposed between the first portion and the second portion. The first portion of the first connection element and the first patterned conductive layer are formed to be a monolithic structure.

Abstract: A mechanical oscillating system for a clock including a balance spring manufactured from a non-metallic, polycrystalline material with a grain size between 10 and 50,000 nm, with a winding area of the balance spring 0.001 mm2 to 0.3 mm2, an oscillating body and a shaft for mounting of the oscillating body and the balance spring on the shaft. A spiral spring for a clock being manufactured from a non-metallic material, wherein the non-metallic material is a polycrystalline material with a grain size between 10 and 50,000 nm, and having a linear thermal expansion coefficient smaller than 8×10?6/K.

Abstract: Semiconductor packages and methods of forming the same are disclosed. The semiconductor package includes a plurality of chips, a first molding compound, a first redistribution structure, a second molding compound and a second redistribution structure. The first molding compound encapsulates the chips. The first redistribution structure is disposed over the plurality of chips and the first molding compound. The second molding compound surrounds the first molding compound. The second redistribution structure is disposed over the first redistribution structure, the first molding compound and the second molding compound.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a circuit region, a seal ring region and an assembly isolation region. The circuit region includes a first conductive layer. The seal ring region includes a second conductive layer. The assembly isolation region is between the circuit region and the seal ring region. The first conductive layer and the second conductive layer respectively include a portion extending into the assembly isolation region thereby forming an electric component in the assembly isolation region.

Abstract: In a step-down chopper circuit, a distance between a plurality of first mounting portions of a first semiconductor package that houses a switching device circuit and a distance between a plurality of second mounting portions of a second semiconductor package that houses a backflow prevention diode circuit are different from each other.

Abstract: A package-on-package stacked microelectronic structure comprising a pair of microelectronic packages attached to one another in a flipped configuration. In one embodiment, the package-on-package stacked microelectronic structure may comprise a first and a second microelectronic package, each comprising a substrate having at least one package connection bond pad formed on a first surface of each microelectronic package substrate, and each having at least one microelectronic device electrically connected to the each microelectronic package substrate first surface, wherein the first and the second microelectronic package are connected to one another with at least one package-to-package interconnection structure extending between the first microelectronic package connection bond pad and the second microelectronic package connection bond pad.

Abstract: A singulation assembly for molded leadframe sheets includes a saw chuck table having a flat upper surface with a plurality of holes therein. A vacuum source is in fluid communication with the plurality of holes. A mechanical clamping assembly operatively associated with the saw chuck table is adapted to be selectively engageable with predetermined portions of a warped molded leadframe sheet supported on the flat upper surface of the saw chuck table.

Abstract: An object is to provide a technique that can reduce the degradation in the characteristics of a transmitting filter by improving heat dissipation characteristics of a composite component having a stack structure. Since a transmitting filter is disposed in or on a first substrate 14, the heat generated in the transmitting filter is efficiently dissipated, for example, to an external module substrate 2 electrically connected to the first substrate 14. It is thus possible to reduce changes in the characteristics of the transmitting filter caused by a temperature rise. Thus, by improving heat dissipation characteristics of a composite component 10 having a stack structure, the degradation in the characteristics of the transmitting filter can be reduced.

Abstract: In a boost chopper circuit, a distance between a plurality of first mounting portions of a first semiconductor package that houses a switching device circuit and a distance between a plurality of second mounting portions of a second semiconductor package that houses a backflow prevention diode circuit are different from each other.

Abstract: A MEMS component includes, on a substrate, component structures, contact areas connected to the component structures, metallic column structures seated on the contact areas, and metallic frame structures surrounding the component structures. A cured resist layer is seated on frame structure and column structures such that a cavity is enclosed between substrate, frame structure and resist layer. A structured metallization is provided directly on the resist layer or on a carrier layer seated on the resist layer. The structured metallization includes at least external contacts of the component and being electrically conductively connected both to metallic structures and to the contact areas of the component structures.

Abstract: A semiconductor package includes a printed circuit board, a resistor circuit, and first and second semiconductor chips. First and second pads are on a first surface of the printed circuit board, and external connection terminal is on a second surface of the printed circuit board. The resistor circuit has a first connection terminal connected to the first pad and a second connection terminal connected to the second pad. The first semiconductor chip is connected to the first pad and the second semiconductor chip is stacked on the first semiconductor chip and connected to the second pad. The printed circuit board includes a signal transfer line connecting a branch in the printed circuit board to the external connection terminal. A first transfer line connects the branch to the first pad. A second transfer line connects the branch to the second pad.

Abstract: Embodiments include a synthetic jet device formed within layers of a package substrate, such as to provide a controlled airflow for sensing or cooling applications. The jet device includes an electromagnetically driven vibrating membrane of conductive material between a top and bottom cavity. A top lid with an opening covers the top cavity, and a permanent magnet is below the bottom cavity. An alternating current signal conducted through the membrane causes the membrane to vibrate in the presence of a magnetic field caused by the permanent magnet. By being manufactured with package forming processes, the jet (1) is manufactured more cost-effectively than by using silicon chip or wafer processing; (2) is easily integrated as part of and with the other layers of a package substrate; and (3) can be driven by a chip mounted on the package. Embodiments also include systems having and processes for forming the jet.

Abstract: A semiconductor device including: a semiconductor substrate; a first coil formed on the semiconductor substrate via a first insulation film; a second insulation film formed on the semiconductor substrate so as to cover the first insulation film and the first coil; a first pad formed on the second insulation film and disposed at a position not overlapped with the first coil in a planar view; a laminated insulation film formed on the second insulation film, the laminated insulation film having a first opening from which the first pad is exposed; a second coil formed on the laminated insulation film and disposed above the first coil; and a first wiring formed on the laminated insulation film including an upper portion of the first pad exposed from the first opening, the first wiring being electrically connected to the first pad.

Abstract: Embodiments include a synthetic jet device formed within layers of a package substrate, such as to provide a controlled airflow for sensing or cooling applications. The jet device includes an electromagnetically driven vibrating membrane of conductive material between a top and bottom cavity. A top lid with an opening covers the top cavity, and a permanent magnet is below the bottom cavity. An alternating current signal conducted through the membrane causes the membrane to vibrate in the presence of a magnetic field caused by the permanent magnet. By being manufactured with package forming processes, the jet (1) is manufactured more cost-effectively than by using silicon chip or wafer processing; (2) is easily integrated as part of and with the other layers of a package substrate; and (3) can be driven by a chip mounted on the package. Embodiments also include systems having and processes for forming the jet.

Abstract: The present invention relates to an integrated circuit package comprising at least one substrate, each substrate including at least one layer, at least one semiconductor die, at least one terminal, and an antenna located in the integrated circuit package, but not on said at least one semiconductor die. The conducting pattern comprises a curve having at least five sections or segments, at least three of the sections or segments being shorter than one-tenth of the longest free-space operating wavelength of the antenna, each of the five sections or segments forming a pair of angles with each adjacent segment or section, wherein the smaller angle of each of the four pairs of angles between sections or segments is less than 180° (i.e.

Abstract: A power amplifier (PA) cell is coupled to an input signal source, and includes a transistor coupled to the load; a first inductor coupled to a gate of the transistor; and a second inductor coupled to a source of the transistor, wherein the first inductor and the second inductor each includes a first conductive coil and a second conductive coil, respectively, having first and second inductance values, respectively, such that the PA cell includes a terminal between the gate of the transistor and the input signal source, and the terminal is impedance matched with the input signal source.

Abstract: Light emitting diode (LED) packages and methods are disclosed herein. In one aspect, a light emitting package is disclosed. The light emitting package includes one or more areas of conductive material having a thickness of less than approximately 50 microns (?m). The package can further include at least one light emitting diode (LED) electrically connected to the conductive material and at least one thin gap disposed between areas of conductive material.

Abstract: A method for fabricating a semiconductor memory device is provided. The method includes: etching a first region of the semiconductor memory device to expose a first capping layer; forming a second capping layer on the first capping layer; etching a portion of the first capping layer and a portion of the second capping layer to form a first trench reaching a first metal line; and forming a second metal line in the first trench to contact the first metal line.

Abstract: A system module includes a printed circuit board (PCB), a first semiconductor chip embedded in the PCB, a semiconductor package connected to the PCB through a plurality of stack balls, and a second semiconductor chip disposed on a surface of the PCB in a space between the PCB and the semiconductor package.

Abstract: Field-effect transistor (FET) devices are described herein that include an insulator layer, a field-effect transistor implemented over the insulator layer, a substrate layer implemented under the insulator layer, and a proximity electrode that extends at least partially through the insulator layer and positioned from the FET by a distance that is less than about 5 ?m. The FET device can include one or more substrate contact features as well.

Abstract: Vertical meander inductors for small core voltage regulators and approaches to fabricating vertical meander inductors for small core voltage regulators are described. For example, a semiconductor die includes a substrate. An integrated circuit is disposed on an active surface of the substrate. An inductor is coupled to the integrated circuit. The inductor is disposed conformal with an insulating layer disposed on an essentially planar surface of the substrate. The insulating layer has an undulating topography.