Abstract: Technologies are generally described for switchable patterned metal shield inductance structures. In some examples, an inductance structure on a substrate may include an inductor and a metal shield, where the metal shield separates and shields the inductor from the substrate. The configuration of the metal shield and the inductor may facilitate reduction in the overall inductance of the inductance structure. In particular, the metal shield may be configured to develop one or more eddy currents in response to an inductor-generated magnetic field. The eddy currents may then result in a magnetic field opposing the inductor-generated magnetic field, which may result in a reduction in the overall magnetic field and the overall inductance of the inductance structure. The metal shield may be switchable between multiple modes, where each mode may be effective to reduce the overall inductance by a different amount.

Abstract: An integrated circuit (IC) die may include a substrate layer and an inductor with an associated capacitance formed on one of multiple metal layers above the substrate layer. Power shielding strips may be formed between the inductor and the substrate layer. Portions of the power shielding strips may be selectively activated to adjust the capacitance of the inductor. As an example, switches may be coupled to the power shielding strips to selectively couple a portion of the power shielding strips to a ground voltage to increase the capacitance of the inductor. As another example, a fuse element may be used to selectively activate desired portions of the power shielding strips.

Abstract: A semiconductor device including a first insulating layer and a second insulating layer sequentially disposed on a substrate having a center region. The semiconductor device includes a first winding portion and a second winding portion disposed in the second insulating layer and surrounding the center region A second conductive line and a third conductive line are arranged from the inside to the outside. In addition, each of the first, second and third conductive lines has a first end and a second end. The semiconductor device also includes a coupling portion disposed in the first and second insulating layers between the first and second winding portions, and having a first pair of connection layers cross-connecting the second ends of the first and second conductive lines, and a second pair of connection layers cross-connecting the first ends of the second and third conductive lines.

Abstract: Consistent with an example embodiment, a System on Chip (SoC) device operates in millimeter wave frequencies. The SoC device comprises, a silicon device having at least one differential pair pad, the at least one differential pair pad having a shunt inductor coupled thereon. A parasitic capacitance on at least one differential pair pads is tuned out by resonance of the shunt inductor. A package has a redistribution layer (RDL), with an array of contact areas to which the silicon device is mounted and then encapsulated. A connection corresponds to the at least one differential pair pad and the connection is located about an outer row or column of the array of contact areas.

Abstract: An inductive device is formed in a circuit structure that includes alternating conductive and insulating layers. The device includes, in a plurality of the conductive layers, traces forming a respective pair of interleaved loops and at least one interconnect segment in each of the plurality of the conductive layers. In each layer among the plurality of the conductive layers, at least one loop in the respective pair is closed by jumpers to an interconnect segment formed in another layer above or below the layer.

Abstract: A semiconductor device includes a plurality of first inductors having a spiral shape and provided in a modulator of a transmitting side, and a plurality of second inductors having a horseshoe shape and provided in an oscillator of a receiving side, the plurality of second inductors being arranged such that an opening of plurality of second inductors is disposed opposite to the plurality of first inductors. The semiconductor device performs a transmission process and a reception process using a radio wave.

Abstract: A method including forming a first metal wire in a first dielectric layer, the first metal wire including a first vertical side opposite from a second vertical side; and forming a second metal wire in a second dielectric layer above the first dielectric layer, the second metal wire including a third vertical side opposite from a fourth vertical side, where the first vertical side is laterally offset from the third vertical side by a first predetermined distance, and the second vertical side is laterally offset from the fourth vertical side by a second predetermined distance, where the first metal wire and the second metal wire are in direct contact with one another.

Abstract: A parallel stacked multipath inductor includes a first layer including turns disposed about a center region, the turns on the first layer having segments that extend length-wise along the turns, the segments having positions that vary from an innermost position relative to the center region and an outermost position relative to the center region. A second layer includes turns electrically connected to the first layer along its length and disposed about the center region, the turns on the second layer having segments that extend length-wise along the turns, the segments having positions that vary from an innermost position and an outermost position relative to the center region. Cross-over architectures are configured to couple the segments on the first layer with the segments on the second layer to form segment paths that have a substantially same length for all segment paths per turn between the first and second layers.

Abstract: An inductor includes a first coil, an input terminal electrically connected to an outermost portion of the first coil, a first insulating film on the first coil, a second coil on the first insulating film, a second insulating film on the second coil, a third coil on the second insulating film, connection conductors that connect the first coil to the second coil at locations so that a signal propagates through outside portions of the first coil and the second coil before propagating through other portions of the first coil and the second coil, a central portion connection conductor that connects a central portion of the first coil or a central portion of the second coil to a central portion of the third coil, and an output terminal electrically connected to an outermost portion of the third coil.

Abstract: An improvement is achieved in the reliability of a semiconductor device by preventing a dielectric breakdown between two semiconductor chips facing each other. During the manufacturing of first and second semiconductor chips, the process of planarizing the upper surfaces of insulating films is performed. Then, the first and second semiconductor chips are stacked via an insulating sheet with the respective insulating films of the first and second semiconductor chips facing each other such that the respective coils of the first and second semiconductor chips are magnetically coupled to each other.

Abstract: A device includes a substrate, and a vertical inductor over the substrate. The vertical inductor includes a plurality of parts formed of metal, wherein each of the parts extends in one of a plurality of planes perpendicular to a major surface of the substrate. Metal lines interconnect neighboring ones of the plurality of parts of the vertical inductor.

Abstract: In accordance with an embodiment, a semiconductor component and a method for manufacturing a semiconductor component are provided. A first dielectric material is formed over a body of semiconductor material of the first conductivity type and a plurality of semiconductor fingers are formed over the first of dielectric material. Semiconductor fingers of the plurality of semiconductor fingers spaced apart from each other and at least one of the semiconductor fingers has a first end spaced apart from a second end by a central region. A second dielectric material is formed over central region of the at least one semiconductor finger of the plurality of semiconductor fingers. An electrically conductive material is formed over the second dielectric material that is over the central region of the at least one semiconductor finger. The electrically conductive material serves as a shielding structure and the semiconductor material may be coupled to a fixed potential.

Abstract: A magnetic field measuring device having a first semiconductor body having a surface formed in a first x-y plane, the first semiconductor body having on the surface two magnetic field sensors which are spaced apart and arranged along a first connecting line, and wherein the magnetic field sensors respectively measure a z-component of a magnetic field, and the x-direction and the y-direction and the z-direction are each formed orthogonally to each other. A first magnet is provided with a planar main extension surface formed in a second x-y plane and with a symmetry surface formed in an x-z plane, wherein the direction of magnetization extends substantially or exactly parallel to the main extension surface and substantially or exactly parallel to the plane of symmetry. The first semiconductor body and the first magnet are rigidly fixed to each other.

Abstract: Integrated MEMS-CMOS devices and methods for fabricating MEMS devices and CMOS devices are provided. An exemplary method for fabricating a MEMS device and a CMOS device includes forming the CMOS device in and/or over a first side of a semiconductor substrate. Further, the method includes forming the MEMS device in and/or under a second side of the semiconductor substrate. The second side of the semiconductor substrate is opposite the first side of the semiconductor substrate.

Abstract: A method for manufacturing a digital circuit is described including forming a plurality of field effect transistor pairs, connecting the field effect transistors of the field effect transistor pairs such that in response to a first transition from a first state of two nodes of the digital circuit and in response to a second transition from a second state of the nodes of the digital circuit the nodes each have an undefined logic state when, for each field effect transistor pair, the threshold voltages of the field effect transistors of the field effect transistor pair are equal and setting the threshold voltages of the field effect transistors of the field effect transistor pairs such that the nodes each have a predetermined defined logic state in response to the first transition and in response to the second transition.

Abstract: The three dimensional (3D) circuit includes a first tier including a semiconductor substrate, a second tier disposed adjacent to the first tier, a three dimensional inductor including an inductive element portion, the inductive element portion including a conductive via extending from the first tier to a dielectric layer of the second tier. The 3D circuit includes a ground shield surrounding at least a portion of the conductive via. In some embodiments, the ground shield includes a hollow cylindrical cage. In some embodiments, the 3D circuit is a low noise amplifier.

Abstract: An electrostatic discharge (ESD) protection circuit includes a first inductor coupled to an input node configured to receive an input signal and to an output node. A second inductor is coupled to the input node and to a first ESD protection device, and a third inductor is coupled to the output node and to a second ESD protection device.

Abstract: Wiring structures, methods for providing a wiring structure, and methods for distributing currents with a wiring structure from one or more through-substrate vias to multiple bumps. A first current is directed from a first through-substrate via of a first electrical resistance through a first connection line to a first bump and directing a second current from the first through-substrate via through a second connection line of a second electrical resistance to a second bump. The first connection line has a first length relative to a first position of the first bump and a first cross-sectional area, the second connection line has a second length relative to a first position of the second bump and a second cross-sectional area, the second length is different from the first length, and the second cross-sectional area is different from the first cross-sectional area.

Abstract: An integrated device package includes a die and a package substrate. The package substrate includes at least one dielectric layer (e.g., core layer, prepeg layer), a magnetic core in the dielectric layer, a first plurality of interconnects configured to operate as a first protective ring, and a second plurality of interconnects configured to operate as a first inductor. The second plurality of interconnects is positioned in the package substrate to at least partially surround the magnetic core. At least one interconnect from the second plurality of interconnects is also part of the first plurality of interconnects. In some implementations, the first protective ring is a non-contiguous protective ring. In some implementations, the first inductor is a solenoid inductor. In some implementations, the magnetic core includes a carrier, a first magnetic layer, and a second magnetic layer.

Abstract: According to various embodiments, a miniature passive structure for electrostatic discharge protection and input/output matching for a high frequency integrated circuit may be provided. The structure may include: either a transmission line or an inductor for providing at least one electrostatic discharge path; and a capacitor with a first end connected to the transmission line or inductor and a second end connected to ground.

Abstract: A printed wiring board includes a first core substrate having an opening portion, an inductor component accommodated in the opening portion of the first core substrate, a first buildup layer formed on a first surface of the first core substrate and the inductor component, and a second buildup layer formed on a second surface of the first core substrate and the inductor component on the opposite side with respect to the first surface of the first core substrate. The inductor component has a second core substrate, a buildup layer formed on a surface of the second core substrate and a coil layer formed on the buildup layer, and the second buildup layer has a coil layer and a via conductor connecting the coil layer in the second buildup layer and the coil layer formed on the buildup layer in the inductor component.

Abstract: A varainductor includes a spiral inductor over a substrate, the spiral inductor comprising a ring portion. The varainductor further includes a ground ring over the substrate, the ground ring surrounding at least the ring portion of the spiral inductor and a floating ring over the substrate, the floating ring disposed between the ground ring and the spiral inductor. The varainductor further includes an array of switches, the array of switches is configured to selectively connect the ground ring to the floating ring.

Abstract: A circuit substrate includes: an insulative substrate formed with a pattern of a recess, the recess being defined by a recess-defining wall that has a bottom wall surface and a surrounding wall surface extending upwardly from the bottom wall surface; a patterned metallic layer structure including at least a patterned active metal layer disposed within the recess, formed on the bottom wall surface of the recess-defining wall, and spaced apart from the surrounding wall surface of the recess-defining wall, the patterned active metal layer containing an active metal capable of initiating electroless plating; and a primary metal layer plated on the patterned metallic layer structure.

Abstract: Systems and methods relate to a semiconductor package comprising a first substrate or a 2D passive-on-glass (POG) structure with a passive component and a first set of one or more package pads formed on a face of a glass substrate. The semiconductor package also includes a second or laminate substrate with a second set of one or more package pads formed on a face of the second or laminate substrate. Solder balls are dropped, configured to contact the first set of one or more package pads with the second set of one or more package pads, wherein the first substrate or the 2D POG structure is placed face-up on the face of the second or laminate substrate. A printed circuit board (PCB) can be coupled to a bottom side of the second or laminate substrate.

Abstract: A wireless transceiver includes a semiconductor device configured to perform a transmission process and a reception process using a radio wave, the semiconductor device including a transmission unit and a reception unit. The wireless transceiver further includes an antenna configured to transmit an output signal from the transmission unit and provide a received input signal to the reception unit, and a baseband circuit configured to receive an output signal from the reception unit and output the output signal to the transmission unit.

Abstract: A light-emitting element, comprises: a substrate; a light-emitting stack formed on the substrate, comprising a first semiconductor layer having a first surface facing the substrate, a second semiconductor layer having a second surface opposite the first surface, and an active layer between the first semiconductor layer and the second semiconductor layer; an insulating adhesive layer formed between the light-emitting stack and the substrate; and an inductive coil embedded in the insulating adhesive layer, comprising a first end electrically connecting the first semiconductor layer, and a second end electrically connecting the second semiconductor layer.

Abstract: There is described a dual-band semiconductor RF amplifier device. The device comprises (a) a transistor (205) having an output capacitance (CO), (b) a first shunt element (210) arranged in parallel with the output capacitance, the first shunt element comprising a first shunt inductor (L1) connected in series with a first shunt capacitor (C1), and (c) a second shunt element (220) arranged in parallel with the first shunt capacitor, the second shunt element comprising a second shunt inductor (L2) connected in series with a second shunt capacitor (C2), wherein the capacitance of the second shunt capacitor (C2) is at least two times the capacitance of the first shunt capacitor (C1). Furthermore, there is described a method of manufacturing a dual-band semiconductor RF amplifier device and a dual-band RF amplifier comprising a plurality of such amplifier devices.

Abstract: A multilayer electronic support structure comprising at least one pair of adjacent feature layers extending in an X-Y plane that are separated by a via layer; said via layer comprising a dielectric material that is sandwiched between the two adjacent feature layers and at least one one non-cylindrical via post that couples said pair of adjacent feature layers through the dielectric material in a Z direction perpendicular to the X-Y plane; wherein said at least one non-cylindrical via post is characterized by having a long dimension in the X-Y plane that is at least 3 times as long as a short dimension in the X-Y plane.

Abstract: A transformer structure includes a first coil having two sections of spiral, with a top section including a plurality of metal layers occupying top X metal layers and a bottom section including a plurality of metal layers occupying bottom Z metal layers, where X and Z represent a number of metal layers having a specific number selected to provide a particular performance of the first coil. A second coil of the transformer is disposed between the two sections of the first coil and includes a plurality of metal layers where Y represents a number of vertically adjacent metal layers, with the specific number chosen to provide the particular performance, such that a sum X+Y+Z represents a total number of vertical metal layers for the transformer structure.

Abstract: Some novel features pertain to an integrated device package that includes a die, an electromagnetic (EM) passive device, an encapsulation layer covering the die and the EM passive device, and a redistribution portion coupling the die and the EM passive device. In some implementations, the EM passive device includes an electromagnetic (EM) passive device. The EM passive device includes a base layer, a via traversing the base layer, a pad coupled to the via, and at least redistribution layer configured to operate as electromagnetic (EM) passive component, where the redistribution layer is coupled to the pad. The redistribution portion of the EM passive device includes at least one redistribution layer that is configured to electrically couple the die to the EM passive device. The redistribution portion includes at least one redistribution layer that is configured as an electromagnetic (EM) shield.

Abstract: The present disclosure involves a semiconductor device. The semiconductor device includes a substrate; a capacitor disposed over the substrate; an inductor disposed over the substrate and having a coil feature surrounding the capacitor; and a shielding structure over the substrate and configured around the coil feature.

Abstract: According to an exemplary embodiment, a semiconductor device is provided. The semiconductor device includes a first seal ring and a first circuit. The first circuit includes a first capacitor and a first inductor connected in series. The first circuit is connected between the first seal ring and a ground.

Abstract: A system and method for providing and manufacturing an inductor is provided. In an embodiment similar masks are reutilized to form differently sized inductors. For example, a two turn inductor and a three turn inductor may share masks for interconnects and coils, while only masks necessary for connections between the interconnects and coils may need to be newly developed.

Abstract: A RF power amplifier module comprises a die with a RF power transistor and the RF power transistor comprises a control terminal, a transistor output terminal and a transistor reference terminal. The RF power amplifier module further comprises a module input terminal, a module output terminal and at least two module reference terminals being electrically coupled to the control terminal, the transistor output terminal and the transistor reference terminal, respectively. The RF power amplifier module further comprises an electrically isolating layer and a heat conducting element. The die is in thermal contact with the heat conducting element via the electrically isolating layer in order to transfer heat during operation of the RF power transistor to the heat conducting element.

Abstract: In accordance with an embodiment, a semiconductor device comprises a semiconductor die, an interposer, and conductive bumps bonding the semiconductor die to the interposer. The semiconductor die comprises a first metallization layer, and the first metallization layer comprises a first conductive pattern. The interposer comprises a second metallization layer, and the second metallization layer comprises a second conductive pattern. Some of the conductive bumps electrically couple the first conductive pattern to the second conductive pattern to form a coil. Other embodiments contemplate other configurations of coils, inductors, and/or transformers, and contemplate methods of manufacture.

Abstract: An inductor assembly generally comprises at least one helical inductive component comprising that includes a plurality of conductive line layers having conductive lines therein. A plurality of vias are configured to couple conductive lines from two or more conductive line layers such that a spacing between two adjacent parallel conductive lines, in different conductive line layers from each other, is two or more times a distance between respective bottom surfaces of two adjacent conductive line layers.

Abstract: Base pads are spaced by a pitch on a support surface. Conducting members, optionally Cu or other metal pillars, extend up from the base pads to top pads. A top pad interconnector connects the top pads in a configuration establishing an inductor current path between the base pads.

Abstract: A semiconductor device has a first semiconductor die. A first inductor is formed over the first semiconductor die. A second inductor is formed over the first inductor and aligned with the first inductor. An insulating layer is formed over the first semiconductor die and the first and second inductors. A conductive bridge is formed over the insulating layer and electrically connected between the second inductor and the first semiconductor die. In one embodiment, the semiconductor device has a second semiconductor die and a conductive layer is formed between the first and second semiconductor die. In another embodiment, a capacitor is formed over the first semiconductor die. In another embodiment, the insulating layer has a first thickness over a footprint of the first semiconductor die and a second thickness less than the first thickness outside the footprint of the first semiconductor die.

Abstract: A substrate with a silicon carbide film includes a Si substrate, and a SiC film and a mask stacked on the Si substrate. The SiC film has a first SiC film provided on the upper side of the Si substrate and a second SiC film provided on the upper side of the first SiC film. The mask has a first mask provided on the Si substrate and including an opening (first opening) and a second mask provided on the first SiC film and including an opening (second opening). The width W1 (?m) of the first opening and the thickness T1 (?m) of the first mask satisfy the following relationship: T1<tan(54.6°)×W1.

Abstract: An inductor includes a plurality of first conductive lines, a plurality of second conductive lines and a plurality of contacts. Each of the first conductive lines is spaced apart from one another. Each of the second conductive lines is spaced apart from one another, and each of the second conductive lines crosses over each of the first conductive lines. Each of the contacts electrically interconnects one of the first conductive lines and one of the second conductive lines. These contacts are arranged in a way such that at least parts of the first conductive lines and at least parts of the second conductive lines form an electric current path serving as an inductor.

Abstract: A structure (100) includes ground conductive bodies (111 and 141) that are formed in an A layer (110) and a D layer (140) that face each other, a connection member (151) that connects between the ground conductive bodies (111 and 141), a conductive part (131) that is formed in a C layer (130) and faces the ground conductive bodies (111 and 141), and an opening (132), through which the connection member (151) passes through, disposed in the conductive part (131), and a conductive element (121) that is formed in a B layer (120), faces the conductive part (131), and is electrically connected to the connection member (151) that passes through an opening (132) disposed in the conductive part (131).

Abstract: A coupled inductor topology for a thin-film magnetic core power inductor that enables efficient integrated power conversion. Coupled magnetic core inductors with interleaved windings inductors comprise magnetic films and partially or fully interleaved conductors. Methods described herein are suitable for integration into monolithic, chip stacking fabrication or other traditional semiconductor device fabrication techniques and equipment. Soft ferromagnetic materials exhibiting high permeability and low coercivity are deposited using thin-film techniques. A plurality of electrical conductors surround at least one ferromagnetic core giving rise to two or more windings. Windings are coupled to one another through magnetic core(s). Windings are used to control permeability, inductance and magnetic saturation, finding particular utility in high magnetic flux applications.

Abstract: A semiconductor device includes a substrate, a first trough structure and a second trough structure. The first trough structure which is in the substrate includes a first conductive layer, a first doping layer and a first insulation layer, which is placed between the first conductive layer and the first doping layer. The second trough structure which is in the substrate and separated from the first trough structure by a separation part of the substrate includes a second conductive layer and a second insulation layer. A first contact connects the first doping layer, a second contact connects the separation part, and a third contact connects the second conductive layer. The separation part forms a resistor, coupled between the first contact and the second contact, and the substrate, the second insulation layer and the second conductive layer together form a capacitor, coupled between the second contact and the third contact.

Abstract: Provided is a time division duplex (TDD) transceiver. A receiver chain processing received signals and a transmitter chain processing signals to be transmitted share an electronic component used in a circuit, such as an amplifier, a mixer, a filter, etc., so that the size of a semiconductor die needed to manufacture a radio frequency (RF) chip can be reduced.

Abstract: Some novel features pertain to an integrated device that includes a substrate, a first cavity through the substrate, and a toroid inductor configured around the first cavity of the substrate. The toroid inductor includes a set of windings configured around the first cavity. The set of windings includes a first set of interconnects on a first surface of the substrate, a set of though substrate vias (TSVs), and a second set of interconnects on a second surface of the substrate. The first set of interconnects is coupled to the second set of interconnects through the set TSVs. In some implementations, the integrated device further includes an interconnect material (e.g., solder ball) located within the first cavity. The interconnect material is configured to couple a die to a printed circuit board. In some implementations, the interconnect material is part of the toroid inductor.

Abstract: A semiconductor device is configured to perform a transmission process and a reception process using a radio wave, includes a transmission unit configured to perform the transmission process, and includes a modulator having a first inductor of a spiral shape, and a reception unit configured to perform the reception process, which includes a local oscillator having a second inductor. The second inductor includes a first portion extending in a first direction, a second portion extending in a second direction and a third portion extending in a third direction. The second direction and the third direction intersect with the first direction. The first portion, second portion and third portion include a same conductor layer. The second portion has an end which is not connected with the first portion. The third portion has another end which is not connected with the first portion, and the end of the second portion and said another end of the third portion are located apart in a plan view.

Abstract: An inductor may be formed from a conductive path that includes intertwined conductive lines. There may be two, three, or more than three intertwined conductive lines in the conductive path. The conductive lines may be formed from conductive structures in the dielectric stack of an integrated circuit. The dielectric stack may include metal layers that include conductive traces and may include via layers that include vias for interconnecting the traces. The intertwined conductive lines may be formed from the conductive structures in the metal and via layers. In crossover regions, the conductive lines may cross each other without electrically connecting to each other. Vias may be used to couple multiple layers of traces together to reduce line resistance.

Abstract: A semiconductor device includes a semiconductor substrate, a first wiring layer including a plurality of first dummy metals provided inside an inductor wiring, a plurality of second dummy metals provided outside the inductor wiring, and a plurality of third dummy metals provided to overlap the inductor wiring in a plan view, and a second wiring layer provided between the semiconductor substrate and the first wiring layer. The second wiring layer includes the inductor wiring formed in the second wiring layer, a first region surrounding the inductor wiring which includes a plurality of fourth dummy metals, and a second region surrounding the first region which includes a plurality of fifth dummy metals. A density of the fourth dummy metals is lower than a density of the fifth dummy metals.

Abstract: The present invention provides an integrated inductor and an integrated inductor fabricating method. The integrated inductor comprises: a semiconductor substrate, a plurality of deep trenches, and an inductor. The deep trenches are formed in the semiconductor substrate and arranged in a specific pattern, and the deep trenches are filled with a metal material to form a patterned ground shield (PGS). The inductor is formed above the semiconductor substrate. The integrated inductor fabricating method comprises: forming a semiconductor substrate; forming a plurality of deep trenches in the semiconductor substrate and arranging the deep trenches in a specific pattern; filling the deep trenches with a metal material to form a patterned ground shield (PGS); and forming an inductor above the semiconductor substrate.

Abstract: Disclosed herein is a common mode filter including: a body element including an insulating member enclosing a coil electrode pattern and a magnetic member disposed on one surface or both surfaces of the insulating member; and an insulating layer disposed on at least one side of the body element, thereby increasing an interlayer adhesion between the respective components configuring the common mode filter.