Abstract: An inductor structure includes a substrate, a protection layer, a patterned first conductive layer, copper bumps, a passivation layer, a diffusion barrier layer, and an oxidation barrier layer. The protection layer is located on the substrate. The bond pads of the substrate are respectively exposed through protection layer openings. The first conductive layer is located on the surfaces of the bond pads and the protection layer adjacent to the protection layer openings. The copper bumps are located on the first conductive layer. The passivation layer is located on the protection layer and the copper bumps. At least one of the copper bumps is exposed through a passivation layer opening. The diffusion barrier layer is located on the copper bump that is exposed through the passivation layer opening. The oxidation barrier layer is located on the diffusion barrier layer.

Abstract: The present invention discloses an electronic package structure. The body has a top surface with a cavity thereon, the first conductive element is disposed in the cavity, and the second conductive element is disposed in the body. The first external electrode electrically connected to the first conductive element and the second external electrode electrically connected to the second conductive element are both disposed on the top surface of the body or a first surface formed by the top surface of the encapsulation compound and the exposed portions of the top surface of the body which are not covered by the encapsulation compound.

Abstract: A patterned ground shield structure is provided. The patterned ground shield structure includes a substrate having a dielectric layer. The patterned ground shield structure also includes a plurality of conductive rings having a plurality of sub conductive rings in the dielectric layer. Further, the patterned ground shield structure includes an interconnection line connecting with all of the sub conductive rings in the dielectric layer. Further, the patterned ground shield structure also includes a ground ring connecting with the interconnection line.

Abstract: The three dimensional (3D) circuit includes a first tier including a semiconductor substrate, a second tier disposed adjacent to the first tier, a three dimensional inductor including an inductive element portion, the inductive element portion including a conductive via extending from the first tier to a dielectric layer of the second tier. The 3D circuit includes a ground shield surrounding at least a portion of the conductive via. In some embodiments, the ground shield includes a hollow cylindrical cage. In some embodiments, the 3D circuit is a low noise amplifier.

Abstract: Various embodiments provide ground shield structures, semiconductor devices, and methods for forming the same. An exemplary structure can include a substrate and a dielectric layer disposed on the substrate. The structure can further include multiple conductive rings disposed in the substrate, in the dielectric layer, and/or on the dielectric layer. Each conductive ring of the multiple conductive rings can have openings of about three or more, and the openings of the each conductive ring can divide the multiple conductive rings into a plurality of sub-conductive rings arranged spaced apart. The structure can further a ground ring electrically connected to each of the plurality of sub-conductive rings.

Abstract: Characteristics of a semiconductor device are improved. A semiconductor device has a laminated insulating film formed above a lower-layer inductor. This laminated insulating film includes a first polyimide film, and a second polyimide film formed on the first polyimide film and having a second step between the first polyimide film and the second polyimide film. An upper-layer inductor is formed on the laminated insulating film. Since such a laminated structure of the first and second polyimide films is adopted, the film thickness of the insulating film between the lower-layer and upper-layer inductors can be increased, so that withstand voltage can be improved. Further, the occurrence of a depression or peeling-off due to defective exposure can be reduced, and step disconnection of a Cu (copper) seed layer or a plating defect due to the step disconnection can also be reduced.

Abstract: A common mode filter includes a first coil, a second coil, a first insulating layer separating the first coil from the second coil, a third coil serially connected with the first coil, a second insulating layer separating the second coil from the third coil, a fourth coil serially connected with the second coil, and a third insulating layer separating the third coil from the fourth coil. The second coil is between the first and third coils, and the third coil is between the second and fourth coils. At least one of the first insulating layer, the second insulating layer and the third insulating layer may include magnetic material.

Abstract: There are provided a non-magnetic composition for a ceramic electronic component, a ceramic electronic component manufactured by using the same, and a manufacturing method thereof. The non-magnetic composition for a ceramic electronic component includes a compound represented by ZnCuTiO4 such that the inductance decreasing rate at the high current and the capacitance rate of change of the magnetic body after the application of current according to the temperature change are insensitive, whereby the stable operational characteristics of the ceramic electronic component may be secured.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a first inductor formed on a first substrate; a second inductor formed on a second substrate and conductively coupled with the first inductor as a transformer; and a plurality of micro-bump features configured between the first and second substrates. The plurality of micro-bump features include a magnetic material having a relative permeability substantially greater than one and are configured to enhance coupling between the first and second inductors.

Abstract: A semiconductor package is provided that has a transformer formed within a multilayer dielectric laminate substrate. The transformer has a first inductor coil formed in one or more dielectric laminate layers of the substrate, a second inductor coil formed in one or more dielectric laminate layers of the substrate, and an isolation barrier comprising two or more dielectric laminate layers of the multilayer substrate positioned between the first inductor coil and the second inductor coil. The transformer may be mounted on a lead frame along with one or more integrated circuits and molded into a packaged isolation device.

Abstract: In one embodiment, a method of forming a semiconductor device includes forming a first inductor coil within and/or over a substrate. The first inductor coil is formed adjacent a top side of the substrate. First trenches are formed within the substrate adjacent the first inductor coil. The first trenches are filled at least partially with a magnetic fill material. At least a first portion of the substrate underlying the first inductor coil is thinned. A backside magnetic layer is formed under the first portion of the substrate. The backside magnetic layer and the magnetic fill material form at least a part of a magnetic core region of the first inductor coil.

Abstract: A bias circuit according to the present invention includes a resistor layer 2 which is placed above a substrate 1 and connected to a ground potential, and a conductor 4 for forming an inductor 5 placed above the resistor layer 2. Further, a manufacturing method of the bias circuit according to the present invention generates the resistor layer 2 above the substrate 1 and is connected to the ground potential, and generates the conductor 4 for forming the inductor 5 above the resistor layer 2. The present invention can provide a bias circuit and a manufacturing method of the bias circuit that enables easy integration on a semiconductor substrate and prevents parasitic oscillation.

Abstract: A signal transmission arrangement is disclosed. A voltage converter includes a signal transmission arrangement.

Abstract: This disclosure provides systems, methods and apparatus for combining devices deposited on a first substrate, with integrated circuits formed on a second substrate such as a semiconducting substrate or a glass substrate. The first substrate may be a glass substrate. The first substrate may include conductive vias. A power combiner circuit may be deposited on a first side of the first substrate. The power combiner circuit may include passive devices deposited on at least the first side of the first substrate. The integrated circuit may include a power amplifier circuit disposed on and configured for electrical connection with the power combiner circuit, to form a power amplification system. The conductive vias may include thermal vias configured for conducting heat from the power amplification system and/or interconnect vias configured for electrical connection between the power amplification system and a conductor on a second side of the first substrate.

Abstract: A structure includes a metal feature, and a passivation layer having a portion overlapping the metal feature. The passivation layer includes a non-low-k dielectric material. A polymer layer is over the passivation layer. A Post-Passivation Interconnect (PPI) extends into the polymer layer to electrically couple to the metal feature. A guard ring includes a second PPI, wherein the guard ring is electrically grounded. The second PPI substantially encircles the first PPI.

Abstract: Various embodiments provide a chip. The chip has a carrier, an integrated circuit formed above the carrier, and an energy storage element. The energy storage element has a first electrode and a second electrode and is used to supply the integrated circuit with electrical energy. The carrier, the integrated circuit and the energy storage element are monolithically formed, the first electrode being formed from the carrier.

Abstract: A manufacturing method of an inductor structure includes the following steps. A protection layer is formed on a substrate, such that bond pads of the substrate are respectively exposed form protection layer openings of the protection layer. A conductive layer is formed on the bond pads and the protection layer. A patterned first photoresist layer is formed on the conductive layer. Copper bumps are respectively formed on the conductive layer located in the first photoresist layer openings. A patterned second photoresist layer is formed on the first photoresist layer, such that at least one of the copper bumps is exposed through second photoresist layer opening and the corresponding first photoresist layer opening. A diffusion barrier layer and an oxidation barrier layer are formed on the copper bump. The first and second photoresist layers, and the conductive layer not covered by the copper bumps are removed.

Abstract: Provided is a semiconductor device including, on the same semiconductor substrate, a transistor element, a capacitor, and a resistor. The capacitor is formed on an active region, and the resistor is formed on an element isolation region, both formed of the same polysilicon film. By CMP or etch-back, the surface is ground down while planarizing the surface until a resistor has a desired thickness. Owing to a difference in height between the active region and the element isolation region, a thin resistor and a thick upper electrode of the capacitor are formed to prevent passing through of a contact.

Abstract: A semiconductor structure with a high voltage area and a low voltage area includes a substrate of a first conductivity type accommodating the high voltage area and the low voltage area. A resistor is on the substrate, connecting the high voltage area and the low voltage area, and the resistor resides substantially in the high voltage area. The structure further includes a first doped region of the first conductivity type in the substrate between the high voltage area and the low voltage area, and a second doped region of a second conductivity type between the substrate and the first doped region. Moreover, an insulating layer is formed between the resistor and the first doped region.

Abstract: A semiconductor device includes a semiconductor substrate having a first main surface in which a recess is formed. Further, the semiconductor device includes an electrical interconnect structure which is arranged at a bottom of the recess. A semiconductor chip is located in the recess. The semiconductor chip includes a plurality of chip electrodes facing the electrical interconnect structure. Further, a plurality of electrically conducting elements is arranged in the electrical interconnect structure and electrically connected to the plurality of chip electrodes.

Abstract: To suppress the noise caused by an inductor leaks to the outside, and also to be configured such that magnetic field intensity change reaches the inductor. An inductor surrounds an internal circuit in a planar view and also is coupled electrically to the internal circuit. The upper side of the inductor is covered by an upper shield part and the lower side of the inductor is covered by a lower shield part. The upper shield part is formed by the use of a multilayered wiring layer. The upper shield part has plural first openings. The first opening overlaps the inductor in the planar view.

Abstract: Some novel features pertain to a semiconductor device that includes a substrate, a first cavity that traverses the substrate. The first cavity is configured to be occupied by a interconnect material (e.g., solder ball). The substrate also includes a first metal layer coupled to a first side wall of the first cavity. The substrate further includes a first integrated passive device (IPD) on a first surface of the substrate, the first IPD coupled to the first metal layer. In some implementations, the substrate is a glass substrate. In some implementations, the first IPD is one of at least a capacitor, an inductor and/or a resistor. In some implementations, the semiconductor device further includes a second integrated passive device (IPD) on a second surface of the substrate. The second IPD is coupled to the first metal layer.

Abstract: An electronic apparatus includes a semiconductor substrate, a circuit block disposed in and supported by the semiconductor substrate and comprising an inductor, and a discontinuous noise isolation guard ring surrounding the circuit block. The discontinuous noise isolation guard ring includes a metal ring supported by the semiconductor substrate and a ring-shaped region disposed in the semiconductor substrate, having a dopant concentration level, and electrically coupled to the metal ring, to inhibit noise in the semiconductor substrate from reaching the circuit. The metal ring has a first gap and the ring-shaped region has a second gap.

Abstract: The present invention relates to an on-chip electronic device and a method for manufacturing the same. The on-chip electronic device according to the present invention comprises a substrate, a porous layer, a plurality of magnetic bodies, and an electronic member layer. The porous layer is disposed on the substrate and has a plurality of voids; each of the plurality of magnetic bodies is disposed in the plurality of voids, respectively; and the electronic member layer is disposed on one side of the porous layer, such as upper side of or lower sider of the porous layer. Because the plurality of magnetic bodies is used as the core of the inductance, the inductance is increased effectively and the area of the on-chip electronic device is reduced. Besides the manufacturing method according to the present invention is simple and compatible with the current CMOS process, the manufacturing cost can be lowered.

Abstract: In accordance with an embodiment, a semiconductor component, includes a common mode filter monolithically integrated with a protection device. The common mode filter includes a plurality of coils and the protection device has a terminal coupled to a first coil and another terminal coupled to a second coil.

Abstract: A semiconductor structure is provided. The semiconductor structure includes an interposer structure. The interposer structure includes an interposer substrate, a ground, through vias, a dielectric layer, and an inductor. The through vias are formed in the interposer substrate and electrically connected to the ground. The dielectric layer is on the interposer substrate. The inductor is on the dielectric layer.

Abstract: In accordance with an embodiment, a semiconductor component includes a common mode filter monolithically integrated with a protection device. The common mode filter may be composed of first, second, third, and fourth coils, wherein each coil has first and second terminals and the first coil is magnetically coupled to the second coil and the third coil is magnetically coupled to the fourth coil. The protection device has a first terminal coupled to the first terminal of the first coil and a second terminal coupled to the first terminal of the third coil. An energy storage element has a terminal coupled to the second and first terminals of the first and second coils, respectively. Another embodiment includes monolithically integrating a common mode filter with a protection device and monolithically integrating a metal-insulator-metal capacitor with the common mode filter.

Abstract: A semiconductor package includes a semiconductor chip, an inductor applied to the semiconductor chip. The inductor includes at least one winding. A space within the at least one winding is filled with a magnetic material.

Abstract: An apparatus for performing communication control includes a control module implemented with at least one integrated circuit (IC) whose package includes a plurality of sets of terminals, each set of the plurality of sets of terminals corresponding to one of a plurality of sub-modules of the control module, and within the sets of terminals, a set of terminals corresponding to a specific sub-module of the sub-modules include a power-input terminal arranged to input power from outside the control module. For example, on a printed circuit board (PCB) of the apparatus, arrangement of some modules is similar to that of some contact pads associated to the sets of terminals. In another example, the control module includes a power distribution system including at least one power distribution wire. In another example, a PCB within the apparatus includes at least one signal transmission wire and at least one set of co-plane ground wires.

Abstract: In a semiconductor device, a first semiconductor chip includes a first circuit and a first inductor, and a second semiconductor chip includes a second circuit and chip-side connecting terminals. An interconnect substrate is placed over the first semiconductor chip and the second semiconductor chip. The interconnect substrate includes a second inductor and substrate-side connecting terminals. The second inductor is located above the first inductor. The chip-side connecting terminals and the two substrate-side connecting terminals are connected through first solder balls.

Abstract: X-line routing arrangements for dense multi-chip-package interconnects are described. In an example, an electronic signal routing structure includes a substrate. A plurality of layers of conductive traces is disposed above the substrate. A first pair of ground traces is disposed in a first of the plurality of layers of conductive traces. A signal trace is disposed in a second of the plurality of layers of conductive traces, below the first layer. A second pair of ground traces is disposed in a third of the plurality of layers of conductive traces, below the first layer. The first and second pairs of ground traces and the signal trace provide an X-pattern routing from a cross-sectional perspective.

Abstract: A chip package includes an electrically conducting chip carrier and at least one first semiconductor chip attached to the electrically conducting chip carrier. The chip package further includes a passive component. The electrically conducting chip carrier, the at least one first semiconductor chip, and the passive component are embedded in an insulating laminate structure.

Abstract: A semiconductor device includes: a spiral-shaped inductor formed to include a metal wire; and a horseshoe-shaped inductor formed to include the metal wire. The horseshoe-shaped inductor is arranged such that an opening of the horseshoe-shaped inductor is disposed opposite to the spiral-shaped inductor. Accordingly, unnecessary wave (spurious) output from a transmitting unit can be reduced as small as possible.

Abstract: The present disclosure relates to a multi-level integrated inductor that provides for a good inductance and Q-factor. In some embodiments, the integrated inductor has a first inductive structure with a first metal layer disposed in a first spiral pattern onto a first IC die and a second inductive structure with a second metal layer disposed in a second spiral pattern onto a second IC die. The first IC die is vertically stacked onto the second IC die. A conductive interconnect structure is located vertically between the first and second IC die and electrically connects the first metal layer to the second metal layer. The conductive interconnect structure provides for a relatively large distance between the first and second inductive structures that provides for an inductance having a high Q-factor over a large range of frequencies.

Abstract: A semiconductor device includes a substrate, a semiconductor chip, a first molding member and a metal layer. The substrate includes a first ground pad formed therein, the first ground pad having a first exposed surface exposed at a first surface of the substrate. The semiconductor chip is formed on the first surface of the substrate. The first molding member is formed on the first surface of the substrate and covers the semiconductor chip while not covering the first exposed surface. The metal layer covers the first molding member and extends to lateral surfaces of the substrate while contacting the first exposed surface.

Abstract: A semiconductor device substrate includes a front section and back section that are laminated cores disposed on a front- and back surfaces of a first core. The first core has a cylindrical plated through hole that has been metal plated and filled with air-core material. The front- and back sections have laser-drilled tapered vias that are filled with conductive material and that are coupled to the plated through hole. The back section includes an integral inductor coil that communicates to the front section. The first core and the laminated-cores form a hybrid-core semiconductor device substrate with an integral inductor coil.

Abstract: Embodiments of inductive communication devices include first and second galvanically isolated IC die. The first IC die has a first coil proximate to a first surface of the first IC die, and the second IC die has a second coil proximate to a first surface of the second IC die. The first and second IC die are arranged so that the first surfaces of the first and second IC die face each other, and the first coil and the second coil are aligned across a gap between the first and second IC die. One or more dielectric components are positioned within the gap directly between the first and second coils. During operation, a first signal is provided to the first coil, and the first coil converts the signal into a time-varying magnetic field. The magnetic field couples with the second coil, which produces a corresponding second signal.

Abstract: Passive circuit elements are formed at surfaces of two integrated circuit wafers. The passive circuit elements are utilized to align the two integrated circuit wafers to form an integrated circuit wafer stack.

Abstract: A semiconductor device is provided with a semiconductor chip. The semiconductor chip has a semiconductor substrate, an interconnect layer, an inductor and conductive pads (first pads). The interconnect layer is provided on the semiconductor substrate. The interconnect layer includes the inductor. The pads are provided on the interconnect layer. The pads are provided in a region within a circuit forming region of the semiconductor chip, which does not overlap the inductor.

Abstract: In accordance with an embodiment, a semiconductor device comprises a semiconductor die, an interposer, and conductive bumps bonding the semiconductor die to the interposer. The semiconductor die comprises a first metallization layer, and the first metallization layer comprises a first conductive pattern. The interposer comprises a second metallization layer, and the second metallization layer comprises a second conductive pattern. Some of the conductive bumps electrically couple the first conductive pattern to the second conductive pattern to form a coil. Other embodiments contemplate other configurations of coils, inductors, and/or transformers, and contemplate methods of manufacture.

Abstract: A semiconductor device comprises a conductor film and a capacitor comprising a lower electrode provided on the conductor film. The conductor film includes a first conductive film containing a first metal, a second conductive film containing a second metal on the first conductive film, and an oxide film of the second metal on the second conductive film. The oxide film of the second metal has a lower electric resistivity than an oxide film of the first metal.

Abstract: A patterned ground shield structure is provided. The patterned ground shield structure includes a substrate having a dielectric layer. The patterned ground shield structure also includes a plurality of conductive rings having a plurality of sub conductive rings in the dielectric layer. Further, the patterned ground shield structure includes an interconnection line connecting with all of the sub conductive rings in the dielectric layer. Further, the patterned ground shield structure also includes a ground ring connecting with the interconnection line.

Abstract: An integrated circuit (IC) package including an IC die and a conductive ink printed circuit layer electrically connected to the IC die.

Abstract: Various methods and systems are provided for power inductors in silicon (PIiS) In one embodiment, a PIiS includes a magnetic core of magnetic material embedded in a silicon substrate, and a conductive winding having a plurality of turns, where adjacent turns of the conductive winding have a space therebetween, and where at least a portion of the magnetic core is encircled by the conductive winding In another embodiment, a DC to DC converter includes a PIiS, which includes a magnetic core of magnetic material embedded in a silicon substrate, a conductive winding having a plurality of turns, where at least a portion of the magnetic core is encircled by the conductive winding, and a cap layer of magnetic material disposed on at least one side of the silicon substrate The DC to DC converter also includes an integrated circuit mounted on the cap layer of the power inductor in silicon.

Abstract: To suppress the noise caused by an inductor leaks to the outside, and also to be configured such that magnetic field intensity change reaches the inductor. An inductor surrounds an internal circuit in a planar view and also is coupled electrically to the internal circuit. The upper side of the inductor is covered by an upper shield part and the lower side of the inductor is covered by a lower shield part. The upper shield part is formed by the use of a multilayered wiring layer. The upper shield part has plural first openings. The first opening overlaps the inductor in the planar view.

Abstract: An integrated circuit has a semiconductor die provided in a first IC layer and an inductor fabricated on a second IC layer. The inductor may have a winding and a magnetic core, which are oriented to conduct magnetic flux in a direction parallel to a surface of a semiconductor die. The semiconductor die may have active circuit components fabricated in a first layer of the die, provided under the inductor layer. The integrated circuit may include a flux conductor provided on a side of the die opposite the first layer. PCB connections to active elements on the semiconductor die may progress through the inductor layer as necessary.

Abstract: The present disclosure involves a semiconductor device. The semiconductor device includes a substrate; a capacitor disposed over the substrate; an inductor disposed over the substrate and having a coil feature surrounding the capacitor; and a shielding structure over the substrate and configured around the coil feature.

Abstract: Back-end-of-line (BEOL) wiring structures and inductors, methods for fabricating BEOL wiring structures and inductors, and design structures for a BEOL wiring structure or an inductor. A feature, which may be a trench or a wire, is formed that includes a sidewall intersecting a top surface of a dielectric layer. A surface layer is formed on the sidewall of the feature. The surface layer is comprised of a conductor and has a thickness selected to provide a low resistance path for the conduction of a high frequency signal.

Abstract: The electronic device comprises a network of at least one thin-film capacitor and at least one inductor on a first side of a substrate of a semiconductor material. The substrate has a resistivity sufficiently high to limit electrical losses of the inductor and being provided with an electrically insulating surface layer on its first side. A first and a second lateral pin diode are defined in the substrate, each of the pin diodes having a doped p-region, a doped n-region and an intermediate intrinsic region. The intrinsic region of the first pin diode is larger than that of the second pin diode.

Abstract: An integrated circuit that includes an on-chip inductor wrapped around an interface pad. On-chip inductors are arranged around an interface pad to reduce the area occupied by the inductor. Furthermore, arranging the on-chip inductors in an upper level metal layer, such us the redistribution layer (RDL), the top metal interconnect layer (MTop), or the second-to-top metal interconnect layer (MTop-1) reduces the on-chip inductor parasitic resistance, reducing the loss of signal.