Abstract: A semiconductor device includes a substrate, first and second bond pad structures supported by the substrate and spaced from one another by a gap, and a wire bond foot jumper extending across the gap and bonded to the first and second bond pad structures.

Abstract: Embodiments of the present disclosure are directed toward techniques and configurations associated with a capductor assembly. In one embodiment, a capductor assembly may include a semiconductor wafer and a plurality of inductors disposed on a first side of the semiconductor wafer. The plurality of inductors may be embedded in electrically insulative material having a plurality of interconnect structures disposed thereon. The plurality of interconnect structures may be configured to electrically couple the plurality of inductors to a die. The IC assembly may further include a plurality of capacitors disposed on a second side of the wafer disposed opposite the first side of the wafer. The plurality of capacitors may be electrically coupled with a second plurality of interconnect structures that may be configured to electrically couple the plurality of capacitors with the die. Other embodiments may be described and/or claimed.

Abstract: A semiconductor device includes: a first semiconductor chip having a first antenna that is formed in a first hole provided in the first semiconductor chip, has an inclined surface inclined with respect to a central line of the first hole, and transmits and receives a radio wave; and a second semiconductor chip stacked over the first semiconductor chip, the second semiconductor chip having a second antenna that is formed in a second hole provided in the second semiconductor chip, has an inclined surface inclined with respect to a central line of the second hole, and transmits and receives a radio wave, wherein the first antenna and the second antenna are disposed so that the inclined surface of the first antenna and the inclined surface of the second antenna face each other.

Abstract: A packaged semiconductor die with a bumpless die-package interface and methods of fabrication are described. For example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines, one of which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate. In another example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines with a layer of conductive vias disposed thereon. At least one of the conductive lines is coupled directly to a conductive via of the semiconductor die which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate.

Abstract: A coil assembly is disclosed. The coil assembly includes a coil that is provided on a substrate. The coil includes a trace element that is wound on the substrate. The trace element includes an interior gap that extends or is present along at least a portion of the trace element. The interior gap is dimensioned to reduce a presence of eddy currents that would otherwise be generated when the coil is active to inductively transmit or receive signals.

Abstract: A thin film semiconductor device including a thin film transistor (TFT) that maintains a constant electrical characteristic and an organic light-emitting display device. The thin film semiconductor device includes: a substrate; and a thin film transistor (TFT) disposed on the substrate and comprising a semiconductor layer comprising a source region and a drain region, wherein a part of the source region is spaced apart from the drain region and partially surrounds the drain region, and wherein a part of the drain region is spaced apart from the source region and partially surrounds the source region.

Abstract: In one general aspect, a method can include forming a redistribution layer on a substrate using a first electroplating process, and forming a conductive pillar on the redistribution layer using a second electroplating process. The method can include coupling a semiconductor die to the redistribution layer, and can include forming a molding layer encapsulating at least a portion of the redistribution layer and at least a portion of the conductive pillar.

Abstract: A multi-port inductor structure for use in semiconductor applications such as high-performance RF filters and amplifiers is provided. Embodiments of the present invention may provide 3 metallization layers and two via layers. The metallization layers and via layers may be substantially stacked on top of each other to conserve space. Each metallization layer comprises a ring pattern. In embodiments, the top two ring patterns include a plurality of concentric bands, forming a spiral pattern. The third (bottom) ring may include a broken ring pattern. In embodiments, the second (middle) ring may include one or more spans to facilitate connection to the inner bands of the second ring. The spans connect inner bands to an outer perimeter region of the second ring. Multiple tap points along the bands and spans allow multiple inductance values to be obtained from the structure.

Abstract: Various embodiments provide semiconductor structures and fabrication methods. In an exemplary method, a semiconductor substrate can contain a shallow trench isolation (STI) structure that includes a fuse region. A protective layer can be provided on the high-K dielectric layer, which is provided on the semiconductor substrate. A portion of each of the protective layer and the high-K dielectric layer can be removed from the fuse region to expose the STI structure. A fuse layer can be formed on the exposed surface of the STI structure. A portion of the fuse layer, the remaining portion of the protective layer, and a remaining portion of the high-K dielectric layer outside of the fuse region can be removed from the semiconductor substrate to form a fuse structure.

Abstract: An inductive touch screen is disclosed. Embodiments include a transparent substrate and a conductive layer. The conductive layer includes helical-shaped patterns, and inductive lines electrically connected with the patterns. The patterns form inductive electrodes and output inductive signals through the inductive lines, and the inductive lines include first and second inductive lines. The inductive electrodes includes rows of first sub-electrodes and rows of second sub-electrodes, where the first and second sub-electrodes are arranged alternately in a column direction. Each of the first inductive lines is electrically connected with a row of the first sub-electrodes, and each of the second inductive lines is electrically connected with the second sub-electrodes in a same column. The touch screen further includes a drive line on the substrate, and the drive line is electrically connected with the inductive electrodes to provide the touch screen with a drive signal.

Abstract: Radio frequency identification (RFID) tags and processes for manufacturing the same. The RFID device generally includes (1) a metal antenna and/or inductor; (2) a dielectric layer thereon, to support and insulate integrated circuitry from the metal antenna and/or inductor; (3) a plurality of diodes and a plurality of transistors on the dielectric layer, the diodes having at least one layer in common with the transistors; and (4) a plurality of capacitors in electrical communication with the metal antenna and/or inductor and at least some of the diodes, the plurality of capacitors having at least one layer in common with the plurality of diodes and/or with contacts to the diodes and transistors. The method preferably integrates liquid silicon-containing ink deposition into a cost effective, integrated manufacturing process for the manufacture of RFID circuits. Furthermore, the present RFID tags generally provide higher performance (e.g.

Abstract: A mechanism is provided for integrating an inductor into a semiconductor. A circular or other closed loop trench is formed in a substrate with sidewalls connected by a bottom surface in the substrate. A first insulator layer is deposited on the sidewalls of the trench so as to coat the sidewalls and the bottom surface. A conductor layer is deposited on the sidewalls and the bottom surface of the trench so as to coat the first insulator layer in the trench such that the conductor layer is on top of the first insulator layer in the trench. A first magnetic layer is deposited on the sidewalls and bottom surface of the trench so as to coat the first insulator layer in the trench without filling the trench. The first magnetic layer deposited on the sidewalls forms an inner closed magnetic loop and an outer closed magnetic loop within the trench.

Abstract: In accordance with an embodiment of the present invention, a semiconductor package includes a semiconductor chip disposed within an encapsulant, and a first coil disposed in the semiconductor chip. A dielectric layer is disposed above the encapsulant and the semiconductor chip. A second coil is disposed above the dielectric layer. The first coil is magnetically coupled to the second coil.

Abstract: A semiconductor device including a first insulating layer and a second insulating layer sequentially disposed on a substrate is disclosed. A first conductive line and a second conductive line are disposed in the first insulating layer, and each of the first and second conductive lines has a first end and a second end, wherein the second ends of the first and second conductive lines are coupled to each other. A first winding portion and a second winding portion are disposed in the second insulating layer, and each of the first and second winding portions includes a third conductive line and a fourth conductive line arranged from the inside to the outside. Each of the third and fourth conductive lines has a first end and a second end, wherein the first and second conductive lines overlap at least a portion of the third conductive lines.

Abstract: This invention pertains to the connection between a radio frequency circuit and its antenna. Miniaturization of radio frequency integrated circuits has made attaching these circuits to their antennas increasingly difficult and costly. This invention uses magnetic coupling, as performed in transformers, between circuits and antennas as a practical solution to reduce cost and effort in attaching the two sides as well as to protect the circuit against electrostatic discharge. Furthermore a simple pre-assembly testing methodology is accounted for as an additional benefit of the method.

Abstract: A semiconductor device comprises a conductor film and a capacitor comprising a lower electrode provided on the conductor film. The conductor film includes a first conductive film containing a first metal, a second conductive film containing a second metal on the first conductive film, and an oxide film of the second metal on the second conductive film. The oxide film of the second metal has a lower electric resistivity than an oxide film of the first metal.

Abstract: An inductor implemented in an integrated circuit is described. The inductor comprises a plurality of loops of the inductor in at least a first metal layer and a second metal layer of a plurality of metal layers; and a plurality of vias connecting ends of loops of the plurality of loops in different metal layers; wherein each loop of the first metal layer which is connected to a corresponding loop of the second metal layer overlies the corresponding loop of the second metal layer. A method of implementing an inductor in an integrated circuit is also described.

Abstract: A parallel stacked symmetrical and differential inductor and manufacturing method of the same is disclosed. The parallel stacked symmetrical and differential inductor is disposed on a substrate and comprises at least one first conductive layer (202, 204) disposed on an insulating layer and at least one subsequent conductive layer (206, 208) disposed on a plurality of insulating layers stacked under the at least one first conductive layer (202, 204). The at least one first conductive layer (202, 204) and each of the at least one subsequent conductive layer (206, 208) are electrically connected by a first plurality of conductive plugs (214) in a winding region (104). Each of the at least one subsequent conductive layer (206, 208) are electrically connected by a second plurality of conductive plugs (212) in a bridge region (102).

Abstract: A coil inductor and buck voltage regulator incorporating the coil inductor are provided which can be fabricated on a microelectronic element such as a semiconductor chip, or on an interconnection element such as a semiconductor, glass or ceramic interposer element. When energized, the coil inductor has magnetic flux extending in a direction parallel to first and second opposed surfaces of the microelectronic or interconnection element, and whose peak magnetic flux is disposed between the first and second surfaces. In one example, the coil inductor can be formed by first conductive lines extending along the first surface of the microelectronic or interconnection element, second conductive lines extending along the second surface of the microelectronic or interconnection element, and a plurality of conductive vias, e.g., through silicon vias, extending in direction of a thickness of the microelectronic or interconnection element. A method of making the coil inductor is also provided.

Abstract: A ceramic electronic component includes an electronic component body and first and second metal terminals. The electronic component body includes a bare ceramic body and first and second outer electrodes. The first and second outer electrodes of the electronic component body are connected respectively to the first and second metal terminals by solders containing Sn as a main constituent. An alloy layer containing Ni—Sn is provided in at least a portion of a bonding interface between adjacent two of the first and second metal terminals and the first and second outer electrodes.

Abstract: A semiconductor device includes a low noise amplifier configured to amplify a radio signal from an antenna and output an reception signal, a down converter configured to down-convert the reception signal, a first divider coupled with the down converter, a first local oscillator coupled with the first divider, a modulator configured to modulate a transmission signal, a second divider coupled with the modulator, and a second local oscillator coupled with the second divider. The modulator includes a first inductor of a spiral shape, the local oscillator includes a second inductor of a horse-shape having an opening, and the opening of the second inductor is disposed opposite to the first inductor.

Abstract: A transformer comprising primary and secondary windings is disclosed. Each winding has first and second metal capping layers coupled together electrically in parallel by a metal connector passing through a substrate lying between the first and second metal capping layers.

Abstract: A method for fabricating a molded interposer package includes performing a first anisotropic etching process to remove a portion of the metal sheet from a top surface of the metal sheet, thereby forming a plurality of first recesses in the metal sheet, forming a molding material covering the top surface, filling the first recesses, forming a plurality of first via openings in the molding material, wherein the first via openings expose the top surface, forming a plurality of first metal vias in the first via openings and a plurality of first redistribution layer patterns respectively on the first metal vias, performing a second anisotropic etching process to remove a portion of the metal sheet from a bottom surface of the metal sheet until a bottom of the molding material is exposed, and forming a solder mask layer on the molding material, leaving the first redistribution layer patterns exposed.

Abstract: In accordance with an embodiment, a semiconductor device comprises a semiconductor die, an interposer, and conductive bumps bonding the semiconductor die to the interposer. The semiconductor die comprises a first metallization layer, and the first metallization layer comprises a first conductive pattern. The interposer comprises a second metallization layer, and the second metallization layer comprises a second conductive pattern. Some of the conductive bumps electrically couple the first conductive pattern to the second conductive pattern to form a coil. A magnetic layer is positioned within the coil. In another embodiment, a coil is formed on a single substrate, wherein a magnetic layer is positioned within the coil. Other embodiments contemplate other configurations of coils, inductors, and/or transformers, and contemplate methods of manufacture.

Abstract: A monolithically integrated circuit, particularly an integrated circuit for radio frequency power applications, may include a transistor and a spiral inductor. The spiral inductor is arranged above the transistor. An electromagnetic coupling is created between the transistor and the inductor. The transistor may have a finger type layout to prevent any significant eddy currents caused by the electromagnetic coupling from occurring. The chip area needed for the circuit may be reduced by such arrangement.

Abstract: An integrated circuit has a semiconductor die provided in a first IC layer and an inductor fabricated on a second IC layer. The inductor may have a winding and a magnetic core, which are oriented to conduct magnetic flux in a direction parallel to a surface of a semiconductor die. The semiconductor die may have active circuit components fabricated in a first layer of the die, provided under the inductor layer. The integrated circuit may include a flux conductor provided on a side of the die opposite the first layer. PCB connections to active elements on the semiconductor die may progress through the inductor layer as necessary.

Abstract: The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member.

Abstract: Devices, methods and production devices that relate to the forming of a coil on a semiconductor substrate are provided. Arranged within the coil is a metal filling, for example with a density of less than 20%.

Abstract: Embodiments of the present disclosure are directed towards a circuit board having integrated passive devices such as inductors, capacitors, resistors and associated techniques and configurations. In one embodiment, an apparatus includes a circuit board having a first surface and a second surface opposite to the first surface and a passive device integral to the circuit board, the passive device having an input terminal configured to couple with electrical power of a die, an output terminal electrically coupled with the input terminal, and electrical routing features disposed between the first surface and the second surface of the circuit board and coupled with the input terminal and the output terminal to route the electrical power between the input terminal and the output terminal, wherein the input terminal includes a surface configured to receive a solder ball connection of a package assembly including the die. Other embodiments may be described and/or claimed.

Abstract: A semiconductor package is provided that has a transformer formed within a multilayer dielectric laminate substrate. The transformer has a first inductor coil formed in one or more dielectric laminate layers of the substrate, a second inductor coil formed in one or more dielectric laminate layers of the substrate, and an isolation barrier comprising two or more dielectric laminate layers of the multilayer substrate positioned between the first inductor coil and the second inductor coil. The transformer may be mounted on a lead frame along with one or more integrated circuits and molded into a packaged isolation device.

Abstract: A first spiral inductor is provided on the semiconductor substrate. A dielectric film covers the first spiral inductor. A second spiral inductor is provided on the dielectric film. A connecting portion penetrates the dielectric film and electrically connects a first inner end portion of the first spiral inductor to a second inner end portion of the second spiral inductor. Winding direction of the first spiral inductor from a first outer end portion toward the first inner end portion is the same as the winding direction of the second spiral inductor from a second inner end portion toward the second outer end portion. A wire of the second spiral inductor is disposed opposite the first spiral inductor with the dielectric film between them. The wire of the second spiral inductor is disposed in gaps between windings of the first spiral inductor, when viewed in a plan view.

Abstract: Some novel features pertain to a first example provides a semiconductor device that includes a printed circuit board (PCB), asset of solder balls and a die. The PCB includes a first metal layer. The set of solder balls is coupled to the PCB. The die is coupled to the PCB through the set of solder balls. The die includes a second metal layer and a third metal layer. The first metal layer of the PCB, the set of solder balls, the second and third metal layers of the die are configured to operate as an inductor in the semiconductor device. In some implementations, the die further includes a passivation layer. The passivation layer is positioned between the second metal layer and the third metal layer. In some implementations, the second metal layer is positioned between the passivation layer and the set of solder balls.

Abstract: In a first semiconductor chip, a first multilayer interconnect layer is formed on a first substrate, and a first inductor is formed in the first multilayer interconnect layer. In a second semiconductor chip, a second multilayer interconnect layer is formed on a second substrate. A second inductor is formed in the second multilayer interconnect layer. The first semiconductor chip and the second semiconductor chip overlap each other in a direction in which the first multilayer interconnect layer and the second multilayer interconnect layer face each other. In addition, the first inductor and the second inductor overlap each other when seen in a plan view. At least one end of a first insulating film does not overlap the end of a facing region, in a Y direction.

Abstract: The present disclosure provides a semiconductor package, which includes a substrate, a passivation layer, a post-passivation interconnect (PPI) having a top surface; and a conductive structure. The top surface of the PPI includes a first region receiving the conductive structure, and a second region surrounding the first region. The second region includes metal derivative transformed from materials made of the first region. The present disclosure provide a method of manufacturing a semiconductor package, including forming a first flux layer covering a portion of a top surface of a PPI; transforming a portion of the top surface of the PPI uncovered by the first flux layer into a metal derivative layer; removing the first flux layer; forming a second flux layer on the first region of the PPI; dropping a solder ball on the flux layer; and forming electrical connection between the solder ball and the PPI.

Abstract: Some implementations provide an integrated device (e.g., semiconductor device) that includes a substrate and an inductor in the substrate. In some implementations, the inductor is a solenoid inductor. The inductor includes a set of windings. The set of windings has an inner perimeter. The set of windings includes a set of interconnects and a set of vias. The set of interconnects and the set of vias are located outside the inner perimeter of the set of windings. In some implementations, the set of windings further includes a set of capture pads. The set of interconnects is coupled to the set of vias through the set of capture pads. In some implementations, the set of windings has an outer perimeter. The set of pads is coupled to the set of interconnects such that the set of pads is at least partially outside the outer perimeter of the set of windings.

Abstract: A magnetometer is described, having a substrate and a magnetic core, the substrate having an excitation coil for generating a magnetic flux in the magnetic core; and the excitation coil having a coil cross section, which is aligned generally perpendicular to a main plane of extension of the substrate. The magnetic core is situated outside the coil cross section.

Abstract: A semiconductor device includes an interface layer, a smooth conductive layer disposed over the interface layer, and a first insulating layer disposed over a first surface of the smooth conductive layer. A first conductive layer is disposed over the first insulating layer and the interface layer, and the first conductive layer contacts the first insulating layer. A second insulating layer is disposed over the second insulating layer and the first conductive layer, and a second conductive layer is disposed below the first conductive layer and contacts a second surface of the smooth conductive layer. The second surface of the smooth conductive layer is opposite the first surface of the smooth conductive layer. A third insulating layer is disposed over the first insulating layer and the first surface of the smooth conductive layer, and a fourth insulating layer is disposed below the second conductive layer and the interface layer.

Abstract: A semiconductor device includes a semiconductor substrate, and a multilayer wiring layer provided over the semiconductor substrate. The multilayer wiring layer includes an inductor wiring formed in one wiring layer, a plurality of first dummy metals formed in the same layer as the inductor and provided inside the inductor, a plurality of second dummy metals formed in a same layer as the inductor and provided outside the inductor, a plurality of third dummy metals formed in a layer lower than the one wiring layer including the inductor, and provided inside the inductor in a plan view, a plurality of fourth dummy metals formed in a same layer as the plurality of third dummy metals and provided outside the inductor in the plan view, and a plurality of fifth dummy metals formed in the same layer as the plurality of third dummy metals and provided to overlap with the inductor.

Abstract: An inductive capacitive structure including a first substrate, a first conductive line over the first substrate, a first shielding layer over the first substrate and a second substrate over the first substrate.

Abstract: Some novel features pertain to an integrated device that includes a substrate, a first cavity through the substrate, and a toroid inductor configured around the first cavity of the substrate. The toroid inductor includes a set of windings configured around the first cavity. The set of windings includes a first set of interconnects on a first surface of the substrate, a set of though substrate vias (TSVs), and a second set of interconnects on a second surface of the substrate. The first set of interconnects is coupled to the second set of interconnects through the set TSVs. In some implementations, the integrated device further includes an interconnect material (e.g., solder ball) located within the first cavity. The interconnect material is configured to couple a die to a printed circuit board. In some implementations, the interconnect material is part of the toroid inductor.

Abstract: Embodiments of mechanisms for forming a semiconductor device structure are provided. The semiconductor device structure includes a metal-insulator-metal (MIM) capacitor formed on a substrate. The semiconductor device structure also includes an inductor formed on the MIM capacitor. The semiconductor device structure further includes a via formed between the MIM capacitor and the inductor, and the via is formed in a plurality of dielectric layers, and the dielectric layers comprise an etch stop layer.

Abstract: Some implementations provide an interposer that includes a substrate, a first passive device in the substrate, and a second passive device. The first passive device includes a first set of through substrate vias (TSVs) in the substrate. The second passive device is configured to wirelessly couple to the first passive device. In some implementations, the second passive device includes a second set of through substrate vias (TSVs) in the substrate. In some implementations, the second passive device is configured to inductively couple to the first passive device. In some implementations, the first passive device is a first inductor and the second passive device is a second inductor. In some implementations, the interposer further includes a first set of interconnects coupled to the first set of TSVs, and a second set of interconnects coupled to the second set of TSVs.

Abstract: The invention provides a semiconductor structure. The semiconductor structure includes a substrate. A first passivation layer is disposed on the substrate. A conductive pad is disposed on the first passivation layer. A second passivation layer is disposed on the first passivation layer. A passive device is disposed on the conductive pad, passing through the second passivation layer. An organic solderability preservative film covers the passive device.

Abstract: Various embodiments provide inductor devices and fabrication methods. An exemplary inductor device can include a plurality of planar spiral wirings isolated by a dielectric layer. The planar spiral wirings can be connected by conductive pads formed over the dielectric layer and by conductive plugs formed in the dielectric layer. In one embodiment, a third planar spiral wiring can be formed over a second planar spiral wirings that is formed over a first planar spiral wiring. The third planar spiral wiring can be configured in parallel with the first third planar spiral wiring. The second planar spiral wiring can be configured in series with the first and third planar spiral wirings configured in parallel.

Abstract: Semiconductor devices and methods of formation are provided herein. A semiconductor device includes a first inductor, a patterned ground shielding (PGS) proximate the first inductor comprising one or more portions and a first switch configured to couple a first portion of the PGS to a second portion of the PGS. The semiconductor device also has a configuration including a first inductor on a first side of the PGS, a second inductor on a second side of the PGS and a first switch configured to couple a first portion of the PGS to a second portion of the PGS. Selective coupling of portions of the PGS by activating or deactivating switches alters the behavior of the first inductor, or the behavior and interaction between the first inductor and the second inductor. A mechanism is thus provided for selectively configuring a PGS to control inductive or other properties of a circuit.

Abstract: Collections of laterally crystallized semiconductor islands for use in thin film transistors and systems and methods for making same are described. A display device includes a plurality of thin film transistors (TFTs) on a substrate, such that the TFTs are spaced apart from each other and each include a channel region that has a crystalline microstructure and a direction along which a channel current flows. The channel region of each of the TFTs contains a crystallographic grain that spans the length of that channel region along its channel direction. Each crystallographic grain in the channel region of each of the TFTs is physically disconnected from and crystallographically uncorrelated with each crystallographic grain in the channel region of each adjacent TFT.

Abstract: An inductor device includes an insulation layer, an inductor, fixed electrodes, and a movable electrode. The inductor is formed on the insulation layer. The fixed electrodes are provided in positions which do not overlap with the inductor in a planar view. The movable electrode overlaps with the inductor and the fixed electrodes in the planar view, and is separated from the inductor and the fixed electrodes. Further, the movable electrode includes first openings.

Abstract: An embodiment of an electronic device includes first and second semiconductor bodies. The first semiconductor body houses a first conductive strip having a first end portion and a second end portion, and houses a first conduction terminal electrically coupled to the first end portion and facing a surface of the first semiconductor body. The second semiconductor body houses a second conductive strip having a third end portion and a fourth end portion, and houses a second conduction terminal electrically coupled to the third end portion and facing a surface of the second semiconductor body. The first and second semiconductor bodies are arranged relative to one another so that the respective surfaces face one another, and the first conduction terminal and the second conduction terminal are coupled to one another by means of a conductive element so as to form a loop of an inductor.

Abstract: Embodiments of mechanisms of forming an inductor structure are provided. The inductor structure includes a substrate and a first dielectric layer formed over the substrate. The inductor structure includes a first metal layer formed in the first dielectric layer and a second dielectric layer over the first metal layer. The inductor structure further includes a magnetic layer formed over the first dielectric layer, and the magnetic layer has a top surface, a bottom surface and sidewall surfaces between the top surface and the bottom surface, and the sidewall surfaces have at least two intersection points.

Abstract: A semiconductor FET provides a resonant gate and source and drain electrodes, wherein the resonant gate is electromagnetically resonant at one or more predetermined frequencies.