Abstract: A semiconductor device package and a method of manufacturing the same are provided. The semiconductor device package includes a first carrier, an encapsulant, a second carrier and one or more supporters. The first carrier has a first surface and a first side contiguous with the first surface. The encapsulant is on the first surface of the first carrier, and the first side of the first carrier is exposed from the encapsulant. The second carrier is disposed over the first carrier. The one or more supporters are spaced apart from the first side of the first carrier and connected between the first carrier and the second carrier. The one or more supporters are arranged asymmetrically with respect to the geographic center of the first carrier. The one or more supporters are fully sealed in the encapsulant.

Abstract: A semiconductor structure includes a first layer, a second layer, a first interconnection layer, and a second interconnection layer. The first layer includes an upper electrode pattern, and the second layer includes a lower electrode pattern, wherein the upper electrode pattern is opposite to the lower electrode pattern. The first interconnection layer includes a plurality of first interconnect structures electrically connected on the upper electrode pattern. The second interconnection layer includes a plurality of second interconnect structures electrically connected on the lower electrode pattern. The first interconnect structures on the upper electrode pattern are hybrid bonded with the second interconnect structures on the lower electrode pattern. Therefore, the upper electrode patterns and the lower electrode patterns are joined by hybrid bonding to form a capacitor element.

Abstract: Provided is an article of cookware and a method of making the same. The cookware has at least one stainless steel layer and at least one copper layer metallurgically bonded directly to the at least one stainless steel layer via solid state bonding. The at least one stainless steel layer may be a ferritic stainless steel layer, and the at least one copper layer may be a grain stabilized copper. The at least one stainless steel layer may be made from a 400 series stainless steel, such as a 436 stainless steel alloy, a 439 stainless steel alloy, or a 444 stainless steel alloy. The at least one copper layer may be made from a high purity, oxygen free copper alloy, such as a C101 copper alloy, a C102 copper alloy, or a C107 copper alloy.

Abstract: An array substrate and a display panel are provided. The present disclosure can form a capacitor by having a first metal layer which forms a start pulse signal line to be a first plate, and having a second metal layer which is connected to a peripheral common electrode line to be a second plate, thereby achieving electrostatic protection. In addition, by designing the start pulse signal line from an original wire-wound type to a grid shape, accumulated electric charges accumulated in the start pulse signal line can be effectively eliminated, thereby reducing probability of electrostatic discharge in the start pulse signal line.

Abstract: A semiconductor memory device includes an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers which are alternately stacked on a substrate defined with a plurality of cell areas and a plurality of coupling areas in a first direction; a hard mask pattern disposed on the electrode structure, and having a plurality of opening holes in the coupling areas; and a plurality of contact holes defined in the electrode structure under the plurality of opening holes, and exposing pad areas of the electrode layers, respectively. The plurality of opening holes are disposed by being distributed in a plurality of rows arranged in a second direction intersecting with the first direction.

Abstract: A micro detector includes a substrate, a fin structure, a floating gate, a sensing gate, a reading gate and an antenna layer. The fin structure is located on the substrate. The floating gate is located on the substrate, and the floating gate is vertically and crossly arranged with the fin structure. The sensing gate is located at one side of the fin structure. The reading gate is located at the other side of the fin structure. The antenna layer is located on the sensing gate and is connected with the sensing gate. An induced charge is generated when the antenna layer is contacted with an external energy source, and the induced charge is stored in the floating gate.

Abstract: Some embodiments include a transistor having an active region containing semiconductor material. The semiconductor material includes at least one element selected from Group 13 of the periodic table in combination with at least one element selected from Group 16 of the periodic table. The active region has a first region, a third region offset from the first region, and a second region between the first and third regions. A gating structure is operatively adjacent to the second region. A first carrier-concentration-gradient is within the first region, and a second carrier-concentration-gradient is within the third region. Some embodiments include methods of forming integrated assemblies.

Abstract: Some image sensors include pixels with capacitors. The capacitor may be used to store charge in the imaging pixel before readout. The capacitor may be a metal-insulator-metal (MIM) capacitor that is susceptible to dielectric relaxation. Dielectric relaxation may cause lag in the signal on the capacitor that impacts the signal on the capacitor during sampling. The image sensor may include dielectric relaxation correction circuitry that leverages the linear relationship between voltage stress and lag signal to correct for dielectric relaxation. The image sensor may include shielded pixels that operate with a similar timing scheme as the imaging pixels in the active array. Measured lag signals from the shielded pixels may be used to correct imaging data.

Abstract: A method for fabricating a phase shift mask includes preparing a transmissive substrate on which a first mask region and a second mask region surrounding the first mask region are defined. In the first mask region, main patterns are formed having a first pitch in a first direction and a second direction perpendicular to the first direction. Each of the main patterns has a first area. In at least one row, assist patterns are formed at the first pitch to surround the main patterns. Each of the assist patterns has a second area less than the first area. In the second mask region, dummy patterns are formed in a plurality of rows. The dummy patterns surround the assist patterns at the first pitch. Each of the dummy patterns has a third area greater than the first area.

Abstract: According to an embodiment, a capacitor includes a conductive substrate, a conductive layer and a dielectric layer. The conductive substrate has a first main surface and a second main surface. The first main surface includes sub-regions. Each sub-region is provided with recesses or projections each having a shape extending in one direction and arranged in a width direction thereof. One or more of the sub-regions and another one or more of the sub-regions are different from each other in a length direction of the recesses or protrusions. The conductive layer covers sidewalls and bottom surfaces of the recesses or sidewalls and top surfaces of the projections. The dielectric layer is interposed between the conductive substrate and the conductive layer.

Abstract: A structure comprises a substrate and a conductive pad disposed over the substrate. A conductive layer overlies the conductive pad. A via is disposed over the conductive pad. The via penetrates through the conductive layer and touches a surface of the conductive pad.

Abstract: The present disclosure relates to systems and methods for providing wireless power to implanted devices. Consistent with some embodiments, a power system for providing wireless power to a device implanted in a body of an individual includes a first antenna loop that produces a first electromagnetic wave and at least one second antenna loop that produces a second electromagnetic wave. The first and second electromagnetic waves may interfere with one another to produce an interference pattern including interference maxima. Further, a location of at least one of the interference maxima may be at or substantially close to the device implanted in the body of the individual. A broad distribution pattern at the surface of the skin can reduce the specific absorption rate of the transmission, while focusing the transmission toward the implanted device improves the antenna system's transfer efficiency.

Abstract: A multilayer ceramic capacitor includes a body including a dielectric layer and first and second internal electrodes disposed with the dielectric layer interposed therebetween and disposed in point-symmetry with each other; first and second connection electrodes penetrating the body in a direction perpendicular to the dielectric layer and connected to the first internal electrode; third and fourth connection electrodes penetrating the body in a direction perpendicular to the dielectric layer and connected to the second internal electrode; first and second external electrodes disposed on both surfaces of the body and connected to the first and second connection electrodes; and third and fourth external electrodes spaced apart from the first and second external electrodes and connected to the third and fourth connection electrodes, and the first and second internal electrodes include a region in which an electrode is not disposed.

Abstract: An integrated circuit (IC) package is described. The IC package includes back-end-of-line layers on a substrate. The IC package also includes a nested interconnect structure on the back-end-of-line layers on the substrate. The nested interconnect structure is composed of an inner core pad and an outer ring pad in a concentric arrangement. The IC package further includes a redistribution layer on the nested interconnect structure. The IC package also includes an under bump metallization layer on the redistribution layer to support package balls.

Abstract: Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. A spacer structure having air gaps is formed on sidewalls of the first contact plug and on sidewalls of the bit line. An plug isolation layer is formed between the plurality of bit line structures. The isolation layer includes an opening. A second contact plug is formed in the opening and a memory element is formed over the second contact plug.

Abstract: A method includes forming a gate dielectric comprising a portion extending on a semiconductor region, forming a barrier layer comprising a portion extending over the portion of the gate dielectric, forming a work function tuning layer comprising a portion over the portion of the barrier layer, doping a doping element into the work function tuning layer, removing the portion of the work function tuning layer, thinning the portion of the barrier layer, and forming a work function layer over the portion of the barrier layer.

Abstract: The present invention is targeted at suppressing ringing and overvoltage. A driver circuit (200) drives a plurality of loads (Z1 to ZN). A plurality of output terminals (Po1 to PoN) are connected to the plurality of loads (Z1 to ZN). A plurality of drivers (Dr1 to DrN) correspond to the plurality output terminals (Po1 to PON), and generate driving signals (Vo#) applied to the respectively corresponding load (Z#). A plurality of clamp circuits (260_1 to 260_N) correspond to the plurality of drivers (Dr1 to DrN), and include Schottky diodes (SD) connected to input nodes or output nodes of the respectively corresponding drivers (Dr).

Abstract: A non-volatile memory device includes a substrate, a memory cell string including a vertical channel structure and memory cells, a voltage generator including a first transistor and configured to provide various voltages to the memory cells, and a vertical capacitor structure. The vertical capacitor structure includes first and second active patterns apart from each other in a first horizontal direction, a first gate pattern located above a channel region between the first and second active patterns, a first gate insulating film between the first gate pattern and the substrate in a vertical direction, and capacitor electrodes each extending in the vertical direction. The first transistor includes a second gate pattern and a second gate insulating film between the second gate pattern and the substrate in the vertical direction. The first gate insulating film has a thickness greater than a thickness of the second gate insulating film in the vertical direction.

Abstract: Some embodiments include an integrated assembly having first and second source/drain regions laterally offset from one another. Metal silicide is adjacent to lateral surfaces of the source/drain regions. Metal is adjacent to the metal silicide. Container-shaped first and second capacitor electrodes are coupled to the source/drain regions through the metal silicide and the metal. Capacitor dielectric material lines interior surfaces of the container-shaped first and second capacitor electrodes, A shared capacitor electrode extends vertically between the first and second capacitor electrodes, and extends into the lined first and second capacitor electrodes. Some embodiments include methods of forming integrated assemblies.

Abstract: High density integrated circuit (IC) capacitor structures and fabrication methods that increase the capacitive density of integrated capacitors with little or no reduction in Q-factor by using a stacked high-density integrated capacitor structure that includes substrate-contact (“S-contact”) capacitor plates. Embodiments include a plurality of S-contact plates fabricated in electrical connection with a capacitor formed in a metal interconnect layer. Some embodiments include interstitial S-contact plates to provide additional capacitive density. Embodiments may also utilize single-layer transfer (SLT) and double-layer transfer (DLT) techniques to create ICs with high density, high Q-factor capacitors. Such capacitors can be beneficially combined with other structures made possible in SLT and DLT IC structures, such as metal interconnect layer capacitors and inductors, and one or more FETs having a conductive aligned supplemental gate.

Abstract: A trench capacitor includes a plurality of trenches in a semiconductor substrate. A first polysilicon layer is located within the plurality of trenches and over a top surface of the substrate. The first polysilicon layer is continuous between the plurality of trenches. The trench capacitor further includes a plurality of second polysilicon layers. Each of the second polysilicon layers fills a corresponding trench of the plurality of trenches. The second polysilicon layers each extend to a top surface of the first polysilicon layer.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate including a central array area and a marginal array area surrounding the central array area, a first bit line positioned above the central array area, a second bit line positioned above the central array area and higher than and offset from the first bit line, a first dummy bit line positioned above the marginal array area, and a second dummy bit line positioned directly above the first dummy bit line.

Abstract: A memory stack comprises at least two memory components. The memory components have a first data link interface and are to transmit signals on a data link coupled to the first data link interface at a first voltage level. A buffer component has a second data link interface coupled to the data link. The buffer component is to receive signals on the second data link interface at the first voltage level. A level shifting latch produces a second voltage level in response to receiving the signals at the second data link interface, where the second voltage level is higher than the first voltage level.

Abstract: The present disclosure relates to a semiconductor package, which includes a carrier, a flip-chip die, a mold compound, and a heat spreader. Herein, the flip-chip die includes a device layer over the carrier and a die substrate over the device layer. The mold compound resides over the carrier and surrounds the flip-chip die. The mold compound has a recess adjacent to the flip-chip die, and the recess extends vertically lower than a top surface of the die substrate. The heat spreader hangs over the flip-chip die, and includes a spreader body that is thermally coupled to the die substrate, and a spreader protrusion that extends from the spreader body into the recess. A thickness of the spreader protrusion is shorter than a depth of the recess, and a width of the spreader protrusion is narrower than a width of the recess, such that the spreader protrusion is floating in the recess.

Abstract: An IC device includes a simultaneously formed capacitor and resistor structure. The capacitor and resistor may be located between a Back End of the Line (BEOL) interconnect stack and an external device interconnect pad of the IC device. The resistor may be used to step down a voltage applied across the resistor. The resistor may include one or more resistor plates that are formed simultaneously with a respective one or more plates of the capacitor. For example, a capacitor plate and a resistor plate may be patterned and formed from the same conductive sheet. Each of the resistor plates may be connected to one or more vertical interconnect accesses (VIA).

Abstract: The present application has disclosed an MIM capacitor of an embedded structure, wherein an interlayer film is formed between a first metal wire layer and a second metal wire layer; the MIM capacitor is formed on the surface of the interlayer film; a capacitor lower electrode is connected to the first metal wire layer by means of a bottom first via, the first metal wire layer is connected, by means of a second via outside the capacitor lower electrode, to a lower electrode lead-out structure formed by the second metal wire layer; and an upper electrode lead-out structure formed by the second metal wire layer covers the surface of the capacitor upper electrode of the MIM capacitor. The present application has further disclosed a method for manufacturing an MIM capacitor of an embedded structure. In the present application, the performance and stability of the capacitor can be improved.

Abstract: Apparatus and methods relating to heterolithic microwave integrated circuits HMICs are described. An HMIC can include different semiconductor devices formed from different semiconductor systems in different regions of a same substrate. An HMIC can also include bulk regions of low-loss electrically-insulating material extending through the substrate and located between the different semiconductor regions. Passive RF circuit elements can be formed on the low-loss electrically-insulating material.

Abstract: In an embodiment, a method includes: dispensing a first dielectric layer around and on a first metallization pattern, the first dielectric layer including a photoinsensitive molding compound; planarizing the first dielectric layer such that surfaces of the first dielectric layer and the first metallization pattern are planar; forming a second metallization pattern on the first dielectric layer and the first metallization pattern; dispensing a second dielectric layer around the second metallization pattern and on the first dielectric layer, the second dielectric layer including a photosensitive molding compound; patterning the second dielectric layer with openings exposing portions of the second metallization pattern; and forming a third metallization pattern on the second dielectric layer and in the openings extending through the second dielectric layer, the third metallization pattern coupled to the portions of the second metallization pattern exposed by the openings.

Abstract: Methods of forming a 3-dimensional metal-insulator-metal super high density (3D-MIM-SHD) capacitor and semiconductor device are disclosed herein. A method includes depositing a base layer of a first dielectric material over a semiconductor substrate and etching a series of recesses in the base layer. Once the series of recesses have been etched into the base layer, a series of conductive layers and dielectric layers may be deposited within the series of recesses to form a three dimensional corrugated stack of conductive layers separated by the dielectric layers. A first contact plug may be formed through a middle conductive layer of the corrugated stack and a second contact plug may be formed through a top conductive layer and a bottom conductive layer of the corrugated stack. The contact plugs electrically couple the conductive layers to one or more active devices of the semiconductor substrate.

Abstract: Described examples include a microelectronic device with a high voltage capacitor that includes a high voltage node, a low voltage node, a first dielectric disposed between the low voltage node and the high voltage node, a first conductive plate disposed between the first dielectric and the high voltage node, and a second dielectric disposed between the first conductive plate and the high voltage node.

Abstract: A semiconductor device includes an integrated trench capacitor in a substrate, with a field oxide layer on the substrate. The trench capacitor includes trenches extending into semiconductor material of the substrate, and a capacitor dielectric in the trenches on the semiconductor material. The trench capacitor further includes an electrically conductive trench-fill material on the capacitor dielectric. A portion of the capacitor dielectric extends into the field oxide layer, between a first segment of the field oxide layer over the trench-fill material and a second segment of the field oxide layer over the semiconductor material. The integrated trench capacitor has a trench contact to the trench-fill material in each of the trenches, and substrate contacts to the semiconductor material around the trenches, with no substrate contacts between the trenches.

Abstract: A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.

Abstract: A capacitor structure for an integrated circuit (IC) is provided. The capacitor structure includes a plurality of spaced metal pillars with each metal pillar positioned on a corresponding underlying metal wire of an underlying metal layer. A metal-insulator-metal layer is positioned over and between the metal pillars. At least one contact is operatively coupled to a first metal pillar of the plurality of metal pillars. The metal-insulator-metal layer creates a MIM capacitor that undulates over the metal pillars, creating a higher density capacitance compared to conventional planar MIM capacitors. The metal pillars extend into the metal-insulator-metal layer, which reduces contact resistance. The capacitor structure can be integrated into an IC with no major integration issues. A related method is also provided.

Abstract: A semiconductor device and methods for making the same are disclosed. The device may include: a first transistor structure; a second transistor structure; a capacitor structure comprising a trench in the substrate between the first and second transistor structures, the capacitor structure further comprising a doped layer over the substrate, a dielectric layer over the doped layer, and a conductive fill material over the dielectric layer; a first conductive contact from the first transistor structure to a first bit line; a second conductive contact from the second transistor to a non-volatile memory element; and a third conductive contact from the non-volatile memory element to a second bit line.

Abstract: A semiconductor device includes a substrate. The semiconductor device further includes a circuit layer over the substrate. The semiconductor device further includes a test line on the circuit layer. The semiconductor device further includes a capacitor on the substrate. The capacitor includes a first conductor, wherein the first conductor is on a portion of the substrate exposed by the circuit layer; a second conductor; and an insulator between the first conductor and the second conductor, wherein the insulator surrounds the first conductor and the second conductor.

Abstract: A method used in forming integrated circuitry comprises forming an array of structures elevationally through a stack comprising first and second materials. The structures project vertically relative to an outermost portion of the first material. Energy is directed onto vertically-projecting portions of the structures and onto the second material in a direction that is angled from vertical and that is along a straight line between immediately-adjacent of the structures to form openings into the second material that are individually between the immediately-adjacent structures along the straight line. Other embodiments, including structure independent of method, are disclosed.

Abstract: A package that includes a substrate, an integrated device coupled to the substrate, and a capacitor structure located between the substrate and the integrated device. The capacitor structure includes a capacitor substrate comprising a first trench, a first electrically conductive layer located in the first trench, a dielectric layer located over the first electrically conductive layer, and a second electrically conductive layer located over the dielectric layer. The first electrically conductive layer over the first trench, the dielectric layer and the second electrically conductive layer are configured as a first capacitor.

Abstract: A semiconductor device includes a semiconductor substrate SUB, a semiconductor layer EP formed on the semiconductor substrate SUB, a buried layer PBL formed between the semiconductor layer EP and the semiconductor substrate SUB, an isolation layer PiSO formed in the semiconductor layer EP so as to be in contact with the buried layer PBL, and a conductive film FG formed over the isolation layer PiSO via an insulating film IF, whereby a first capacitive element including the conductive film FG as an upper electrode, the insulating film IF as a capacitive insulating film, and the isolation layer PiSO as a lower electrode, is formed over the semiconductor substrate SUB.

Abstract: The present disclosure relates to an apparatus that includes a bottom electrode and a dielectric structure. The dielectric structure includes a first dielectric layer on the bottom electrode and the first dielectric layer has a first thickness. The apparatus also includes a blocking layer on the first dielectric layer and a second dielectric layer on the blocking layer. The second dielectric layer has a second thickness that is less than the first thickness. The apparatus further includes a top electrode over the dielectric structure.

Abstract: An integrated resistor-capacitor (RC) structure (400) is disclosed. The integrated RC structure includes a vertical capacitor (302,402,306) and a resistive element (308,310) disposed above the capacitor. The integrated RC structure uses a low ohmic substrate (302) to ensure a good ground return path for the capacitor. Further, a resistivity of the substrate is configured such that a top plate (306) of the capacitor provides a reference ground above a predefined frequency. The impedance of the resistive element (308,310) is matched, relative to the reference ground, to a predetermined resistance. As such, the resistance of the resistive element (308,310) can be controlled to provide an impedance controlled RC structure over a range of operating frequencies.

Abstract: An electronic component includes a body, a pair of external electrodes, disposed on both ends of the body in a first direction, respectively, containing at least one of copper and nickel, while not containing a noble metal, a pair of metal frames connected to the pair of external electrodes, respectively, and a pair of conductive bonding layers, disposed between the external electrode and the metal frame, respectively, containing the same metal component as the external electrode.

Abstract: A capacitor interposer layer (CIL) in a die-to-wafer three dimensional integrated circuit (3DIC) and methods of forming the same are disclosed. A CIL is formed in a wafer under a power distribution network (PDN) die area of a chip. Electrical connections between the wafer and the chip are formed using a copper-to-copper bond. This placement allows the capacitor to be close to the PDN die area within the chip to reduce equivalent series resistance (ESR) and equivalent series inductance (ESL), while permitting a relatively low profile device with reduced PDN voltage droop.

Abstract: A semiconductor device includes a substrate, a storage node electrode disposed on the substrate, a dielectric layer at least partially covering the storage node electrode, and a plate electrode dispose on the dielectric layer. The storage node electrode has a pillar shape, and includes a seam disposed therein. The storage node electrode includes a concave side surface disposed at a higher level than the seam.

Abstract: A metal capacitor provided includes a first metal layer and a second metal layer disposed above a substrate. The first metal layer includes a first electrode sheet and a second electrode sheet, and the second metal layer includes a third electrode sheet and a fourth electrode sheet. The first electrode sheet and the second electrode sheet collectively form a first coplanar capacitor. The third electrode sheet and the fourth electrode sheet collectively form a second coplanar capacitor. At least a portion of the fourth electrode sheet is arranged above the first electrode sheet, and the first electrode sheet and the fourth electrode sheet collectively form a first vertical capacitor. At least a portion of the third electrode sheet is arranged above the second electrode sheet, and the second electrode sheet and the third electrode sheet collectively form a second vertical capacitor.

Abstract: A method of manufacturing a semiconductor structure includes: providing a substrate; forming a first conductive layer having a first opening over the substrate; depositing a first dielectric layer over the first conductive layer and covering the first opening; forming a second conductive layer having a second opening over the first dielectric layer; depositing a second dielectric layer over the second conductive layer and covering the second opening; performing an etching operation through the second dielectric layer at the second opening and the first dielectric layer at the first opening to form a first via; and forming a first conductive structure in the first via.

Abstract: Dielectric patterns may be additionally disposed in margin portions, and thicknesses of the dielectric patterns may be controlled to improve the reliability of a capacitor component.

Abstract: Semiconductor devices and methods of forming the same are provided. A method according to an embodiment includes receiving a substrate including a lower contact feature, depositing a first dielectric layer over a substrate, forming a metal-insulator-metal (MIM) structure over the first dielectric layer, depositing a second dielectric layer over the MIM structure, performing a first etch process to form an opening that extends through the second dielectric layer to expose the MIM structure, performing a second etch process to extend the opening through the MIM structure to expose the first dielectric layer; and performing a third etch process to further extend the opening through the first dielectric layer to expose the lower contact feature. Etchants of the first etch process and the third etch process include fluorine while the etchant of the second etch process is free of fluorine.

Abstract: In an embodiment, a method for forming features for semiconductor processing. A first mandrel and a second mandrel are formed on a substrate. A first spacer is formed along a first sidewall of the first mandrel, and a second spacer is formed along a second sidewall of the second mandrel. A gap is defined between the first spacer and the second spacer. The gap is filled by a gap-filling material. In some examples, the gap-filling material includes a doped silicon material. In some examples, the first spacer and the second spacer each include a doped silicon material.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first conductive structure passing through the substrate. The semiconductor device structure includes a conductive shielding structure passing through the substrate and surrounding the first insulating layer. The semiconductor device structure includes a second insulating layer passing through the substrate and surrounding the conductive shielding structure. The semiconductor device structure includes a second conductive structure passing through the substrate. The semiconductor device structure includes a third insulating layer passing through the substrate and surrounding the second conductive structure. The semiconductor device structure includes a conductive layer passing through the first insulating layer.

Abstract: According to an example embodiment of the present inventive concept, a semiconductor device includes a substrate. A first insulating layer is disposed on the substrate. A thin-film resistor is disposed in the first insulating layer. A capacitor structure is disposed on the first insulating layer and includes a first electrode pattern, a first dielectric pattern, a second electrode pattern, a second dielectric pattern and a third electrode pattern sequentially stacked. A first via is connected to the first electrode pattern and the third electrode pattern. A part of the first via is disposed in the first insulating layer. A second via is connected to the second electrode pattern, and a third via is connected to the thin-film resistor.