Abstract: An integrated circuit (IC) includes a substrate having a semiconductor surface layer with functional circuitry for realizing at least one circuit function, with an inter level dielectric (ILD) layer on a metal layer that is above the semiconductor surface layer. A thin film resistor (TFR) including a TFR layer is on the ILD layer. At least one vertical metal wall is on at least two sides of the TFR. The metal walls include at least 2 metal levels coupled by filled vias. The functional circuitry is outside the metal walls.

Abstract: A semiconductor device includes: a substrate; a first wiring layer arranged above the substrate; a first insulating film covering the first wiring layer; a lower oxidation preventing film arranged on the first insulating film; at least one thin-film resistor arranged on the lower oxidation preventing film; an upper oxidation preventing film arranged on the at least one thin-film resistor; a second insulating film covering the lower oxidation preventing film, the at least one thin-film resistor, and the upper oxidation preventing film; a second wiring layer arranged on the second insulating film; and a third insulating film covering the second wiring layer. The first wiring layer overlaps an end portion of the at least one thin-film resistor when viewed in a normal direction of one surface of the substrate.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an ultra-high voltage resistor and methods of manufacture. The structure includes at least one resistor coupled to a well of a doped substrate, the at least one resistor being separated vertically from the well by an isolation region with one end of the resistor being attached to an input pad and another end coupled to circuitry.

Abstract: A technique relates to forming resistor fins on a substrate. A shallow trench isolation material is formed on dummy fins and the substrate, and the dummy fins are formed on the substrate. Predefined ones of the dummy fins are removed, thereby forming voids in the shallow trench isolation material corresponding to previous locations of the predefined ones of the dummy fins. A first material is deposited into the voids. The height of the first material is reduced, thereby forming trenches in the shallow trench isolation material. A second material is deposited into the trenches to be on top of the first material, thereby forming the resistor fins of a resistor device. A metal contact layer is formed so as to contact a top surface of the first material at predefined locations.

Abstract: A resistive element includes: a resistive layer having a rectangular shape defined by a resistance length direction and a resistance width direction orthogonal to the resistance length direction; a first outer contact and a first inner contact allocated on one side of the resistive layer defined in the resistive length direction; and a second outer contact and a second inner contact allocated on another side of the resistive layer defined in the resistive length direction, wherein, as viewed in the resistance length direction, the first inner contact is shifted from the second inner contact, the first inner contact is at least partly opposed to the second outer contact, and the second inner contact is at least partly opposed to the first outer contact.

Abstract: A method of forming a vertical fin field effect transistor (vertical finFET) with a self-aligned shallow trench isolation region, including forming a pinch-off layer on one or more vertical fin segments, wherein the pinch-off layer has a thickness on the sidewalls of the one or more vertical fin segments, forming a trench mask layer on predetermined portions of the pinch-off layer, removing portions of the pinch-off layer not covered by the trench mask layer, where the removed portions of the pinch-off layer exposes underlying portions of the substrate, and removing at least a portion of the substrate to form one or more isolation region trenches, where the distance of the sidewall of one of the one or more isolation region trenches to an adjacent vertical fin segment is determined by the thickness of the pinch-off layer.

Abstract: A semiconductor device includes dummy gate structures formed on a dielectric layer over a substrate and forming a gap therebetween. A trench silicide structure is formed in the gap on the dielectric layer and extends longitudinally beyond the gap on end portions. The trench silicide structure forms a resistive element. Self-aligned contacts are formed through an interlevel dielectric layer and land on the trench silicide structure beyond the gap on the end portions.

Abstract: A PIN diode is formed on an insulating structure on a substrate of semiconductor. The insulating structure is disposed on a high voltage doped region in the substrate. The PIN diode includes a semiconductor layer, disposed on the insulating structure. The semiconductor layer includes a first doped region of a first conductivity type, at least one second doped region of a second conductivity type, and at least one intrinsic region without being doped or lightly doped between the first doped region and the at least one second doped region. The first conductive type is opposite to the second conductivity type. At least one interconnection structure is disposed on the insulating structure to electrically connect the at least one intrinsic region to the high voltage doped well.

Abstract: A method of forming a vertical fin field effect transistor (vertical finFET) with a self-aligned shallow trench isolation region, including forming a pinch-off layer on one or more vertical fin segments, wherein the pinch-off layer has a thickness on the sidewalls of the one or more vertical fin segments, forming a trench mask layer on predetermined portions of the pinch-off layer, removing portions of the pinch-off layer not covered by the trench mask layer, where the removed portions of the pinch-off layer exposes underlying portions of the substrate, and removing at least a portion of the substrate to form one or more isolation region trenches, where the distance of the sidewall of one of the one or more isolation region trenches to an adjacent vertical fin segment is determined by the thickness of the pinch-off layer.

Abstract: A semiconductor device includes dummy gate structures formed on a dielectric layer over a substrate and forming a gap therebetween. A trench silicide structure is formed in the gap on the dielectric layer and extends longitudinally beyond the gap on end portions. The trench silicide structure forms a resistive element. Self-aligned contacts are formed through an interlevel dielectric layer and land on the trench silicide structure beyond the gap on the end portions.

Abstract: A semiconductor device includes dummy gate structures formed on a dielectric layer over a substrate and forming a gap therebetween. A trench silicide structure is formed in the gap on the dielectric layer and extends longitudinally beyond the gap on end portions. The trench silicide structure forms a resistive element. Self-aligned contacts are formed through an interlevel dielectric layer and land on the trench silicide structure beyond the gap on the end portions.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a logic region and high-voltage (HV) region; forming a first gate structure on the logic region and a second gate structure on the HV region; forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; forming a patterned hard mask on the HV region; and transforming the first gate structure into a metal gate.

Abstract: An integrated circuit includes a first transistor including a first current electrode, a second current electrode, and a bulk tie; a first conductive line coupled between the first current electrode and a first supply voltage; and a second conductive line coupled to the second current electrode. A resistance of the second conductive line is at least 5 percent greater than a resistance of the first conductive line. The bulk tie is coupled to a second supply voltage. The first supply voltage is different than the second supply voltage.

Abstract: A semiconductor device includes dummy gate structures formed on a dielectric layer over a substrate and forming a gap therebetween. A trench silicide structure is formed in the gap on the dielectric layer and extends longitudinally beyond the gap on end portions. The trench silicide structure forms a resistive element. Self-aligned contacts are formed through an interlevel dielectric layer and land on the trench silicide structure beyond the gap on the end portions.

Abstract: An embedded resistor including a first interdielectric layer, a cap layer, a resistive layer and a cap film is provided. The first interdielectric layer is located on a substrate. The cap layer is located on the first interdielectric layer, wherein the cap layer has a trench. The resistive layer conformally covers the trench, thereby having a U-shaped cross-sectional profile. The cap film is located in the trench and on the resistive layer, or, an embedded thin film resistor including a first interdielectric layer, a cap layer and a bulk resistive layer is provided. The first interdielectric layer is located on a substrate. The cap layer is located on the first interdielectric layer, wherein the cap layer has a trench. The bulk resistive layer is located in the trench.

Abstract: Among other things, one or more semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. A layer, such as a poly layer or an inter layer dielectric (ILD) layer, is formed over a substrate. A photoresist mask is formed over the layer. The photoresist mask comprises an open region overlaying a target region of the layer and comprises a protection region overlaying a second region of the layer. An etching process is performed through the open region to reduce a height of the layer in the target region in relation to a height of the layer in the second region because the protection region inhibits the etching process from affecting the layer in the second region. A first structure, having a first height, is formed within the target region. A second structure, having a second height greater than the first height, is formed within the second region.

Abstract: Various embodiments include resistor structures. Particular embodiments include a resistor structure having multiple oxide layers, at least one of which includes a modified oxide. The modified oxide can aid in controlling the thermal capacitance and the thermal time constant of the resistor structure, or the thermal dissipation within the resistor structure.

Abstract: Use of a replacement metal gate (RMG) process provides an opportunity to create precision polysilicon resistors alongside metal gate transistors. During formation of a sacrificial polysilicon gate, the precision polysilicon resistor can also be formed from the same polysilicon film. The polysilicon resistor can be slightly recessed so that a protective insulating layer can cover the resistor during subsequent replacement of the sacrificial gate with a metal gate. The final structure of the precision polysilicon resistor fabricated using such a process is more compact and less complex than existing structures that provide metal resistors for integrated circuits having metal gate transistors. Furthermore, the precision polysilicon resistor can be freely tuned to have a desired sheet resistance by either implanting the polysilicon film with dopants, adjusting the polysilicon film thickness, or both.

Abstract: A method for forming a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, forming a transistor having a polysilicon dummy gate in the transistor region and a polysilicon main portion with two doped regions positioned at two opposite ends in the resistor region, performing an etching process to remove the polysilicon dummy gate to form a first trench and remove portions of the doped regions to form two second trenches, and forming a metal gate in the first trench to form a transistor having the metal gate and metal structures respectively in the second trenches to form a resistor.

Abstract: An electronic device includes: a base layer; a first layer located at least partially over the base layer; a second layer located at least partially over the first layer; a first metal layer located at least partially over the second layer, wherein one or more signal outputs of the electronic device are formed in the first metal layer; and a second metal layer located at least partially over the first metal layer, wherein one or more gate connection is formed in the second metal layer, wherein removing a portion of the second metal layer disrupts at least one gate connection and deactivates the device.

Abstract: At least one three dimensional semiconductor fin is formed from a top semiconductor material of a substrate. A dielectric material is formed along vertical sidewalls and an upper surface of the at least one three dimensional semiconductor fin. A polysilicon resistor is formed on exposed surfaces of the dielectric material and surrounding the at least one semiconductor fin. An interconnect dielectric material is formed above the polysilicon resistor. The interconnect dielectric material has at least one contact structure that extends through the interconnect dielectric to an upper surface of the polysilicon resistor.

Abstract: Disclosed is a semiconductor device. The semiconductor device includes a functional circuit having a resistor formed by a plurality of polysilicon resistors, and in which the property of the functional circuit can be adjusted by trimming the resistor, and in which the polysilicon resistors are coupled in series or in parallel to each other and arranged in a direction perpendicular to one side of the semiconductor device.

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.

Abstract: Controlled localized defect paths for resistive memories are described, including a method for forming controlled localized defect paths including forming a first electrode forming a metal oxide layer on the first electrode, masking the metal oxide to create exposed regions and concealed regions of a surface of the metal oxide, and altering the exposed regions of the metal oxide to create localized defect paths beneath the exposed regions.

Abstract: A semiconductor device includes first and second wells formed side by side as impurity diffusion regions of a first conductive type in a semiconductor substrate, below an intermediate dielectric film that covers a major surface of the substrate. A conductive layer formed above the intermediate dielectric film is held at a potential. A first resistive layer is formed on the intermediate dielectric film and is electrically connected to the first well. A second resistive layer is formed on the intermediate dielectric film and is electrically connected to the second well. The first resistive layer and first well form a first resistance element. The second resistive layer and second well form a second resistance element.

Abstract: A fin resistor and method of fabrication are disclosed. The fin resistor comprises a plurality of fins arranged in a linear pattern with an alternating pattern of epitaxial regions. An anneal diffuses dopants from the epitaxial regions into the fins. Contacts are connected to endpoint epitaxial regions to allow the resistor to be connected to more complex integrated circuits.

Abstract: A Silicon on Insulator (SOI) Integrated Circuit (IC) chip with devices such as a vertical Silicon Controlled Rectifier (SCR), vertical bipolar transistors, a vertical capacitor, a resistor and/or a vertical pinch resistor and method of making the device(s). The devices are formed in a seed hole through the SOI surface layer and insulator layer to the substrate. A buried diffusion, e.g., N-type, is formed through the seed hole in the substrate. A doped epitaxial layer is formed on the buried diffusion and may include multiple doped layers, e.g., a P-type layer and an N-type layer. Polysilicon, e.g., P-type, may be formed on the doped epitaxial layer. Contacts to the buried diffusion are formed in a contact liner.

Abstract: Provided is a high voltage semiconductor device. The semiconductor device includes a doped well located in a substrate that is oppositely doped. The semiconductor device includes a dielectric structure located on the doped well. A portion of the doped well adjacent the dielectric structure has a higher doping concentration than a remaining portion of the doped well. The semiconductor device includes an elongate polysilicon structure located on the dielectric structure. The elongate polysilicon structure has a length L. The portion of the doped well adjacent the dielectric structure is electrically coupled to a segment of the elongate polysilicon structure that is located away from a midpoint of the elongate polysilicon structure by a predetermined distance that is measured along the elongate polysilicon structure. The predetermined distance is in a range from about 0*L to about 0.1*L.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation (STI) on the substrate of the resistor region; forming a tank in the STI of the resistor region; and forming a resistor in the tank and on the surface of the STI adjacent to two sides of the tank.

Abstract: Use of a replacement metal gate (RMG) process provides an opportunity to create precision polysilicon resistors alongside metal gate transistors. During formation of a sacrificial polysilicon gate, the precision polysilicon resistor can also be formed from the same polysilicon film. The polysilicon resistor can be slightly recessed so that a protective insulating layer can cover the resistor during subsequent replacement of the sacrificial gate with a metal gate. The final structure of the precision polysilicon resistor fabricated using such a process is more compact and less complex than existing structures that provide metal resistors for integrated circuits having metal gate transistors. Furthermore, the precision polysilicon resistor can be freely tuned to have a desired sheet resistance by either implanting the polysilicon film with dopants, adjusting the polysilicon film thickness, or both.

Abstract: A phase change memory device that utilizes a nanowire structure. Usage of the nanowire structure permits the phase change memory device to release its stress upon amorphization via the minimization of reset resistance and threshold resistance.

Abstract: A metal gate process includes the following steps. An isolating layer on a substrate is provided, where the isolating layer has a first recess and a second recess. A first metal layer covering the first recess and the second recess is formed. A material is filled in the first recess but exposing a top part of the first recess. The first metal layer in the top part of the first recess and in the second recess is simultaneously removed. The material is removed. A second metal layer and a metal gate layer in the first recess and the second recess are sequentially filled.

Abstract: An adjustable resistor formed on a first insulating layer of a substrate, including: a first polysilicon layer covered with a second insulating layer of a first thickness, except in a region where the first polysilicon layer is covered with a thin insulator layer of a second thickness smaller than the first thickness; a second polysilicon layer covering the second insulating layer and the thin insulator layer; on each side of the second insulating layer and at a distance from it, a first and a second conductive vias providing access to the terminals of the resistor on the first polysilicon layer; and a third conductive via providing access to a contacting area on the second polysilicon layer.

Abstract: It is possible to suppress a change in a resistance value caused by a potential of a semiconductor substrate 10 near a resistance element layer 13, a power line passing on or above the resistance element layer, or a signal line, without generating useless current or a distortion in a signal. A first conductive layer 15 biased by the potential of a first electrode 11 and a second conductive layer 16 biased by the potential of a second electrode 12 cover below the resistance element layer equally. A change in the resistance value caused by a potential difference between the resistance element layer and a neighboring semiconductor substrate 14 is cancelled by the first conductive layer and the second conductive layer covering at least one of above and below the resistance element layer with both ends biased, so the change in the resistance value is suppressed.

Abstract: A method of manufacturing a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, a transistor is positioned in the transistor region and a resistor is positioned in the resistor region; forming a dielectric layer exposing tops of the transistor and the resistor on the substrate; performing a first etching process to remove portions of the resistor to form two first trenches respectively at two opposite ends of the resistor; forming a patterned protecting layer in the resistor region; performing a second etching process to remove a dummy gate of the transistor to form a second trench in the transistor region; and forming a metal layer filling the first trenches and the second trench.

Abstract: Provided is a high voltage semiconductor device that includes a PIN diode structure formed in a substrate. The PIN diode includes an intrinsic region located between a first doped well and a second doped well. The first and second doped wells have opposite doping polarities and greater doping concentration levels than the intrinsic region. The semiconductor device includes an insulating structure formed over a portion of the first doped well. The semiconductor device includes an elongate resistor device formed over the insulating structure. The resistor device has first and second portions disposed at opposite ends of the resistor device, respectively. The semiconductor device includes an interconnect structure formed over the resistor device. The interconnect structure includes: a first contact that is electrically coupled to the first doped well and a second contact that is electrically coupled to a third portion of the resistor located between the first and second portions.

Abstract: Controlled localized defect paths for resistive memories are described, including a method for forming controlled localized defect paths including forming a first electrode forming a metal oxide layer on the first electrode, masking the metal oxide to create exposed regions and concealed regions of a surface of the metal oxide, and altering the exposed regions of the metal oxide to create localized defect paths beneath the exposed regions.

Abstract: A semiconductor device having a transistor circuit and a bleeder resistance circuit is provided in which fluctuations in resistance value of a bleeder resistor are reduced. In the transistor circuit, a barrier metal film and a interconnect film are layered as a metal film on an interlayer insulating film above transistor structure. In the bleeder resistance circuit, the interconnect film is layered as a metal film on the interlayer insulating film above the bleeder resistor formed from polysilicon film. Alternatively, the metal film in the bleeder resistance circuit includes the barrier metal film only in a portion where the metal film is connected to the bleeder resistor. This reduces stress to the bleeder resistor formed from a polysilicon film, and the resistance value of the bleeder resistor accordingly fluctuates less. In addition, since the metal film used as interconnect of the transistor circuit includes the barrier metal film, interconnect reliability is not impaired.

Abstract: A semiconductor device including a substrate, an insulation film being embedded into the substrate and having multiple openings, multiple dummy diffusion layers formed in the substrate and located in the openings, multiple resistance elements being formed over the insulation film so as not to overlap the dummy diffusion layers in a plan view in a resistance element forming region and extending in a first direction, and multiple dummy resistance elements being formed over the insulation film and the dummy diffusion layers and extending in the first direction in the resistance element forming region, in which each of the dummy resistance elements overlaps at least two dummy diffusion layers aligning in a second direction perpendicular to the first direction in a plane horizontal to the substrate in a plan view.

Abstract: The present invention relates to a polysilicon resistor, a reference voltage circuit including the same, and a method for manufacturing the polysilicon resistor. The polysilicon resistor according includes a first polysilicon resistor and at least one of second polusilicon resistors, coupled to the first polysilicon resistor in series. The first polysilicon resistor and the at least one of the second polysilicon resistors are P-type polysilicon, and a doping concentration of the first polysilicon resistor is different from a doping concentration of the at least one of the second polysilicon resistors. The polysilicon resistor formed by serially coupling the first polysilicon resistor and the at least one of the second polysilicon resistors is applied with a constant current such that a reference voltage or a constant voltage is generated.

Abstract: Provided is a method capable of forming a polycrystalline silicon resistor with preferable ratio accuracy so as to design a resistor circuit with high accuracy. In the method, a length of a low concentration impurity region constituting the polycrystalline silicon resistor in a longitudinal direction is varied in accordance with an occupying area of a metal portion overlapping the low concentration impurity region, thereby correcting a variation in resistance without varying an external shape and the occupying area of the resistor.

Abstract: An integrated circuit (IC) is disclosed. The IC includes a substrate with a resistor region and a resistor body disposed on the resistor region. A plurality of first resistor contact strips and a plurality of second resistor contact strips are disposed on the resistor body along a first direction. Two adjacent first and second resistor contact strips are separated by a respective one of contact strip spaces. The IC includes a plurality of first terminals and a plurality of second terminals. Each of the first terminals is coupled to a respective one of the first resistor contact strips while each of the second terminals is coupled to a respective one of the second resistor contact strips. A set of the first terminal and the second terminal forms first and second terminals of an on-chip resistor.

Abstract: It is desirable to design and manufacture electronic chips that are resistant to modern reverse engineering techniques. Disclosed is a method and device that allows for the design of chips that are difficult to reverse engineer using modern teardown techniques. The disclosed device uses devices having the same geometry but different voltage levels to create different logic devices. Alternatively, the disclosed uses devices having different geometries and the same operating characteristics. Also disclosed is a method of designing a chip using these devices.

Abstract: A process is described for integrating, on an inert substrate, a device having at least one passive component and one active component. The process comprises: deposition of a protection dielectric layer on the inert substrate; formation of a polysilicon island on the protection dielectric layer; integration of the active component on the polysilicon island; deposition of the covering dielectric layer on the protection dielectric layer and on the active component; integration of the passive component on the covering dielectric layer; formation of first contact structures in openings realised in the covering dielectric layer in correspondence with active regions of the active component; and formation of second contact structures in correspondence with the passive component. An integrated device obtained through this process is also described.

Abstract: Disclosed is a semiconductor device. The semiconductor device includes a functional circuit having a resistor formed by a plurality of polysilicon resistors, and in which the property of the functional circuit can be adjusted by trimming the resistor, and in which the polysilicon resistors are coupled in series or in parallel to each other and arranged in a direction perpendicular to one side of the semiconductor device.

Abstract: A system and method for forming a resistor system is provided. An embodiment comprises a resistor formed in a U-shape. The resistor may comprise multiple layers of conductive materials, with a dielectric layer filling the remainder of the U-shape. The resistor may be integrated with a dual metal gate manufacturing process or may be integrated with multiple types of resistors.

Abstract: A semiconductor process is provided, including following steps. A polysilicon layer is formed on a substrate. An asymmetric dual-side heating treatment is performed to the polysilicon layer, wherein a power for a front-side heating is different from a power for a backside heating.

Abstract: A method of manufacturing a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, a transistor is positioned in the transistor region and a resistor is positioned in the resistor region; forming a dielectric layer exposing tops of the transistor and the resistor on the substrate; performing a first etching process to remove portions of the resistor to form two first trenches respectively at two opposite ends of the resistor; forming a patterned protecting layer in the resistor region; performing a second etching process to remove a dummy gate of the transistor to form a second trench in the transistor region; and forming a metal layer filling the first trenches and the second trench.

Abstract: The present disclosure provides a method for forming a chip structure with a resistor. A semiconductor substrate is provided and has a surface. A plurality of electronic devices and a resistor is formed on the surface of the semiconductor substrate. A plurality of dielectric layers and a plurality of circuit layers are formed over the semiconductor substrate. The dielectric layers are stacked over the semiconductor substrate and have a plurality of via holes. Each of the circuit layers is disposed on corresponding one of the dielectric layers respectively, wherein the circuit layers are electrically connected with each other through the via holes and are electrically connected to the electronic devices. A passivation layer is formed over the dielectric layers and the circuit layers. A circuit line is formed over the passivation layer, wherein the circuit line passes through the passivation layer and is electrically connected to the resistor.

Abstract: The present invention provides a poly-resistor with an improved linearity. Majority charge carrier wells are provided under the poly-strips and are biased in such way that the non-linearity of the resistor is reduced. Further, when such poly-resistors are used in amplifier circuits, the gain of the amplifier remains constant against the poly-depletion effect.