Abstract: A semiconductor device with a load resistor is manufactured such that a contact is formed at both ends of the load resistor, and at least one contact is formed between the contacts, in order to prevent impurities from being generated within each contact while the contacts are being generated by etching an insulation layer phenomena of electric charge build up from occurring when an etching process fabricates an insulation layer to generate the contact in a long load resistor located under the insulation layer and insulated electrically and physically.

Abstract: The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the polycrystalline first silicon layer has a positive in temperature dependence of resist while the second polycrystalline layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.

Abstract: A semiconductor device is provided, which is provided with a high resistance to surge currents. The semiconductor device comprises three N+ diffusion layers 4a, 4b, and 4c in a region surrounded by an element-separating insulating film 3a. The N+ diffusion layer 4a forms a source diffusion layer of an N-channel MOS transistor 11a, the N+ diffusion layer 4c forms a source diffusion layer of another N-channel MOS transistor 11b, and the N+ diffusion layer 4b forms drain diffusion layers for two N-channel MOS transistors 11a and 11b. That is, respective drain diffusion layers of two N-channel MOS transistors are shared. Furthermore, a ring-shaped mask insulating film 18 is formed on the N+ diffusion layer 4b. A silicide layer 6b is formed on the N+ diffusion layer 4b except the area covered by the ring-shaped mask insulating film 18.

Abstract: A semiconductor film comprising a polycrystalline semiconductor film provided on a substrate having an insulating surface. Nearly all crystal orientation angle differences between adjacent crystal grains constituting the polycrystalline semiconductor film are present in the ranges of less than 10° or 58°-62°.

Abstract: A structure for a semiconductor resistive element, applicable in particular to power components, having a high concentration substrate of the n type, a first epitaxial layer of the n type, a region of the p type arranged on said first epitaxial layer so to form the resistive element proper, a second epitaxial layer of n type grown on said first epitaxial layer to make the region of the p type a buried region, and an additional layer of the n type with a higher concentration with respect to the second epitaxial level, positioned on the embedded region. Low resistivity regions of the p type adapted to make low resistivity deep contacts for the resistor are provided. The buried region can be made either with a development that is substantially uniform in its main direction of extension or so to present, at on part of its length, a structure of adjacent subregions in marginal continuity.

Abstract: Structures for providing devices that include resistive paths specifically designed to provide a predetermined resistance between the bulk material of the device and a well tie contact. By providing a resistive path, an equivalent RC circuit is introduced to the device that allows the bulk material potential to track the gate potential, thereby advantageously lowering the threshold voltage as the device turns on and raising the threshold voltage as the device turns off. In addition, the introduction of the resistive path also allows the bulk material potential to be controlled and stabilize at an equilibrium potential between switching events.

Abstract: It is intended to provide a semiconductor device in which a fuse required conventionally is omitted and an initial resistance value can be maintained even under stress imposed due to packaging or the like, a high-accuracy bleeder resistance circuit that can maintain an accurate voltage division ratio, and a high-accuracy semiconductor device with such a bleeder resistance circuit, for example, a voltage detector or a voltage regulator. In a semiconductor device with a resistor, the resistor includes a P-type resistor made of a P-type semiconductor and an N-type resistor made of an N-type semiconductor which are combined to form one body, and the P-type resistor and the N-type resistor are placed on low and high potential sides, respectively. The P-N junction is irradiated with a laser beam or the like, whereby rectification is damaged to allow conduction.

Abstract: To provide a semiconductor device in which reduction of a variation in resistance value of a polycrystalline silicon film resistor is promoted. In a semiconductor device and a manufacturing method therefor according to the present invention, when the polycrystalline silicon film resistor is formed, a construction thereof is achieved by determining an implantation amount of an impurity implanted into the polycrystalline silicon film resistor through a novel technique to constitute a semiconductor integrated circuit device superior in performance.

Abstract: A resistor layer (5) is formed on an isolation insulating film (4) selectively formed in a major surface (1S) of a semiconductor substrate (1). An interlayer insulation film (7) covering the resistor layer (5) has first and second plugs (9, 19) buried therein in the form of buried interconnections. The first and second plugs (9, 19) provide connection not only between an end portion of the resistor layer (5) and first and second interconnection layers (8, 18) but also between the end portion of the resistor layer (5) and the major surface (1S) of the semiconductor substrate (1).

Abstract: An apparatus and method for conditioning polysilicon circuit elements includes a supply source configured to impress a desired voltage or current upon a polysilicon circuit element including at least a polysilicon resistor for a desired signal duration. The desired voltage or current and signal duration are chosen to cause an irreversible decrease in the resistance of the polysilicon circuit element without generating enough heat to re-alloy the resistor contacts or fuse open the resistor. The process of the present invention may be selectively performed on desired ones of a number of polysilicon resistors forming an array or matrix to thereby program the array or matrix with a desired binary code. Alternatively, the process may be used to pre-condition all the resistors in an array or matrix to thereby facilitate subsequent programming thereof via conventional fusing techniques.

Abstract: A gate oxide film is formed on a surface of a semiconductor substrate. A tunnel insulating film having a thickness smaller than that of the gate insulating film is formed in a portion thereof corresponding to a tunnel region. A first silicon film having a low impurity concentration is formed on the gate insulating film. A second silicon film having an impurity concentration higher than that of the first silicon film is formed on the first silicon film so as to be connected thereto. A third silicon film is formed on the second silicon film through an insulating film. The second and third silicon films are formed into floating and control gates, respectively, thereby forming a semiconductor memory device.

Abstract: A semiconductor device comprises a first insulating layer formed on a substrate; a resistor layer formed on the first insulating layer and having a prescribed electrical resistance; a second insulating layer formed on the resistor layer; a plurality of wirings electrically connected, at positions spaced apart from each other on the resistor layer, to the resistor layer through holes formed in the second insulating layer. Further the semiconductor device comprises a heat storage layer formed in the vicinity of the resistor layer for storing heat generated when a current flows in the resistor layer Hence, even if a large current such as a surge current flows in the resistor layer, heat generated in the resistor layer can be stored in the heat storage layer provided in the vicinity of the resistor layer. Therefore, a stable and reliable semiconductor device free of the breakdown of the resistor layer can be provided.

Abstract: An inductor has a spiral aluminum track deposited on an oxide layer over a silicon substrate. The substrate is etched away to form a trench, which extends around beneath the track and provides an air gap having a low dielectric constant. The oxide layer has an inner region within the track, an outer region outside the track and a bridging region extending between the other regions. The bridging region is comprised of intact bridges and gaps therebetween, which are open to the trench and through which an etchant has access to the silicon substrate to form the trench by etching.

Abstract: A semiconductor device comprises a first insulating layer formed on a substrate; a resistor layer formed on the first insulating layer and having a prescribed electrical resistance; a second insulating layer formed on the resistor layer; a plurality of wirings electrically connected, at positions spaced apart from each other on the resistor layer, to the resistor layer through holes formed in the second insulating layer. Further the semiconductor device comprises a heat storage layer formed in the vicinity of the resistor layer for storing heat generated when a current flows in the resistor layer.

Abstract: A fabrication process and an integrated MOS device having multi-crystal silicon resisters are described. The process includes depositing a multi-crystal silicon layer on top of a single-crystal silicon body; forming silicon oxide regions on top of the multi-crystal silicon layer in zones where resistors are to be produced; depositing a metal silicide layer on top of and in contact with the multi-crystal silicon layer so as to form a double conductive layer; and shaping the conductive layer to form gate regions, of MOS transistors. During etching of the double conductive layer, the metal silicide layer on top of the silicon oxide regions is removed and the silicon oxide regions form masking regions for the multi-crystal silicon underneath, so as to form resistive regions having a greater resistivity than the gate regions.

Abstract: A radio-frequency (RF) integrated circuit is described. In one embodiment, the IC comprises multiple metal layers forming multiple transistors on a non-epitaxial substrate. The transistors are step and mirror symmetric. Also, the RF signal lines are on a top metal layer above all other metal layers and the power and ground planes are on a bottom metal layer below all other metal layers. The top and bottom metal layers are separated by a shield that extends beyond the RF signal lines by a distance that is at least the same distance that the shield is away from the RF lines. Low frequency signals are on signal lines below the top metal layer.

Abstract: An integrated circuit including a resistor that at least partially overlies a first tub of semiconductor material of a first polarity, where the first tub is formed in a second tub of semiconductor material having the opposite polarity, and the second tub is formed in a semiconductor substrate having the first polarity. The second tub forms the base of a vertical bipolar transistor, the first tub forms the emitter of the transistor, and the substrate forms the collector of such transistor. Where the vertical transistor is a PNP transistor, the first tub is the emitter and consists of P-type semiconductor material, the second tub is the base, and the substrate is the collector. Preferably, the resistor is a strip of polysilicon or a set of multiple, series-connected polysilicon segments. Typically, the integrated circuit is an amplifier and the resistor is a gain-setting resistor.

Abstract: Disclosed are methods of forming resistors and diodes from semiconductive material, and static random access memory (SRAM) cells incorporating resistors, and to integrated circuitry incorporating resistors and diodes. A node to which electrical connection is to be made is provided. An electrically insulative layer is provided outwardly of the node. An opening is provided in the electrically insulative layer over the node. The opening is filled with semiconductive material which depending on configuration serves as one or both of a vertically elongated diode and resistor.

Abstract: A semiconductor chip has, at a corner area of the chip, an evaluation test circuit for evaluating the operational speed of the internal circuit of the semiconductor chip, and a reference element having a known coordinates and emitting light and/or generating heat upon energization thereof. Coordinates of a failed element found in a normal test are fixed with respect to the known coordinates of the reference element for analyzing the failed element.

Abstract: A thin film resistor element which maintains its resistance value when stress is applied such as during packaging, so that the resistor element may be used in a high precision bleeder resistor circuit to maintain an accurate voltage dividing ratio. The thin film resistor element has a P-type thin film resistor formed of a P-type semiconductor thin film and an N-type thin film resistor formed of an N-type semiconductor thin film, so that a change in resistance value when stress is applied is prevented. In a bleeder resistor circuit, a resistance value of one unit is regulated by a resistance value formed by a combination of the P-type thin film resistor and the N-type thin film resistor so that, even in the case where stress is applied, a change in resistance values of the respective resistor elements cancel out each other and an accurate voltage dividing ratio can be maintained.

Abstract: There is provided a semiconductor device in which an initial resistance value can be kept even in the case where stress is applied by packaging or the like. A thin film resistor of the semiconductor device is composed of a P-type thin film resistor made from a P-type semiconductor thin film and an N-type thin film resistor made from an N-type semiconductor thin film. Thus, a variation in a resistance value in the case where the stress is applied is prevented. Also, in a bleeder resistance circuit, a resistance value as one unit is defined by a resistance value obtained by a lamination of the P-type thin film resistor and the N-type thin film resistor. Therefore, even if the stress is applied, variations in resistance values of respective resistors are cancelled and thus an accurate voltage dividing ratio can be kept. Further, an area of the bleeder resistance circuit can be reduced.

Abstract: The present invention is disclosed a microchannel array structure embedded in a silicon substrate and a fabrication method thereof. The microchannel array structure of the present invention is formed deep inside the substrate and has high-density microscopic micro-channels. Besides, going through surface micromachining, physical and chemical properties of the silicon substrate are hardly influenced by the fabrication procedures. With microchannels buried in the substrate, the top of a microchannel array structure becomes flat, minimizing the effect of step height. That way, additional devices such as passive components, micro sensors, micro actuators and electronic devices can be easily integrated onto the microchannel array structure.

Abstract: The present invention generally relates to electrical detection of V-groove width during the fabrication of photosensitive chips, which create electrical signals from an original image, as would be found, for example, in a digital scanner or facsimile machine.

Abstract: A voltage variable resistor formed on heterojunction bipolar transistor epitaxial material includes a current channel made on emitter material. Emitter mesas separated by a recess provide the contacts for the voltage variable resistor. Each mesa is topped with emitter metal forming the resistor contacts. The emitter mesas are layered on top of the current channel that is layered atop of a base layer. The voltage variable resistor's control contact is provided by a base contact located on the base layer and separated from the current channel.

Abstract: There are provided a bleeder resistance circuit which has an accurate voltage dividing ratio, a small temperature coefficient of a resistance value, and high precision, and a semiconductor device using such a bleeder resistance circuit, which has high precision and a small temperature coefficient, such as a voltage detector or a voltage regulator. In the bleeder resistance circuit using a thin film resistor, conductors located over and under the thin film resistor are made to have substantially the same potential as the thin film resistor. Further, when polysilicon is used for the thin film resistor, the film thickness of the polysilicon thin film resistor is thinned, and an impurity introduced into the polysilicon thin film resistor is made to be a P-type. Thus, a variation in a resistance value is suppressed, and a temperature dependency of the resistance value is made small.

Abstract: A semiconductor device comprises a ladder resistor circuit formed of a polycrystal silicon film having a thickness of 500-1500 Å and a sheet resistance of 1-5 k&OHgr;/. The polycrystal silicon film is doped only with p-type impurities.

Abstract: A process for producing a semiconductor configuration includes the steps of providing a semiconductor substrate, providing a buffer oxide layer on the semiconductor substrate and providing a hard mask on the buffer oxide layer. An STI trench is etched by using the hard mask and a liner oxide layer is provided in the STI trench. The hard mask is removed to expose the buffer oxide layer and the buffer oxide layer is removed by an etching process. The buffer oxide layer is etched more rapidly than the liner oxide layer in the etching process. A gate oxide layer is provided on the semiconductor substrate. A semiconductor configuration is also provided.

Abstract: It is an object to provide a highly precise bleeder resistance circuit having an accurate voltage division ratio and a small temperature coefficient of the resistance value and a highly precise semiconductor device having a small temperature coefficient using such a bleeder resistance circuit, e.g., a semiconductor device such as a voltage detector and a voltage regulator. Such characteristic features that the potential of electric conductors on the thin film resistors and electric conductors under the thin film resistors of a bleeder resistance circuit using thin film resistors is made almost equal to the potential of respective thin film resistors and that, when polysilicon is used in the thin film resistor, the dispersion of the resistance value is controlled and the temperature dependency of the resistance value is made lower by thinning the film thickness of the polysilicon thin film resistor are constituted.

Abstract: A resistor element according to the present invention comprises a resistive layer provided on a semiconductor substrate through a first insulating film, a first wiring layer provided on the resistive layer through a second insulating film, a second wiring layer provided on the first wiring layer through a third insulating film, a first contact region including a plurality of contacts and provided in the second insulating film and the third insulating film, for electrically connecting the resistive layer to the second wiring layer and a second contact region including a plurality of contacts and provided in the second insulating film, for electrically connecting the resistive layer to said first wiring layer. The contacts of the second contact region are arranged on and along a periphery of a polygonal shape having a center registered with a center point of the first contact region.

Abstract: A semiconductor device requires a reduced cost, has a decreased substrate mounting area, and ensures that paired transistors, etc., have equivalent characteristics to each other. A separation strip 10 splits a semiconductor substrate 3 of one conductivity type into pairing regions and surrounds the semiconductor substrate, and has a high impurity concentration than a front surface side of the semiconductor substrate 3 but the same conductivity type with semiconductor substrate 3. A pair of vertical type semiconductor elements 1, 2 is disposed which shares the semiconductor substrate as a collector region, and the semiconductor elements 1, 2 comprise base regions 12, 22 of a reverse conductivity type which are formed respectively in the pairing regions and emitter regions 13, 23 of the one conductivity type which are formed within the base regions 12, 22 of the reverse conductivity type.

Abstract: A low temperature coefficient resistor (TCRL) has some unrepaired ion implant damage. The damaged portion raises the resistance and renders the resistor less sensitive to operating temperature fluctuations.

Abstract: The present invention relates to a fuse option circuit of an integrated circuit and a method thereof. More particularly it concerns a fuse option circuit comprising: a first fuse formed on a chip, which is cut by providing a larger electric current than a set value; a second fuse formed on the chip identically with the first fuse; a fuse cutting means providing a cutting current loop to the first fuse in response to a fuse cutting signal; and an option signal generating means which produces a fuse option signal by comparing resistance values of the first and second fuses. Accordingly, even if the first use is abnormally cut, the fuse option can be precisely provided by comparing the first fuse having a changed resistance after cutting process with the second fuse keeping an initial resistance value. Therefore, the reliability of a fuse option of an integrated circuit can be improved.

Abstract: A polysilicon resistor is formed using a late implant process. Low dopant concentrations on the order of 6×1019 to 3.75×1020 have shown good results. with a reduced post anneal temperature. Both the first and second order temperature coefficients (TC1 and TC2) can then be adjusted. Using electrical trimming resistors can be produced with highly linear temperature characteristics. By varying the geometries of the resistors, low trimming threshold current densities and voltages can be used to produce good results.

Abstract: Disclosed are methods of forming resistors and diodes from semiconductive material, and static random access memory (SRAM) cells incorporating resistors, and to integrated circuitry incorporating resistors and diodes. A node to which electrical connection is to be made is provided. An electrically insulative layer is provided outwardly of the node. An opening is provided in the electrically insulative layer over the node. The opening is filled with semiconductive material which depending on configuration serves as one or both of a vertically elongated diode and resistor.

Abstract: Disclosed are methods of forming resistors and diodes from semiconductive material, and static random access memory (SRAM) cells incorporating resistors, and to integrated circuitry incorporating resistors and diodes. A node to which electrical connection is to be made is provided. An electrically insulative layer is provided outwardly of the node. An opening is provided in the electrically insulative layer over the node. The opening is filled with semiconductive material which depending on configuration serves as one or both of a vertically elongated diode and resistor.

Abstract: Disclosed are methods of forming resistors and diodes from semiconductive material, and static random access memory (SRAM) cells incorporating resistors, and to integrated circuitry incorporating resistors and diodes. A node to which electrical connection is to be made is provided. An electrically insulative layer is provided outwardly of the node. An opening is provided in the electrically insulative layer over the node. The opening is filled with semiconductive material which depending on configuration serves as one or both of a vertically elongated diode and resistor.

Abstract: An SRAM cell is arranged in a semiconductor device. A metal oxide semiconductor field effect transistor is arranged in the SRAM cell. An interlayer insulating film is formed on the metal oxide semiconductor field effect transistor. A load resistor conductive layer is formed on the interlayer insulating film. In addition, a wiring conductive layer which connects the gate electrode of the metal oxide semiconductor field effect transistor to the load resistor conductive layer is provided. The resistance of the wiring conductive layer is lower than the resistance of the load resistor conductive layer. A side wall is formed between the load resistor conductive layer and the wiring conductive layer.

Abstract: The disclosure relates to the contacts of a polysilicon resistor for semiconductor integrated circuits. The polysilicon resistor has a resistor pattern of a doped polysilicon film formed on a first dielectric film on a semiconductor substrate. The first dielectric film and the polysilicon resistor pattern are overlaid with a second dielectric film. Each contact window for the polysilicon resistor pattern is opened in the second dielectric film and the polysilicon resistor pattern so as to reach the upper surface of the first dielectric film. It is preferable that the contact windows intrudes into the first dielectric film. As a result, side surfaces of the polysilicon film are exposed in each contact window. The contact windows are filled with a contact metal. The etching process for forming the contact windows does not affect the thickness of the polysilicon film, and only side surfaces of the polysilicon film make contact with the contact metal.

Abstract: A high-sheet-resistance polysilicon resistor for integrated circuits is achieved by using a two-layer polysilicon process. After forming FET gate electrodes and capacitor bottom electrodes from a polycide layer, a thin interpolysilicon oxide (IPO) layer is deposited to form the capacitor interelectrode dielectric. A doped polysilicon layer and an undoped polysilicon layer are deposited and patterned to form the resistor. The doped polysilicon layer is in-situ doped to minimize the temperature and voltage coefficients of resistivity. Since the undoped polysilicon layer has a very high resistance (infinite), the resistance is predominantly determined by the doped polysilicon layer.

Abstract: A reference voltage supply circuit is provided with a PNP transistor. The PNP transistor has an N-type well for a base formed at a surface of a P-type semiconductor substrate. The reference voltage supply circuit is further provided with a resistor element connected to an emitter of the PNP transistor. The resistor element has an N-type well for a resistor at the surface of the P-type semiconductor substrate. The well is fabricated at the same time as when the N-type well for a base is fabricated.

Abstract: A method for fabricating an anti-fuse cell using an undoped polysilicon film as a mask in defining the anti-fuse window is described. A layer of silicon oxide is provided over the surface of a semiconductor substrate. A first undoped polysilicon layer is deposited overlying the silicon oxide layer. The first undoped polysilicon layer is covered with a photoresist layer patterned to form a mask. The first undoped polysilicon layer and a portion of the silicon oxide layer are etched away where they are not covered by the mask to form a cell opening. The mask and the remaining silicon oxide within the cell opening are removed. An insulating layer is deposited over the surface of the first undoped polysilicon layer and within the cell opening. A second polysilicon layer is deposited overlying the insulating layer and doped. The second polysilicon layer is patterned to form an anti-fuse cell. Gate electrodes and source and drain regions are formed completing the fabrication of the integrated circuit device.

Abstract: A structure of combined passive elements and logic circuits on a SOI (Silicon On Insulator) wafer. By combining passive elements (including a resistor, an inductor and a capacitor) with a logic device on a SOI wafer with dual damascene technology, an extremely thick inductor that effectively reduces the resistance of the inductor can be formed while also reducing the layout area. The invention is compatible with conventional VLSI technology without increasing number of masks or process steps. Furthermore, because the resistor of the invention is composed of single crystal Si, the resistor has high stability and low noise. Therefore, the structure according to the invention is suitable for RF device design and is also suitable for a System On Chip design.

Abstract: In a semiconductor device comprising a resistance element electrically connected to a bipolar transistor, the bipolar transistor is formed on a silicon substrate and a predetermined resistance element is formed on an insulation film formed on the bipolar transistor based on results of measurements monitored for this transistor, in such a manner that the semiconductor device has prescribed characteristics.

Abstract: The present invention teaches fabrication of a high-resistance integrated circuit diffusion resistor that uses standard CMOS process steps. By appropriate masking during ion-implantation of source/drain diffusion regions, diffusion resistors created during NMOS source/drain implant may be counterdoped during PMOS source/drain implants and vice-versa. By appropriate choice of relative concentrations of a resistor dopant and counterdopant, and choice of diffusion depths, junction diodes can be formed which create a pinched resistor by constricting the current flow. The relative dopant concentrations can also be chosen to create regions of light effective doping within the diffusion resistor rather than creating junction diodes.

Abstract: A thermo-optic semiconductor device has one semiconductor region providing an optical waveguide and an adjacent semiconductor region providing a resistive heater between two doped regions, current may be passed through the resistive heater within the adjacent semiconductor region to heat it and thereby vary the optical characteristics of the waveguide.

Abstract: An SRAM cell includes six transistors and two variable resistors. A first pair of transistors form a first inverter, while a second pair of transistors form a second inverter. The remaining two transistors are pass transistors. The inverters are cross-coupled, through the variable resistors, to form a flip flop circuit which stores binary logic states. The variable resistors are formed by doping a portion of a polysilicon layer. Above the doped polysilicon resistor is a thin oxide layer. Disposed above the oxide layer is a thin layer of aluminum or polysilicon, which is connected by metallization. When a positive voltage is applied to the metallization, electrons accumulate in the doped polysilicon resistor, thereby lowering the resistance value of the polysilicon region. This voltage is applied to the interconnect during a write-in cycle, when it is desired to write data to the SRAM cell. The lowered resistance value of the polysilicon resistor allows for relatively fast write-in times for the SRAM cell.

Abstract: There is a voltage dividing circuit having a voltage dividing resistor for generating reference voltages for A/D conversion. The voltage dividing resistor further comprises a semiconductor element and, provided thereon, a resistance element, at least one capacity electrode and dielectric held therebetween. Each capacity electrode thereon is earthed. The voltage dividing resistor and the voltage dividing circuit are capable of lowering impedance of output terminals in a high frequency range, while avoiding an increase of a surface area of a chip, and undulation of impedances of output terminals in a high frequency range.

Abstract: A method of forming a transistor in a peripheral circuit of a random access memory device wherein a transistor gate, capacitor electrode or other component in the memory cell array is formed simultaneously with the formation of a transistor gate in the periphery.

Abstract: There is provided a new polysilicon fuse structure for implementation within integrated circuit devices so as to permit programming of the same. The polysilicon fuse structure includes a first electrical contact region, a second electrical contact region, and multiple fuse regions interconnected between the first electrical contact region and the second electrical contact region. The multiple fuse regions are formed of a plurality of strips, each being of a different width and/or length, which are disposed in a spaced-apart relationship so as to form a small opening between adjacent strips. A number of the plurality of strips is selectively blown when a predetermined amount of current is passed from one of the first and second electrical contact regions through the plurality of strips to the other one of the first and second electrical contact regions so to limit the current passing to an integrated circuit device connected thereto during normal operating conditions.

Abstract: A method of forming an SRAM cell includes, a) providing a pair of pull-down gates having associated transistor diffusion regions operatively adjacent thereto, one of the diffusion regions of each pull-down gate being electrically connected to the other pull-down gate; b) providing a pair of pull-up resistor nodes for electrical connection with a pair of respective pull-up resistors, the pull-up nodes being in respective electrical connection with one of the pull-down gate diffusion regions and the other pull-down gate; c) providing a first electrical insulating layer outwardly of the resistor nodes; d) providing a pair of contact openings, with respective widths, through the first insulating layer to the pair of resistor nodes; e) providing a second electrical insulating layer over the first layer and to within the pair of contact openings to a thickness which is less than one-half the open widths; f) anisotropically etching the second electrical insulating layer to define respective electrical insulating ann