Polycrystalline Silicon (doped Or Undoped) Patents (Class 257/538)
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Patent number: 7130181Abstract: A semiconductor device is disclosed which has a plurality of unit capacitive elements. At least one lead-out electrode of bottom electrodes of the unit capacitive elements of the capacitive element group is disposed along a circumference going around top electrodes as a whole of the capacitive element group, and a given capacitive element is connectable to the capacitive element group, the given capacitive element having a capacitance value that is set to eliminate effects of parasitic capacitance of at least the capacitive element group. Furthermore, the given capacitive element may consist of a capacitive element group.Type: GrantFiled: July 15, 2004Date of Patent: October 31, 2006Assignee: Sanyo Electric Co., Ltd.Inventor: Hiroshi Saito
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Patent number: 7105912Abstract: A resistor structure includes a substrate, a semiconductor layer positioned on the substrate, a salicide block positioned on portions of the surface of the semiconductor layer, and at least a salicide layer positioned on the portions of the surface of the semiconductor layer adjacent to the salicide block. The semiconductor layer has a predetermined region overlapping the salicide layer, the junction between the salicide layer and the salicide block, and the portions of the salicide block adjacent to the junction between the salicide layer and the salicide block. The semiconductor layer has a higher doping concentration within the predetermined region than in the other regions.Type: GrantFiled: September 15, 2004Date of Patent: September 12, 2006Assignee: United Microelectronics Corp.Inventors: Cheng-Hsiung Chen, Yue-Shiun Lee
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Patent number: 7091577Abstract: A voltage-dividing resistor enables a multi-step voltage division. The voltage-dividing resistor includes a polysilicon layer formed on a semiconductor substrate; a metal layer formed on a partial area of the polysilicon layer; an insulating interlayer covering the polysilicon layer and the metal layer; a first electrode for applying a first reference voltage to one end of the polysilicon layer; a second electrode for applying a second reference voltage to the other end of the polysilicon layer; a plurality of third electrodes provided between the first and second electrodes to contact the metal layer; and a plurality of fourth electrodes provided between the first and second electrodes to contact the polysilicon layer.Type: GrantFiled: December 29, 2005Date of Patent: August 15, 2006Assignee: Dongbu Electronics Co., Ltd.Inventor: Suk Kyun Lee
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Patent number: 7078786Abstract: According to one exemplary embodiment, an integrated circuit chip comprises an oxide region. The integrated circuit chip further comprises a poly resistor having a first terminal and second terminal, where the poly resistor is situated over the oxide region. According to this exemplary embodiment, the integrated circuit chip further comprises a metal resistor having a first terminal and a second terminal, where the metal resistor is situated over the poly resistor, and where the first terminal of the metal resistor is connected to the first terminal of the poly resistor. According to this exemplary embodiment, the integrated circuit chip may further comprise a first metal segment connected to the second terminal of the metal resistor and a second metal segment connected to the second terminal of the poly resistor. The integrated circuit chip may further comprise an inter-layer dielectric situated between the poly resistor and the metal resistor.Type: GrantFiled: May 10, 2004Date of Patent: July 18, 2006Assignee: Newport Fab, LLC dba Jazz SemiconductorInventors: Marco Racanelli, Chun Hu, Chih-Chieh Shen
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Patent number: 7064414Abstract: A structure and associated method for annealing a trapped charge from a semiconductor device. The semiconductor structure comprises a substrate and a first heating element. The substrate comprises a bulk layer, an insulator layer and a device layer. The first heating element is formed within the bulk layer. A first side of the first heating element is adjacent to a first portion of the insulator layer. The first heating element is adapted to be selectively activated to generate thermal energy to heat the first portion of the insulator layer and anneal a trapped electrical charge from the first portion of the insulator layer.Type: GrantFiled: November 12, 2004Date of Patent: June 20, 2006Assignee: International Business Machines CorporationInventors: John M Aitken, Ethan H. Cannon, Philip J. Oldiges, Alvin W. Strong
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Patent number: 7002235Abstract: A semiconductor device has a semiconductor support substrate, a buried insulation film disposed on the semiconductor support substrate, and a single-crystal silicon active layer disposed on the buried insulation film. The buried insulation film has portions which have been removed so that remaining portions of the buried insulating film form buried insulating film island regions. The single-crystal silicon active layer has portions which have been removed so that remaining portions of the single-crystal silicon active layer form single-crystal silicon active layer island regions defining single-crystal silicon resistors of a resistance circuit.Type: GrantFiled: March 24, 2003Date of Patent: February 21, 2006Assignee: Seiko Instruments Inc.Inventor: Hisashi Hasegawa
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Patent number: 6995452Abstract: Provided are an SOI MOSFET device with a nanoscale channel that has a source/drain region including a shallow extension region and a deep junction region formed by solid-phase diffusion and a method of manufacturing the SOI MOSFET device. In the method of manufacturing the MOSFET device, the shallow extension region and the deep junction region that form the source/drain region are formed at the same time using first and second silicon oxide films doped with different impurities. The effective channel length of the device can be scaled down by adjusting the thickness and etching rate of the second silicon oxide film doped with the second impurity. The source/drain region is formed on the substrate before the formation of a gate electrode, thereby easily controlling impurity distribution in the channel. An impurity activation process of the source/drain region can be omitted, thereby preventing a change in a threshold voltage of the device. A solid-phase impurity is diffused.Type: GrantFiled: December 30, 2003Date of Patent: February 7, 2006Assignee: Electronics and Telecommunications Research InstituteInventors: Wonju Cho, Seong Jae Lee, Jong Heon Yang, Jihun Oh, Kiju Im
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Patent number: 6965151Abstract: Structures for providing devices that include resistive paths specifically designed to provide a predetermined resistance between the bulk material of the device and a well tie contact. By providing a resistive path, an equivalent RC circuit is introduced to the device that allows the bulk material potential to track the gate potential, thereby advantageously lowering the threshold voltage as the device turns on and raising the threshold voltage as the device turns off. In addition, the introduction of the resistive path also allows the bulk material potential to be controlled and stabilize at an equilibrium potential between switching events.Type: GrantFiled: March 20, 2003Date of Patent: November 15, 2005Assignee: Sun Microsystems, Inc.Inventor: James B. Burr
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Patent number: 6958523Abstract: An integrated circuit programmable structure (60) is formed for use a trim resistor and/or a programmable fuse. The programmable structure comprises placing heating elements (70) in close proximity to the programmable structure (60) to heat the programmable structure (60) during programming.Type: GrantFiled: September 7, 2001Date of Patent: October 25, 2005Assignee: Texas Instruments IncorporatedInventors: Jeffrey A. Babcock, Angelo Pinto, Gregory E. Howard, Philipp Steinmann, Scott Balster
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Patent number: 6940152Abstract: A plurality of impurity diffusion layers working as bit lines are formed in surface portions of a semiconductor substrate, and a plurality of buried insulating films are formed above the plural impurity diffusion layers on the semiconductor substrate. Gate electrodes of memory devices include a plurality of first polysilicon films, which are formed between the buried insulating films with a trapping film formed below and have top faces at substantially the same level as top faces of the buried insulating films, and a second polysilicon film formed over the plural buried insulating films and the plural first polysilicon films for electrically connecting the plural first polysilicon films to one another.Type: GrantFiled: February 5, 2003Date of Patent: September 6, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Masatoshi Arai
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Patent number: 6933591Abstract: Programmable fuses for integrated circuits are provided. The fuses may be based on polysilicon or crystalline silicon fuse links coated with silicide or other conductive thin films. Fuses may be formed on silicon-on-insulator (SOI) substrates. A fuse may be blown by applying a programming current to the fuse link. The silicon or polysilicon in the fuses may be provided with a p-n junction. When a fuse is programmed, the silicide or other conductive film forms an open circuit. This forces current though the underlying p-n junction. Unlike conventional silicided polysilicon fuses, fuses with p-n junctions change their qualitative behavior when programmed. Unprogrammed fuses behave like resistors, while programmed fuses behave like diodes. The presence of the p-n junction allows sensing circuitry to determine in a highly accurate qualitative fashion whether a given fuse has been programmed.Type: GrantFiled: October 16, 2003Date of Patent: August 23, 2005Assignee: Altera CorporationInventors: Lakhbeer S. Sidhu, Irfan Rahim
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Patent number: 6924216Abstract: A method of forming the active regions of field effect transistors is proposed. According to the proposed method, shallow implanting profiles for both the halo structures and the source and drain regions can be obtained by carrying out a two-step damaging and amorphizing implantation process. During a first step, the substrate is damaged during a first light ion implantation step and subsequently substantially fully amorphized during a second heavy ion implantation step.Type: GrantFiled: May 19, 2003Date of Patent: August 2, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Thomas Feudel, Manfred Horstmann, Rolf Stephan
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Patent number: 6891248Abstract: A semiconductor component includes a semiconductor die, and an on board capacitor on the die for filtering transient voltages, spurious signals and power supply noise in signals transmitted to the die. The capacitor includes a first electrode in electrical communication with a first terminal contact for the component, and a second electrode in electrical communication with a second terminal contact for the component. The electrodes are separated by a dielectric layer and protected by an outer protective layer of the component. The capacitor can be fabricated using redistribution layers on a wafer containing multiple dice. The component can be used to construct systems such as multi chip packages and multi chip modules.Type: GrantFiled: August 23, 2002Date of Patent: May 10, 2005Assignee: Micron Technology, Inc.Inventors: Salman Akram, Mike Brooks
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Patent number: 6885280Abstract: A resistor structure is disclosed that is constructed out of two layers of polysilicon. The intrinsic device is made using the top layer which is either a dedicated deposition, or formed as part of an existing process step such as a base epi growth in a BiCMOS flow. This poly layer can be made with a relatively high (greater than 2000 ohms per square) sheet resistance by appropriate scaling of the implant dose or by insitu doping methods. In this invention this layer is arranged to be about 1000 A or less thick. Such a resistor form with this thickness has been shown to demonstrate a better standard; deviation of resistance compared to resistors made with a thicker layer. Additionally, practical resistors made in elongated forms demonstrate better standard deviations of resistance when five bends were incorporated into the form. The resistor ends are formed by the addition of a bottom poly layer in a self aligned manner with a deposition that may already be part of the process sequence.Type: GrantFiled: January 31, 2003Date of Patent: April 26, 2005Assignee: Fairchild Semiconductor CorporationInventor: James Michael Olson
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Patent number: 6882699Abstract: An increasing monotonic counter over n bits formed as an integrated circuit, including an assembly of 2n+1?(n+2) irreversible counting cells distributed in at least n groups of 2p?1 counting cells, where p designates the group rank, and at least n?1 parity calculators, each calculator providing a bit of rank p, increasing from the most significant bit of the result count, taking into account the states of the cells of the group of same rank.Type: GrantFiled: October 27, 2003Date of Patent: April 19, 2005Assignee: STMicroelectronics S.A.Inventors: Luc Wuidart, Claude Anguille
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Patent number: 6867473Abstract: A surface may be selectively coated with a polymer using an induced surface grafting or polymerization reaction. The reaction proceeds in those regions that are polymerizable and not in other regions. Thus, a semiconductor structure having organic regions and metal regions exposed, for example, may have the organic polymers formed selectively on the organic regions and not on the unpolymerizable or metal regions.Type: GrantFiled: November 26, 2003Date of Patent: March 15, 2005Assignee: Intel CorporationInventors: Michael D. Goodner, Grant Kloster, Steven W. Johnston
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Patent number: 6849921Abstract: A semiconductor device includes: a semiconductor substrate; a first insulating film formed on the semiconductor substrate; a polysilicon resistor film formed on the first insulating film; a second insulating film formed on the resistor film; a high heat conductor film consisting of a highly heat-conducting material formed on the second insulating film; and a pair of terminal wirings formed on the second insulating film and connected to the resistor film, in which a thickness T3 of the second insulating film is thinner than a thickness T2 of the resistor film.Type: GrantFiled: July 10, 2001Date of Patent: February 1, 2005Assignee: Renesas Technology Corp.Inventor: Akio Uenishi
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Patent number: 6849914Abstract: A thermo-optic semiconductor device has one semiconductor region providing an optical waveguide and an adjacent semiconductor region providing a resistive heater between two doped regions, current may be passed through the resistive heater within the adjacent semiconductor region to heat it and thereby vary the optical characteristics of the waveguide.Type: GrantFiled: October 30, 2002Date of Patent: February 1, 2005Assignee: Bookham Technology PLCInventor: Ian Edward Day
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Patent number: 6844610Abstract: Methods are provided for forming an integrated circuit device including a resistor pattern having a desired resistance value. A low resistive layer is formed on an integrated circuit substrate. An insulating layer is formed on the low resistive layer opposite the integrated circuit substrate. A high resistive layer, which may have a specific resistance of at least about a hundred ??•cm, is formed on the insulating layer opposite the low resistive layer. The low resistive layer, the insulating layer and the high resistive layer define the resistor pattern in a region of the integrated circuit substrate. Integrated circuit devices including resistor patterns as provided by the methods are also provided and methods for forming metal contacts to the resistor pattern are also provided.Type: GrantFiled: September 25, 2003Date of Patent: January 18, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Seok-Jun Won, Young-Wook Park
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Patent number: 6844599Abstract: A semiconductor device has thin film resistors connected in series to form a bleeder resistance circuit. Each of the thin film resistors is made of a polysilicon film doped with B or BF2 P-type impurities and has two end portions each having a high impurity concentration region. A first insulating film overlies the thin film resistors. First conductors are connected to the ends of the thin film resistors for connecting the thin film resistors in series. The semiconductor device has second conductors each connected to a respective one of the first conductors and overlying a respective one of the thin film resistors through the first insulating film.Type: GrantFiled: July 27, 2001Date of Patent: January 18, 2005Assignee: Seiko Instruments Inc.Inventors: Mika Shiiki, Hiroaki Takasu
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Patent number: 6838747Abstract: A dopant is ion-implanted into a second region (52) of a polycrystalline silicon film (50) for a resistive element (5). Nitrogen or the like is ion-implanted into a second region (62) of a polycrystalline silicon film (60) for a resistive element (6). The density of crystal defects in the second regions (52, 62) is higher than that in first regions (51, 61). The density of crystal defects in a polycrystalline silicon film (70) for a resistive element (7) is higher near a silicide film (73). A polycrystalline silicon film (80) for a resistive element (8) is in contact with a substrate (2) with a silicide film in an opening of an isolation insulating film (3). The density of crystal defects in a substrate surface (2S) near the silicide film is higher than that in the vicinity. With such a structure, a current leak in an isolation region can be reduced.Type: GrantFiled: July 11, 2002Date of Patent: January 4, 2005Assignee: Renesas Technology Corp.Inventor: Hidekazu Oda
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Publication number: 20040256695Abstract: The present invention provides a circuit arrangement to convert fixed, or grounded resistors, to floating resistors. In particular, the circuit arrangement provides for the coupling of active electrical resistance devices to provide a relatively high value electrical resistance between two non-grounded nodes of the circuit arrangement in the order of Giga-ohms. The invention further provides for the magnitude of the floating electrical resistance to be determined by the magnitude of electrical current supply thus providing a means to select the magnitude of the floating electrical resistance by selecting by selecting the magnitude of electrical current supply. The circuit arrangement requires relatively few active devices and consumes a relatively small amount of electrical power in operation.Type: ApplicationFiled: April 12, 2004Publication date: December 23, 2004Inventor: Said Al-Sarawi
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Patent number: 6828655Abstract: A semiconductor film comprising a polycrystalline semiconductor film provided on a substrate having an insulating surface. Nearly all crystal orientation angle differences between adjacent crystal grains constituting the polycrystalline semiconductor film are present in the ranges of less than 10° or 58°-62°.Type: GrantFiled: November 15, 2002Date of Patent: December 7, 2004Assignee: Sharp Kabushiki KaishaInventors: Toshio Mizuki, Yoshinobu Nakamura
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Publication number: 20040238920Abstract: A semiconductor device, a method for manufacturing the semiconductor device, and an integrated circuit including the semiconductor device are disclosed. The semiconductor device includes a substrate section, a resistor formed on the substrate section, a metal pattern formed on the resistor, an oxide pattern formed on the metal pattern, and a protective film covering the resistor, the metal pattern and the oxide pattern. With this structure, the metal pattern sufficiently prevents formation of an oxide film on a surface of the resistor even when dry ashing or dry etching is performed in the manufacturing process.Type: ApplicationFiled: May 19, 2004Publication date: December 2, 2004Inventors: Yasunori Hashimoto, Kimihiko Yamashita
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Patent number: 6815714Abstract: A conductive structure provides a conductive path from a first region in a semiconductor material to a second spaced apart region in the semiconductor material by forming one or more trenches between the first and second regions, and implanting a dopant into the bottom surfaces of the trenches to form a continuous conductive path.Type: GrantFiled: February 20, 2003Date of Patent: November 9, 2004Assignee: National Semiconductor CorporationInventors: William M. Coppock, Charles A. Dark
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Patent number: 6812486Abstract: A conductive structure provides a conductive path from a first region in a semiconductor material to a second spaced apart region in the semiconductor material by forming a plurality of trenches between the first and second regions, implanting a dopant into the bottom surfaces of the trenches, and then annealing the wafer to cause the dopant at the bottom surfaces to diffuse and form a continuous conductive path.Type: GrantFiled: February 20, 2003Date of Patent: November 2, 2004Assignee: National Semiconductor CorporationInventors: Charles A. Dark, William M. Coppock
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Patent number: 6800924Abstract: Structures for providing devices that include resistive paths specifically designed to provide a predetermined resistance between the bulk material of the device and a well tie contact. By providing a resistive path, an equivalent RC circuit is introduced to the device that allows the bulk material potential to track the gate potential, thereby advantageously lowering the threshold voltage as the device turns on and raising the threshold voltage as the device turns off. In addition, the introduction of the resistive path also allows the bulk material potential to be controlled and stabilize at an equilibrium potential between switching events.Type: GrantFiled: March 20, 2003Date of Patent: October 5, 2004Assignee: Sun Microsystems, Inc.Inventor: James B. Burr
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Publication number: 20040183157Abstract: A semiconductor device with a resistor element whose the resistance value can be adjusted to a desired value without changing dimensions thereof is provided. The resistor element is formed of a poly-Si layer formed on an insulator over a semiconductor substrate. An impurity is introduced into the poly-Si layer by the use of ion implantation. In the vicinity of both ends of the poly-Si layer forming the resistor element, silicide layers each made of cobalt silicide or the like are formed over an upper surface of the poly-Si layer. The area of one silicide layer is larger than that of the other silicide layer. By adjusting the area of the one silicide layer, the length between the silicide layers is adjusted and the resistance value of the resistor element can be adjusted without changing the shape of the poly-Si layer.Type: ApplicationFiled: January 29, 2004Publication date: September 23, 2004Applicants: Hitachi, Ltd., Hitachi Display Devices, Ltd.Inventors: Shinichiro Wada, Hiromi Shimamoto
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Patent number: 6781213Abstract: Structures for providing devices that include resistive paths specifically designed to provide a predetermined resistance between the bulk material of the device and a well tie contact. By providing a resistive path, an equivalent RC circuit is introduced to the device that allows the bulk material potential to track the gate potential, thereby advantageously lowering the threshold voltage as the device turns on and raising the threshold voltage as the device turns off. In addition, the introduction of the resistive path also allows the bulk material potential to be controlled and stabilize at an equilibrium potential between switching events.Type: GrantFiled: March 20, 2003Date of Patent: August 24, 2004Assignee: Sun Microsystems, Inc.Inventor: James B. Burr
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Publication number: 20040159910Abstract: A method of forming a Fin structure including a resistor present in the thin vertically oriented semiconductor body is provided. The method includes the steps of forming at least one vertically-oriented semiconductor body having exposed vertical surfaces on a substrate; implanting dopant ions into the exposed vertical surfaces of the at least one semiconductor body off-axis at a concentration and energy sufficient to penetrate into the exposed vertical surfaces of the at least one semiconductor body without saturation; and forming contacts to the at least one semiconductor body. The present invention is directed to a Fin structure which includes a resistor present within the thin vertically oriented semiconductor body.Type: ApplicationFiled: February 9, 2004Publication date: August 19, 2004Applicant: International Business Machines CorporationInventors: David M. Fried, Edward J. Nowak
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Patent number: 6777779Abstract: Structures for providing devices that include resistive paths specifically designed to provide a predetermined resistance between the bulk material of the device and a well tie contact. By providing a resistive path, an equivalent RC circuit is introduced to the device that allows the bulk material potential to track the gate potential, thereby advantageously lowering the threshold voltage as the device turns on and raising the threshold voltage as the device turns off. In addition, the introduction of the resistive path also allows the bulk material potential to be controlled and stabilize at an equilibrium potential between switching events.Type: GrantFiled: March 20, 2003Date of Patent: August 17, 2004Assignee: Sun Microsystems, Inc.Inventor: James B. Burr
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Publication number: 20040155316Abstract: Provided is a semiconductor reliability evaluating apparatus for evaluating an electro-migration characteristic of a wiring layer which is capable of being formed simply and in a low cost using a reticle set, having a minimum number of reticles, which is capable of measuring an ordinary via plug resistance where the number of wiring layer is two. A first wiring layer and a second wiring layer are configured so that the first wiring layer is connected to the second wiring layer with a plurality of via plugs formed in an insulating layer which is placed between the first wiring layer and the second wiring layer, the first wiring layer and the second wiring layer are made of metals having almost same specific resistances, and each different parasitic resistances are put to at least one of the first wiring layer and the second wiring layer connected to each of the plurality of via plugs to make the total resistance value of the current path through each of the plurality of via plugs different.Type: ApplicationFiled: February 10, 2004Publication date: August 12, 2004Applicant: NEC ELECTRONICS CORPORATIONInventors: Yumi Saito, Hiroshi Tsuda
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Patent number: 6770949Abstract: A system and method in accordance with the invention minimizes the redesign burden in tuning and/or customizing PLLs on ICs. Variable resistors are placed in the PLL in places that facilitate tuning. The variable resistors are formed with a set of at least three contacts, where each contact is in electrical communication with a resistive area. A metal layer is used to form leads to the resistive area, where each lead is formed to be in electrical communication with only a selected subset of contacts from the set. In one embodiment, only the uppermost metal layer used in forming the IC is used to form the leads. Because the uppermost metal layer is utilized, the resistor value can be adjusted simply by selecting the subsets of contacts that are to be in electrical communication with the uppermost metal layer. In this manner, only one metal layer needs to be adjusted in tuning and/or customizing a PLL, rather than having to redesign and re-layout all metal layers and vias in the IC.Type: GrantFiled: August 31, 1998Date of Patent: August 3, 2004Assignee: Lightspeed Semiconductor CorporationInventor: Shafy Eltoukhy
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Patent number: 6762474Abstract: A method and apparatus for temperature compensation of a resistive based Read-Only Memory device is disclosed. In accordance with the method of the invention, the input voltage supplied to ROM device is adjusted in response to changes in temperature to maintain the current through the ROM at a substantially constant level even as the resistivity of the temperature-dependent connection resistors changes. In one embodiment of the invention, the voltage across the reference resistor is determined by providing a constant current source to the reference resistor and this voltage level is applied to the input of the ROM device. The reference resistor is selected to have similar properties of conductivity as those of the data resistor, for example, a polysilicon. As the temperature increases, the resistivity of a polysilicon data resistor and resistor decrease in a similar manner and, accordingly, the voltage across the reference resistor also decreases.Type: GrantFiled: January 7, 2000Date of Patent: July 13, 2004Assignee: Agere Systems Inc.Inventor: Allen P. Mills, Jr.
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Patent number: 6759729Abstract: According to one exemplary embodiment, an integrated circuit chip comprises an oxide region. The integrated circuit chip further comprises a poly resistor having a first terminal and second terminal, where the poly resistor is situated over the oxide region. According to this exemplary embodiment, the integrated circuit chip further comprises a metal resistor having a first terminal and a second terminal, where the metal resistor is situated over the poly resistor, and where the first terminal of the metal resistor is connected to the first terminal of the poly resistor. According to this exemplary embodiment, the integrated circuit chip may further comprise a first metal segment connected to the second terminal of the metal resistor and a second metal segment connected to the second terminal of the poly resistor. The integrated circuit chip may further comprise an inter-layer dielectric situated between the poly resistor and the metal resistor.Type: GrantFiled: October 16, 2002Date of Patent: July 6, 2004Assignee: Newport Fab, LLCInventors: Marco Racanelli, Chun Hu, Bruce Shen
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Patent number: 6759726Abstract: A method of forming an isolating wall in a semiconductor substrate of a first conductivity type, including the steps of boring in the substrate separate recesses according to the desired isolating wall contour; filling the recesses with a material containing a dopant of the second conductivity type; and performing an anneal step so that regions of the second conductivity type diffused from neighboring recesses join. A first series of recesses is formed from the upper surface and a second series of recesses is formed from the lower surface. The recesses have a substantially rectangular section, the large dimension of which is perpendicular to the alignment of the recesses and a depth smaller than or equal to the half-thickness of the substrate.Type: GrantFiled: October 22, 1999Date of Patent: July 6, 2004Assignee: STMicroelectronics S.A.Inventors: Christine Anceau, Fabien Pierre, Olivier Bonnaud
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Patent number: 6750531Abstract: To provide a semiconductor device in which reduction of a variation in resistance value of a polycrystalline silicon film resistor is promoted. In a semiconductor device and a manufacturing method therefor according to the present invention, when the polycrystalline silicon film resistor is formed, a construction thereof is achieved by determining an implantation amount of an impurity implanted into the polycrystalline silicon film resistor through a novel technique to constitute a semiconductor integrated circuit device superior in performance.Type: GrantFiled: September 17, 2002Date of Patent: June 15, 2004Assignee: Seiko Instruments Inc.Inventors: Nobuo Takei, Toshihiko Omi, Keisuke Uemura
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Publication number: 20040094803Abstract: Formed on an insulator (9) are an N− type semiconductor layer (10) having a partial isolator formed on its surface and a P− type semiconductor layer (20) having a partial isolator formed on its surface. Source/drain (11, 12) being P+ type semiconductor layers are provided on the semiconductor layer (10) to form a PMOS transistor (1). Source/drain (21, 22) being N+ type semiconductor layers are provided on the semiconductor layer (20) to form an NMOS transistor (2). A pn junction (J5) formed by the semiconductor layers (10, 20) is provided in a CMOS transistor (100) made up of the transistors (1, 2). The pn junction (J5) is positioned separately from the partial isolators (41, 42), where the crystal defect is thus very small. Therefore, the leakage current is very low at the pn junction (J5).Type: ApplicationFiled: November 17, 2003Publication date: May 20, 2004Applicant: Renesas Technology Corp.Inventors: Takashi Ipposhi, Toshiaki Iwamatsu
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Patent number: 6734075Abstract: A CMOS device includes a reverse electric conduction type well (2) formed on a monoelectric conduction type semiconductor substrate (1), a first MOS transistor (3) of a reverse electric conduction type channel formed on a surface of the semiconductor substrate, and a second MOS transistor (4) of monoelectric conduction type channel is formed on a surface of the well. In the present invention, resistance elements (8R, 7R, 2R) are formed in the semiconductor substrate on a lower side of a thick field oxide film (9) covering a surface of the semiconductor substrate. Further, a second resistance element (11R) composed of a polycrystal silicon layer is formed on an upper side of the field oxide film.Type: GrantFiled: May 19, 1999Date of Patent: May 11, 2004Assignee: Mitsumi Electric Co., Ltd.Inventor: Shigeki Onodera
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Patent number: 6730984Abstract: A method and structure for increasing an electrical resistance of a resistor that is within a semiconductor structure, by oxidizing or nitridizing a fraction of a surface layer of the resistor with oxygen/nitrogen (i.e., oxygen or nitrogen) particles, respectively. The semiconductor structure may include a semiconductor wafer, a semiconductor chip, and an integrated circuit. The method and structure comprises five embodiments. The first embodiment comprises heating an interior of a heating chamber that includes the oxygen/nitrogen particles as gaseous oxygen/nitrogen-comprising molecules (e.g., molecular oxygen/nitrogen). The second embodiment comprises heating the fraction of the surface layer by a beam of radiation (e.g., laser radiation), or a beam of particles, such that the semiconductor structure is within a chamber that includes the oxygen/particles as gaseous oxygen/nitrogen-comprising molecules (e.g., molecular oxygen/nitrogen).Type: GrantFiled: November 14, 2000Date of Patent: May 4, 2004Assignee: International Business Machines CorporationInventors: Arne W. Ballantine, Daniel C. Edelstein, Anthony K. Stamper
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Patent number: 6727556Abstract: A semiconductor device has a semiconductor element formed on a semiconductor substrate and a first insulating film having contact holes. The semiconductor element has a gate electrode, a source region and a drain region. The semiconductor element also has metal wirings each for connecting a respective one of the contact holes to the gate electrode, the source region and the drain region of the semiconductor element. A second insulating film is formed on the first insulating film and the metal wirings. The second insulating film has a chemical-mechanical polished portion defining a flattened upper surface of the second insulating film. Resistors are formed on and are disposed directly in contact with the flattened upper surface of the second insulating film and are connected in series to form a bleeder resistor circuit or a ladder circuit.Type: GrantFiled: July 26, 2001Date of Patent: April 27, 2004Assignee: Seiko Instruments Inc.Inventors: Mika Shiiki, Minoru Sudou
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Patent number: 6720621Abstract: A SOI semiconductor device comprises a resistor body which is formed of a top semiconductor layer in a SOI substrate having an embedded dielectric film and the top semiconductor layer formed on the embedded dielectric film and which is dielectrically isolated by an insulating film, wherein a resistance value of the resistor body is set to be a predetermined value by the concentration of impurities contained in the top semiconductor layer and by the dimension of the resistor body.Type: GrantFiled: September 22, 2000Date of Patent: April 13, 2004Assignee: Sharp Kabushiki KaishaInventor: Alberto Oscar Adan
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Patent number: 6717233Abstract: A method for fabricating resistors within a semiconductor integrated circuit device is disclosed. A resistor is fabricated by first depositing a passivation layer on a semiconductor substrate having multiple transistors previously formed thereon. Next, a first contact window and a second contact window are formed through the first passivation layer at a first contact location and a second contact location, respectively. The first and second contact windows are then filled with metal, such as tungsten, and the metal at the first and second contact windows is planarized to form a first bottom contact and a second bottom contact, respectively. A resistive film, such as polysilicon, subsequently deposited over the first passivation layer. Next, a second passivation layer is formed over the resistive film. Finally, a first top contact and a second top contact are formed to respectively connect the first bottom contact and the second bottom contact to the resistive film.Type: GrantFiled: January 25, 2000Date of Patent: April 6, 2004Assignee: BAE Systems Information and Electronic Systems Integration, Inc.Inventors: Nadim Haddad, Charles N. Alcorn, Jonathan Maimon, Leonard R. Rockett, Scott Doyle
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Publication number: 20040056326Abstract: A method and structure for controlling the surface properties in the dielectric layers in a thin film component can be provided for improving the trimming process of thin film element. A metal fill is configured with a uniform fill pattern beneath an array of thin film resistors, and can comprise a plurality of smaller features or peaks providing a finer fill pattern that improves the control of the topology of the dielectric layers. The fill pattern can be configured in various manners, such as fill patterns parallel to the thin film resistor, fill patterns perpendicular to the thin film resistor, or fill patterns comprising a checkerboard-like configuration.Type: ApplicationFiled: September 20, 2002Publication date: March 25, 2004Applicant: Texas Instruments IncorporatedInventors: Eric W. Beach, Walter B. Meinel, Eric L. Hoyt
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Patent number: 6700474Abstract: A resistor structure is disclosed that is constructed out of two layers of polysilicon. The intrinsic device is made using the top layer which is either a dedicated deposition, or formed as part of an existing process step such as a base epi growth in a BiCMOS flow. This poly layer can be made with a relatively high (greater than 2000 ohms per square) sheet resistance by appropriate scaling of the implant dose or by insitu doping methods. The resistor ends are formed by the addition of a bottom poly layer in a self aligned manner with a deposition which may already be part of the process sequence. The end result is that the intrinsic resistor body is formed of a single poly layer, while the ends are created out of two layers. These ends are thick enough so that standard silicide and contact etch processing may be added to the structure without special care.Type: GrantFiled: August 22, 2002Date of Patent: March 2, 2004Assignee: Fairchild Semiconductor CorporationInventor: Steven M. Leibiger
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Publication number: 20040026762Abstract: It is an object to provide a semiconductor device in which a resistance value of a resistor formed by a silicon film is changed with difficulty. A resistor (31) is formed by an amorphous silicon film, and silicides (32a) and (32b) are formed in connecting portions of contact plugs (5a) and (5b) in a surface portion thereof. Since the resistor (31) is the amorphous silicon, a hydrogen atom is bonded with more difficulty as compared with the case in which polycrystalline silicon is used for a material of the resistor. Thus, it is possible to obtain a semiconductor device in which a resistance value of the resistor formed by the silicon film is changed with difficulty. Moreover, the suicides (32a) and (32b) are formed in the connecting portions of the contact plugs (5a) and (5b). Therefore, when contact holes for the contact plugs (5a) and (5b) are to be formed on a first interlayer insulating film (4a) by etching, the resistor (31) is etched with difficulty.Type: ApplicationFiled: June 12, 2003Publication date: February 12, 2004Applicant: Renesas Technology Corp.Inventors: Yuuichi Hirano, Takuji Matsumoto, Takashi Ipposhi
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Patent number: 6690083Abstract: The present invention is drawn to a method and a system for creating a sub-1V bandgap reference (BGR) circuit. In particular, a sub-1V BGR circuit is formed comprising a shallow trench isolation (STI) region and a poly silicon region above said STI region. The poly silicon region is formed having a first doped region longer than a second doped region. The poly silicon region as one single structure is adapted to function as a resistor and a diode coupled in series, said structure adapted to generate currents in a feedback loop to generate a BGR voltage. In forming the sub-1V BGR circuit, a silicide blocking mask (already available in the process flow for forming a standard semiconductor device) is used to prevent spacer oxide from forming above the center portion of the poly silicon region. In turn, silicide contacts can be formed away from the center portion of the poly silicon region.Type: GrantFiled: June 1, 2000Date of Patent: February 10, 2004Assignee: Koninklijke Philips Electronics N.V.Inventors: Todd Mitchell, Mark W. Haley
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Patent number: 6653713Abstract: A thin film resistor maintains its resistance value when stress is applied so that it may be used in a high precision bleeder resistor circuit to maintain an accurate voltage dividing ratio. The thin film resistor has a P-type thin film resistor formed of a P-type semiconductor thin film and an N-type thin film resistor formed of an N-type semiconductor thin film overlapping the P-type thin film resistor with an insulating layer interposed therebetween, so that a change in resistance value when stress is applied is prevented. In a bleeder resistor circuit, a resistance value of one unit is regulated by a resistance value formed by a combination of the P-type thin film resistor and the N-type thin film resistor so that an accurate voltage dividing ratio can be maintained when stress is applied.Type: GrantFiled: October 12, 2001Date of Patent: November 25, 2003Assignee: Seiko Instruments Inc.Inventor: Hiroaki Takasu
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Patent number: 6653688Abstract: A semiconductor device comprises a MOS transistor and a resistor. The resistor has a P-type resistor formed from a P-type semiconductor, an N-type resistor formed from an N-type semiconductor and disposed adjacent the P-type resistor, and an insulating film disposed between the P-type and N-type resistors. The P-type resistor is arranged at the low potential side of the semiconductor device and the N-type resistor is arranged at the high potential side thereof. A portion of the insulating film between the P-type and N-type resistors is made electrically conductive by irradiating the portion with a laser beam to destroy the insulating property thereof to thereby achieve conductivity between the P-type and N-type resistors. A gate electrode of the MOS transistor is formed of a P-type polysilicon thin film having the same high concentration impurity as that of the region where the P-type resistor is in contact with a metal wiring, thereby enhancing the current driving capacity of a driver MOS.Type: GrantFiled: April 3, 2002Date of Patent: November 25, 2003Assignee: Seiko Instruments Inc.Inventors: Hiroaki Takasu, Jun Osanai
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Patent number: 6627971Abstract: A device with a plurality of structures with different resistance values is formed on a substrate. A polysilicon layer is formed upon the substrate. A silicon oxide layer is formed over the substrate. A hard masking layer is formed over the silicon oxide layer. The hard masking layer includes a full thickness portion and a thinner portion. The polysilicon layer below the full thickness portion is lightly doped forming a high resistance region. Below the thinner portion the polysilicon layer is heavily doped forming a low resistance region. However, in spite of the differences in resistance, the high resistance region and the low resistance region have the same thickness.Type: GrantFiled: September 5, 2000Date of Patent: September 30, 2003Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chih-Heng Shen, Sen-Fu Chen, Huan-Wen Wang, Ying-Tzu Yen