Abstract: An insulating wall of a second conductivity type intended for separating elementary components formed in different wells of a semiconductive layer of a first conductivity type, a component located in one at least one of the wells being capable of operating with a high current density. The insulating wall includes at least two elementary insulating walls separated by a portion of the wafer material and, in operation, this portion is connected to a reference potential.

Abstract: A manufacturing method, and an integrated circuit resulting therefrom has a substrate with a semiconductor device thereon. A channel dielectric layer is deposited over the device and has an opening provided therein. A reducing process is performed in order to reduce the oxidation on the conductor and a conformal atomic liner is deposited in an atomic layer thickness to line the opening in the channel dielectric layer. A barrier layer is deposited over the conformal atomic liner and a seed layer is deposited over the barrier layer. A conductor core layer is deposited on the seed layer, filling the opening over the barrier layer and connecting to the semiconductor device.

Abstract: The semiconductor switching element blocks in both directions between a first and a second load terminal. The switching element has a field effect transistor and a bipolar transistor. The field effect transistor has a controlled gate, a source connected to the first load terminal, a drain connected to the second load terminal and a body connection. The bipolar transistor has a base, an emitter, and a collector. The emitter is connected to the body connection of the field effect transistor.

Abstract: An integrated circuit having a high voltage lateral MOS with reduced ON resistance. In one embodiment, the integrated circuit includes a high voltage lateral MOS with an island formed in a substrate, a source, a gate and a first and second drain extension. The island is doped with a low density first conductivity type. The source and drain contact are both doped with a high density second conductivity type. The first drain extension is of the second conductivity type and extends laterally from under the gate past the drain contact. The second drain extension is of the second conductivity type and extends laterally from under the gate toward the source. A portion of the second drain extension overlaps the first drain extension under the gate to form a region of increased doping of the second conductivity type.

Abstract: A compensating component and a method for the production thereof are described. Compensating regions are produced by implanting sulfur or selenium in a p-conductive semiconductor layer or, are provided as p-conductive regions, which are doped with indium, thallium and/or palladium, in a cluster-like manner inside an n-conductive region.

Abstract: A method and apparatus are provided for implementing enhanced silicon-on-insulator (SOI) passgate operations. The apparatus for implementing enhanced silicon-on-insulator (SOI) passgate operations includes a silicon-on-insulator (SOI) passgate field effect transistor. A select input is coupled to the silicon-on-insulator (SOI) passgate field effect transistor. A discharging field effect transistor of an opposite channel type is coupled to the silicon-on-insulator (SOI) passgate field effect transistor. The discharging field effect transistor is activated during an off cycle of the silicon-on-insulator (SOI) passgate field effect transistor. The discharging field effect transistor is coupled to the body of the SOI passgate field effect transistor. The discharging field effect transistor is deactivated during an on cycle of the SOI passgate field effect transistor, whereby the body of the SOI passgate field effect transistor floats during the on cycle.

Abstract: A device and a method are provided for isolating a circuit well from a substrate of the same conductivity type. In particular, an integrated circuit is provided which includes a circuit well arranged over a semiconductor substrate with no layer of opposite conductivity type arranged between the well and the substrate. The integrated circuit may further include a pair of isolation wells extending along opposite lateral boundaries of the circuit well. The isolation wells and circuit well may be adapted such that a single continuous depletion region underlying the circuit well may be formed upon application of an isolation voltage between the substrate and the pair of isolation wells. The formation of such a depletion region may beneficially isolate the circuit well from the underlying substrate.

Abstract: In a semiconductor device having a junction type diode using a bipolar transistor and a process for producing the same, a ratio of a diode electric current to a leakage electric current is improved, and latch up resistance is improved without increasing the process. A p type semiconductor substrate, a collector buried region and an n type epitaxial layer are formed, a p type first impurity region is formed in the n type epitaxial layer, an n type second impurity region is formed in the first impurity region, an N+ sinker is formed, and a collector electrode is formed, with a common electrode being formed on the first and second impurity regions.

Abstract: A methodology of creating integrated circuits with improved noise isolation is presented. The circuitry of an integrated circuits is separated into noise generating circuit blocks and noise sensitive circuit blocks. N-type and P-type diffusion guard rings are placed around each of the circuit blocks. Substantially overlying the N-type and P-type diffusion guard rings are power supply meshes which are intimately in contract with the guard rings below through spaced apart vias. The power supply meshes not only supply power for the circuit blocks, but also reverse-bias the diffusion guard rings for improved noise isolation.

Abstract: A high withstand voltage diode for protecting a high-voltage transistor has a first region 2 of a second conductivity type formed on the substrate of a first conductivity type, a high-concentration second region 5 of the second type formed on the first region 2, a third region 3 of the first conductivity type formed so as to, be adjacent to the first region 2, a high-concentration fourth region 4 of the first conductivity type formed on the surface of the third region 3, and a gate electrode 7 that straddles the first region 2 and the third region 3 with an intervening gate oxide film, and which is electrically connected to the fourth region.

Abstract: A circuit isolation technique that uses implanted ions in embedded portions of a wafer substrate to lower the resistance of the substrate under circuits formed on the wafer or portions of circuits formed on the wafer to prevent the flow of injected currents across the substrate. The embedded ions provide low resistance regions that allow injected currents from a circuit to flow directly to a ground potential in the same circuit rather than flowing across the substrate to other circuits. High energy implantation processes on the order of 1 MeV to 3 MeVs can be used to implant the ions in embedded regions. Multiple energy levels can be used to provide thick embedded layers either prior to or after application of an epitaxial layer. Various masking materials can be used to mask the isolation regions during the implantation process, including hard masking materials such as silicon dioxide or silicon nitride, poly-silicon or an amorphous silicon layer, and a photoresist layer.

Abstract: A CMOS structure having a silicon dioxide outer ring around the sense region. The CMOS sense structure has a substrate, a n− region, a n+ region, an isolation region, a field implant region and a silicon dioxide outer ring region. The n− region is formed in the substrate, and the n+ region is formed within the n− region. The isolation region is formed in the substrate next to the edge of the n− region. The field implant region is formed under the isolation region. The silicon dioxide outer ring region is formed over the n− region, a portion of the isolation region and a portion of the n+ region. The silicon dioxide outer ring can prevent surface leakage that is caused by etching and lengthening the distance from the n− region to the field implant region so that edge junction leakage is reduced.

Abstract: A transistor having an improved sidewall gate structure and method of construction is provided. The improved sidewall gate structure may include a semiconductor substrate (12) having a channel region (20). A gate insulation (36) may be adjacent the channel region (20) of the semiconductor substrate (12). A gate (38) may be formed adjacent the gate insulation (36). A sidewall insulation body (28) may be formed adjacent a portion of the gate (38). The sidewall insulation body (28) is comprised of a silicon oxynitride material. An epitaxial layer (30) may be formed adjacent a portion of the sidewall insulation body (28) and adjacent the semiconductor substrate (12) substantially outward of the channel region (20). A buffer layer (32) may be formed adjacent a portion of the sidewall insulation body (28) and adjacent the epitaxial layer (30).

Abstract: An electrode structure for semiconductor devices includes first electrode material positioned in overlying relationship to the surface of a substrate so as to define a first side wall perpendicular thereto. A nonconductive side wall spacer is formed on the first side wall and defines a second side wall parallel to and spaced from the first side wall. Second electrode material is formed in overlying relationship to the substrate and on the second side wall so as to define a third side wall parallel to and spaced from the second side wall. The first and second electrode materials are connected as first and second electrodes in a common semiconductor device. Additional electrodes can be formed by forming electrode material on additional side walls.

Abstract: Leakage current may be reduced in trench isolated semiconductor devices by providing a buffer between the trench isolation and an active area. For example, with a trench isolated photodiode, a buffer of opposite conductivity type may be provided between the trench and the diffusion that forms the p-n junction of the photodiode.

Abstract: The present invention is related to a MOS ESD protection circuit with embedded well diodes.

Abstract: The present invention relates to an isolating wall for separating elementary components formed in different wells, a component located in at least one of the wells being capable of operating with a high current density. The isolating wall exhibits in its median portion a concentration of carriers higher than 1016 atoms/cm3. Preferably, the width of the openings from which the dopant diffusions are formed in the upper and lower surfaces of the substrate is higher than 1.3 times the half-thickness of the substrate.

Abstract: The provision of an isolation gate connecting unassociated active areas of adjacent transistors formed in a semiconductor substrate provides effective isolation of the adjacent transistors with no additional process steps required. The isolation gate is tied to a reference to ensure that a channel between the unassociated active areas is not formed, and effective isolation is provided. The adjacent transistors are cross coupled to form sense amplifiers for dynamic random access memory devices.

Abstract: Provided is a semiconductor structure that comprises a substrate; a conductor; and insulating layer separating the conductor from the substrate; and a removable conductive strap coupled to the conductor and the substrate for maintaining a common voltage between the conductor and substrate during ion beam and/or plasma processing; and a method for fabricating.

Abstract: A field effect transistor (FET) structure, and method for making the same, which further suppresses short-channel effects based on variations within the gate dielectric itself. The FET structure utilizes non-uniform gate dielectrics to alter the vertical electric field presented along the channel. The thickness and/or dielectric constant of the gate dielectric is varied along the length of the channel to present a vertical electric field which varies in a manner that tends to reduce the short-channel effects and gate capacitances.

Abstract: A semiconductor circuit device having a triple-well structure wherein a predetermined potential level is supplied to a top well without a contact region formed in the top well is disclosed. In an N-type ion implantation step for forming an N-type well region (1) in a P-type semiconductor substrate (5), a mask of a predetermined configuration is used so that ions are not implanted into a region of a portion which is to serve as a bottom portion (1B) of the well region (1). Then, the N-type well region (1) is formed which is shaped such that a portion (6) having P-type properties remains partially in the bottom portion (1B). The P-type portion (6) establishes electrical connection between a P-type well region (2) and the semiconductor substrate (5) to permit the potential applied to a contact region (4) to be supplied to the well region (2) therethrough. The portion (6) may include a plurality of portions (6) which allow uniform potential supply.

Abstract: A structure of a polysilicon via that includes a semiconductor substrate, a conducting layer on the substrate, a dielectric layer on the conducting layer, a polysilicon plug formed in the dielectric layer, a polysilicon layer on the polysilicon plug, and a silicide layer formed on the polysilicon layer. The polysilicon layer is electrically connected to the conducting layer through the polysilicon plug. The structure of a polysilicon via according to the invention prevents the occurrence of leakage currents in the presence of misalignment in the follow-up photolithography process.

Abstract: A dummy pattern that is inserted to stabilize the form of a transistor active region is implanted with an impurity of the same conductivity type as a well, and the impurity-doped region of the dummy pattern is supplied with a potential through a metal interconnection. Hence, fluctuation of a well potential due to noise hardly occurs, and a semiconductor device enduring latch up, for example, to a greater extent can be provided.

Abstract: The present invention relates to a composite integrated circuit including at least one well that separates analog and digital blocks of the circuit, this well being connected to a first terminal of a power supply of biasing of one of the two blocks, and being of type opposite to that of the circuit substrate, and a resistor being interposed on the well biasing link.

Abstract: A suppression method is applied to an integrated circuit formed on a substrate of p-type material having at least one region of n-type material with junction isolation, a first electrical contact on the frontal surface of the substrate, a second electrical contact on the n-type region and a third electrical contact on the back of the substrate connected to a reference (ground) terminal of the integrated circuit. To avoid current in the substrate due to the conduction of parasitic bipolar transistors in certain operating conditions of the integrated circuit, the method provides for monitoring the potential of the second contact to detect if this potential departs from the (ground) potential of the reference terminal by an amount greater than a predetermined threshold value. If this occurs the first contact is taken to the potential of the second contact, otherwise they are held at the (ground) potential of the reference terminal. A device and an integrated circuit which utilize the method are also described.

Abstract: An integrated semiconductor structure comprises two homologous P-type regions formed within an N-type epitaxial layer. A P-type region formed in the portion of the epitaxial layer disposed between the two P-type regions includes within it an N-type region. This N region is electrically connected to the P region by means of a surface metal contact. The structure reduces the injection of current between the first and second P regions, at the same time preventing any vertical parasitic transistors from being switched on.

Abstract: A resistor on a semiconductor wafer comprising a silicon substrate, a first doped layer in a predetermined area on the silicon substrate, a second doped layer within a predetermined area of the first doped layer, a dielectric layer above the first and second doped layers on the silicon substrate, a passivation layer on the dielectric layer, and a conducting layer between the dielectric layer and the passivation layer. The silicon substrate contains dopants that characterize it as an n-type (or p-type) semiconductor. The first doped layer functioning as a resistor layer is a p-type (or n-type) semiconductor and forms a first pn-junction at its interface with the silicon substrate to prevent electrical leakage. The second doped layer is a n-type (p-type) semiconductor and forms a second pn-junction at its interface with the first doped layer that prevents electrical leakage. The passivation layer has a plurality of charges at fixed positions.

Abstract: A semiconductor device includes a semiconductor substrate in which a trench for element isolation is formed, and an element isolation oxide film buried into the trench in such a manner that the element isolation oxide film is projected from the surface of the semiconductor substrate. The element isolation oxide film which is an element isolation insulating film for defining an element forming region on the semiconductor substrate has a projection portion above the surface of the semiconductor substrate. The projection portion has the width wider than that of the trench. The projection portion and a contact portion made in contact with the semiconductor substrate within the trench are made of thermal oxide films, and a portion other than the projection portion and the contact portion is made of a CVD dioxide film.

Abstract: A dielectric isolated high voltage semiconductor device having an arrangement for extending a depletion layer of a main junction beyond an insulating layer containing an island to a semiconductor supporter by applying the same reverse biasing voltage to the supporter and the islands. That is, in the structure, an electrode is provided at the back surface of the supporter and connected to a main electrode of the selected island. The above-mentioned main junction is the pn junction to which the reverse biasing voltage for securing the withstand voltage of the semiconductor device is applied. The device is structured, also, with high impurity concentration regions for preventing a depletion layer, formed during a reverse biasing of the main junction of a circuit element of an island, from extending into adjacently disposed islands.

Abstract: A high voltage integrated circuit is provided which includes a first conductivity type semiconductor substrate, a first conductivity type isolation region that extends continuously from the first conductivity type semiconductor substrate, a substrate electrode formed on a surface of the first conductivity type isolation region, a second conductivity type island-like region that is formed on the first conductivity type semiconductor substrate, such that the entire periphery of the island-like region is surrounded by the first conductity type isolation region, and a plurality of high voltage MOSFETs that are connected to a common power source and operate independently of each other.

Abstract: The invention relates to a structure for and the method of manufacturing a driver circuit for an inductive load monolithically integrated on a semiconductor substrate doped with a first type of doping agent and on which is grown an epitaxial well having a second type of doping agent. An insulated well doped with the same type of doping agent as the substrate, which houses at least one power transistor of the driver circuit, is provided within the epitaxial well. The epitaxial well also houses a first and a second active area which house the cathode terminal and anode terminal of a protection diode, respectively.

Abstract: A substrate (10) of a semiconductor device includes a power section (12) and a control section (14). The power section includes doped regions (16, 18, 20) and terminals (22, 24, 26) which define power devices such as transistors or SCRs. The control region also includes doped areas including a parasitic collector (32). A minority carrier current (62) flows from the doped regions of the power section to the collector of the control section when the power device to substrate junction is forward-biased. A self-biased moat assembly (40) includes a first doped region (42) between the doped regions of the power and control sections under which the parasitic minority carrier current flows. An electrical connection (46) connects the moat first doped region (42) with a moat second doped region (44). The self-biased moat assembly is isolated from ground such that it is self-biased negative in accordance with internal operating conditions of the semiconductor device.

Abstract: A method and apparatus for the localized reduction of the lifetime of charge carriers in integrated electronic devices. The method comprises the step of implanting ions, at a high dosage and at a high energy level, of a noble gas, preferably helium, in the active regions of the integrated device so that the ions form bubbles in the active regions. A further thermal treatment is performed after the formation of bubbles of the noble gas in order to improve the structure of the bubbles and to make the noble gas evaporate, leaving cavities in the active regions.

Abstract: A semiconductor device includes a power transistor group and a signal circuit on the same substrate. The substrate is grounded at an isolation region at an end of the substrate adjacent to the power transistor group so that the grounded portion of the substrate is distant from the signal circuit.

Abstract: An integrated circuit includes a substrate and at least two circuits, such as a digital circuit and an analog circuit. The substrate is preferably derived from a bulk substrate wafer. The integrated circuit preferably comprises at least two islands in the substrate for noise isolation between the circuits. The two islands are buried-layers that are implanted, by preference, using conventional MeV techniques. A method of manufacturing an integrated circuit includes a substrate and at least two circuits. The method comprises the step of implanting at least two islands in the substrate for noise isolation between the circuits. The implanting is accomplished by conventional masking and high-energy implantation, such as MeV.

Abstract: The invention relates to a high voltage integrated circuit with connecting metal conductors (30, 32) connected to ground or potential near ground and covered by a passivating layer (18). The invention is characterized by said passivating layer (18) being partially broken up above said metal conductors to prevent activation of parasitic MOS-transistor.

Abstract: Isolation between the heavily-doped active regions of an active pixel sensor cell is provided by utilizing a series of isolation regions which have a doping concentration that is approximately equal to the doping concentration of a low-density drain (LDD) region. A first isolation region of the series, which has the same conductivity type as the active regions, is formed to adjoin a first active region. A second isolation region of the series, which has the opposite conductivity type as the active regions, is formed to adjoin the first isolation region. A third isolation region, which has the same conductivity type as the active regions, is formed to adjoin the second isolation region and a second active region.

Abstract: A semiconductor integrated circuit has a semiconductor substrate on which macrocells are formed. At least one of the macrocells is surrounded by a first diffused region, which may be surrounded by a second diffused region. The first and second diffused regions are connected to power source terminals, respectively. Semiconductor elements included in each macrocell are connected to power source terminals that are independent of the terminals connected to the diffused regions. Alternatively, a voltage is supplied to the diffused regions through power lines that are different from power lines for the semiconductor elements. This arrangement absorbs short-circuit current in CMOS circuitry and/or substrate current produced by the semiconductor elements.

Abstract: An arrangement that prevents triggering of latchup in internal circuits by input/output buffers on an integrated circuit chip provides a space surrounding each active device connected to a bond pad. A ring well surrounds the space and separates the active device from the internal circuits of the chip. The ring well serves as a collector to prevent triggering latchup by the active device of the internal circuits located outside the ring well.

Abstract: A closed loop control system for controlling the temperature of a heated substrate is presented. In the preferred embodiment, the closed loop control system is implemented substantially or completely on a single substrate. The closed loop control system comprises means to reduce or eliminate parasitic feedback in the control system. In one aspect of the present invention, the mechanism for reducing the effects of parasitic feedback comprises a mechanism to prevent minority carriers from collecting around the base of the temperature sensing device. The mechanism for preventing minority carriers from collecting around the base of the temperature sensing device can be one or more guard rings which attract the minority carriers and prevent them from collecting around the base of the temperature sensor.

Abstract: A CMOS layout enables the matching of an intentionally created parasitic capacitance to an existing parasitic capacitance, for example, a gate-to-drain capacitance of a MOSFET, with a high degree of precision. This precise matching allows a differential pair of MOSFETs acting as the input of an amplfier to have intentionally created capacitances (that match the parasitic gate-to-drain capacitances) cross-coupled between the inputs and the outputs of the differential pair. This cross-coupling of matching capacitances effectively cancels the bandwidth reducing effect of the gate-to-drain capacitances of the differential pair. The layout provides for the interdigitation of the gates of the differential pair, with each input transistor comprising at least two transistors connected together to form a single input transistor.

Abstract: The present invention relates to an electronic device integrated monolithlly on a semiconductor material comprising a substrate having a first conductivity type in which are formed first and second diffusion regions of a second conductivity type. The substrate and the first and second diffusion regions defining a base region, a collector region and an emitter region of a parasitic transistor. The second diffusion region includes a third diffusion region having conductivity of the first type to provide in the second diffusion region a resistive path placed in series with the emitter region of the parasitic transistor while backfeeding it negatively and taking it to saturation with a resulting reduction of its current gain and limitation of the maximum current due thereto.

Abstract: A semiconductor integrated circuit device for driving a motor and including a p-type semiconductor substrate having spaced apart first and second areas; power transistors in the semiconductor substrate within the first area; a small signal system circuit in the semiconductor substrate within the second area; and an n-type isolating region in the semiconductor substrate separated from the first and second areas and disposed at least partially between the first and second areas, the n-type isolating region being connected to ground.

Abstract: The earth wire is a conductive lead located at the nearest position to a flat surface of the semiconductor substrate, and the earth wire and the word lines are arranged so that these are not formed on the other wires in the memory cell, the wiring resistance is reduced by shortening the wiring length, and there is little unevenness in the underlayer of the earth wire, whereby the read-out operation is stabilized. Furthermore, the earth wire is formed of a wiring layer which is near to the semiconductor substrate, so that the distance between the earth wire and a load element is set to be larger than that in the prior art. Therefore, it can be prevented that the earth wire acts as the gate electrode of a parasitic transistor and thus malfunction occurs. In addition, the shape of the field pattern can be simplified.

Abstract: A guard ring with the same conductivity as a device pocket surrounds the pocket and a pocket isolation ring to establish a parasitic transistor that conducts current between the guard ring and the pocket when the pocket voltage is driven sufficiently below the substrate voltage. The guard ring is connected to a voltage supply for the circuit which, together with its shorter current path, allows the parasitic transistor to harmlessly divert current away from unwanted inter-pocket parasitic transistors.

Abstract: An integrated circuit including a power stage, a low-voltage component separated from the power stage by an isolating region and a reference potential region at a reference potential. The power stage includes an N-type substrate region which may be biased to a terminal voltage with respect to the reference potential and the isolating region has P-type conductivity. The low-voltage component includes an N-type input region receiving an input voltage. The input voltage and the terminal voltage may oscillate a few tens of volts above or below the reference potential and turn on parasitic transistors. To prevent turning on of the parasitic transistors, switchable conductive paths are interposed between the isolating region on the one hand, and the substrate region, the input region and the reference potential region on the other, for electrically connecting the isolating region to one of the substrate region, input region and reference potential region which presents instant by instant the lowest potential.

Abstract: An input cell circuit for an integrated circuit for use in a mixed signal mode where an input pin may receive either digital or analog signals. The circuit solves the problem where several such pins are used in a mixed signal mode and share a common internal bus. Such input signals will cause erratic values on the common analog bus, if any given input pin is used as a digital input signal and the voltage on that input pin exceeds the supply voltage by the base-emitter voltage of the parasitic transistor in the P-channel transistor in a pass gate in the associated input cell. This problem is solved by adding a second P-channel transistor to the pass gate and also adding an N-channel transistor connected to a node between the two P-channel transistors, as well as adding an input resistor.

Abstract: A circuit construction for biasing near a pocket containing a power supply potential circuit element in a junction-isolated circuit. In normal operation if the polarity of the supply voltage is reversed from that intended the pocket is disconnected. To achieve this, in one embodiment the emitter of a transistor is connected to the positve supply voltage. The collector of that transistor is used to bias the pocket, containing a circuit element, which in normal operation should receive the supply voltage. When the supply voltage is reversed, the emitter-base junction is reverse biased and the collector-base junction is turned off. The pocket is thus disconnected from the supply during supply reversal. The transistor may also have a second collector to handle reinjection of carriers when it is saturated. This second collector can be connected to the base or used by other circuits to detect when saturation occurs.

Abstract: An improved isolation structure for a semiconductor device includes a p-type semiconductor substrate (12) with a p-type well (28) disposed in the substrate (12). A continuous plurality of n-type regions (14, 16, 26) is disposed around the p-type well (28), and the continuous plurality of n-type regions (14, 16, 26) fully isolates the p-type well (28) from the substrate (12) except that the continuous plurality of regions (14, 16, 26) comprises one or more p-type gaps (18) that electrically connect the p-type well (28) to the p-type substrate (12). The use of the gap (18) improves cross-talk suppression in mixed-mode integrated circuits at higher frequencies, for example greater than 50 MHz.

Abstract: An active pixel image sensor in accordance with the present invention utilizes guard rings, protective diffusions, and/or a combination of these two techniques to prevent electrons generated at the periphery of the active area from impacting upon the image sensor array. For example, an n+ guard ring connected to V.sub.cc can be imposed in the p-epi layer between the active area edge and the array, making it difficult for edge-generated electrons to penetrate the p+ epi in the array; this approach requires the use of annular MOS devices in the array. Alternatively, the gates of the n-channel devices in the array can be built to overlap heavily doped p+ bands, forcing current flow between the source/drain regions. As stated above, combinations of these two techniques are also contemplated. Elimination of the active area edge leakage component from the array can increase the dynamic range of the image sensor by 6 bits.