Abstract: An IC is constructed with deep layers preventing current flow due to parasitic transistors formed within the IC. Reverse current in case of voltage source polarity reversal is prevented by means of the reverse bias diodes formed by the addition of a P+ ring, and N+ well, for the embodiment disclosed.

Abstract: A high-voltage bipolar transistor and fabrication method that comprises a shield electrode (or field-termination electrode) located between bond pads and underlying semiconductor material. The shield electrode is sandwiched between two isolating dielectric layers. High-voltage applied to the bond pad establishes an electric field between the bond pad and the shield electrode), preventing field penetration into and inversion of the underlying semiconductor material. Using this overlapping field-termination structure, low leakage current and high breakdown voltage is maintained in the transistor. The present overlapping field-termination structure provides an effective field termination underneath the bond pads, and because of its overlapping design, provides for a more compact transistor.

Abstract: By reverse biasing the PN junction formed around a semiconductor element, the semiconductor element is isolated from other elements. The PN junction around the semiconductor element is a junction between a layer surrounding the semiconductor element and a layer disposed outside the layer. Jointly with the layer constituting the semiconductor, the layer surrounding the semiconductor element forms a parasitic diode. The potential of the layer on the semiconductor element to be connected to the layer surrounding the semiconductor element is detected, and based on this potential, the voltage to be applied to the parasitic diode is controlled so as to be constant. When the voltage to be applied to the parasitic diode is lower than a threshold, the parasitic diode will be in a cutoff state.

Abstract: A two masking level process for a dual buried region epitaxial architecture forms a first masking layer on a surface of a P type substrate. The first masking layer exposes first and second surface portions of the substrate for N+ and P+ buried regions. N type impurities are introduced into the substrate through the first masking layer, so as to form N+ doped regions. A second masking layer is then selectively formed on the first masking layer, such that the second masking layer masks the first aperture, but exposes a second portion of the first masking layer that both includes and surrounds the second aperture. Boron impurities are then introduced through the exposed second aperture of the first masking layer, to a P+ doping concentration.

Abstract: An integrated circuit containing both power and small-signal NPN bipolar devices. The small-signal devices use lateral current flow, and are completely surrounded (laterally and vertically) by an N-type well region. The N-type well region itself is completely surrounded (laterally and vertically) by a P-type isolation region. This double isolation provides improved protection against turn-on of parasitic devices, which can cause leakage problems in the conventional device structures. Optionally a self-aligned process step is used to provide a graded base doping profile in the small-signal devices.

Abstract: A large sense voltage is produced by the semiconductor device of the present invention. The semiconductor device, utilizing current mirror techniques, is comprised of a power MOSFET having a plurality of power cells and a plurality of sense cells formed in a semiconductor epitaxial layer. The large sense voltage is provided by isolating and separating the plurality of power cells from the plurality of sense cells by at least the thickness of the semiconductor epitaxial layer. Isolation can be provided by forming a plurality of inactive cells or an elongated cell between the plurality of power cells and the plurality of sense cells. In addition, high voltage capabilities can be maintained by including a partially active region adjacent the power cells to provide for good termination.

Abstract: A semiconductor integrated circuit has a P-type substrate and a plurality of PN-junction isolated islands of N-type, a first one of the islands may contain a power device which during certain periods of operation causes the first island to become forward biassed and to inject electrons into the substrate. Collection of these injected charges by a second island at one side of the injecting island is reduced by a separate protective bipolar transistor formed in a third N-type island. The third island is preferably interposed between the injecting island and the islands to be protected, but may be located anywhere with respect to the injecting transistor. The emitter of the protective transistor is electrically connected to an N-type portion of the first island. The collector of the protective transistor is connected to the P-type isolation-wall portion of the substrate located between the injecting transistor and the small islands to be protected.

Abstract: A substrate insulation device includes power supply terminals which are connected to a terminal of an active integrated element which has, with respect to a substrate on which it is defined, at least one reverse-biased junction.

Abstract: By forming an isolated semiconductor layer or electrode layer on a semiconductor surface between neighboring field effect transistors and element separating trenches which are deep enough to reach at least the semi-insulating substrate or the hetero junction interface on the buffer layer, low frequency oscillation of a compound semiconductor integrated circuit can be reduced. By controlling the thickness of the buffer layer having a hetero junction to at most 150 nm, the low frequency oscillation can be reduced. By forming materials separating adjacent elements with a width of at most 2 .mu.m which reach from the element region surface to the buffer layer having hetero junction so as to enclose the element regions and etched regions in the neighborhood of the elements or so as to enclose the element regions in the etched regions and by controlling the angle of the sides of the etched regions against the semiconductor layer surface to 10.degree. to 60.degree., wires can be prevented from short-circuiting.

Abstract: In an integrated circuit in which a first PN-junction-isolated island may momentarily become forward biased with respect to the surrounding substrate and inject unwanted charge that is collected by second islands adjacent one side of a first island, the injected charge is drawn away from the second islands and to a gatherer-collector island located at another side of the first island. The first island, gatherer-collector island and intervening substrate therebetween serve respectively as the emitter, collector, and base of a protective transistor. This transistor becomes a highly efficient collector of injected charge when the protective-transistor collector is hard wired to ground and the protective-transistor base is hard-wire connected to the substrate portion between the injecting first island and adjacent second island.

Abstract: An isolation structure is provided to give improved protection from below ground current injection. A first epitaxial region is provided between a power field effect device and nearby control circuitry. The first epitaxial region is tied to the substrate, and the ties are located between the first epitaxial region and the power field effect device. On the opposite side of the power device, preferably adjacent an edge of the integrated circuit chip, a second epitaxial region is formed. This epitaxial region is connected to the first epitaxial region, preferably by a metal interconnect line. A second set of substrate contacts is located between the power device and the second epitaxial region, and is tied to ground. The second epitaxial region encourages injection of current at a location spaced away from the control circuitry.

Abstract: A circuit die 100 with improved substrate noise isolation may be achieved by providing a first circuit element 102 and a second circuit element 103 on a substrate 101. The first circuit element 102 generally injects noise into the substrate 101 while the second circuit element 103 is adversely affected by noise being carried in the substrate 101. To reduce the noise interference, a noise isolation ring 104-017 may be placed around the first circuit element 102 and/or the second circuit element 103 wherein the noise isolation ring is of a conducted material. A first lead 202 is electrically connected to a first circuit element 102, a second lead 205 is electrically connected to the second circuit element 103, and a third lead 201 is electrically connected to the noise isolation ring 105, wherein the third lead 201 is electrically isolated from both the first and second leads 202 and 205.

Abstract: An overvoltage protected switch (1) includes a power semiconductor device (10) formed by a plurality of second regions (11) within a first region (3) of a semiconductor body (2), and an insulated gate 12 overlying a conduction channel region (13) between each second region (11) and the first region (3) with the first and second regions (3 and 11) providing a conductive path to first and second main electrodes (4 and 5), respectively, of the switch (1). An auxiliary semiconductor device (100) is formed by a number of further second regions (11), less than the plurality of second regions (11), and a further insulated gate (120) overlying a further conduction channel region (13) between each further second region (11) and the first region (3).

Abstract: In a semiconductor device, a FET and an isolation are provided on a semiconductor substrate and a channel stop region is provided under the isolation. At least a region to which a high voltage is applied of a source region and a drain region of the FET is separated from the channel stop region, and a first buffer region doped with an impurity for adjusting the threshold level is provided therebetween. A region under a gate electrode and adjacent to the isolation serves as a second buffer region to which an impurity for adjusting the threshold level is doped. With the first buffer region, a depletion region at a boundary of the drain region and the channel stop region is ensured, obtaining a superior durability to high voltage of the source/drain region. With the second buffer region, leakage current between the source region and the drain region is prevented.

Abstract: An input protective circuit provided between a semiconductor integrated circuit and an input bonding pad formed on a semiconductor substrate includes an N or P type electric field intensity relaxing region for setting a clamp level of the input protective circuit. The electric field intensity relaxing region is formed between an N.sup.+ -type semiconductor region connected to an input wiring layer and a P.sup.+ -type semiconductor region connected to a reference potential wiring layer.

Abstract: A MOS transistor is formed in a first low-doped P-type retion coating a second more highly doped P-type region. The transistor comprises an N-type drain region, an N-type source region, and a region contacting the for region. The drain, cource and contacting regions are formed at the surface of the first region. The source and contacting regions are interconnected. An N-type highly doped region extends from the drain region through the first low-doped P-type region to the second more highly doped P-type region.

Abstract: A semi-insulating compound semiconductor device includes an input terminal portion having a protection diode connected thereto and an element formation region and which is provided with a conduction region having the highest potential in the semiconductor device disposed between the input terminal portion and the element formation region. With such an arrangement, low-frequency oscillation of the drain current I.sub.D or drain conductance g.sub.m due to a leak age current from the protection diode connected to the input terminal portion can be prevented from occurring and thus the semi-insulating compound semiconductor device can operate satisfactorily with stabilized characteristics.

Abstract: A field effect transistor signal switching device includes a semiconductor substrate including an active region; an input electrode disposed on the substrate and including a source electrode disposed on the active region and a source pad; first and second output electrodes respectively including first and second drain electrodes disposed on the active region; and first and second control electrodes disposed on the substrate for controlling the selective transmission of an input signal applied to the input electrode to the first and second output electrodes, the first and second control electrodes respectively including first and second gate electrodes disposed on the active region between the source electrode and the first and second drain electrodes, respectively, first and second gate pads, and first and second connecting portions disposed on the substrate respectively electrically connecting the first and second gate electrodes to the first and second gate pads.

Abstract: Herein disclosed is a semiconductor integrated circuit device, in which a buffer circuit having a MISFET of a second conduction type and arranged in a first region of the principal plane of a semiconductor substrate of a first conduction type is supplied with a first supply voltage and in which an internal circuit having a complementary MISFET and arranged in a second region of the principal plane of the semiconductor substrate different from the first region is supplied with a second supply voltage independent of the first supply voltage at least over the semiconductor substrate and having a potential equal to that of the first supply voltage. The MISFET of the buffer circuit is formed in the principal plane of a well region of a first conduction type formed in the principal plane of the semiconductor substrate. Between the well region of the first conduction type and the semiconductor substrate, there is formed a separating region for separating the two electrically.

Abstract: A bias structure for an integrated circuit including first and second transistors having emitter terminals coupled respectively to the supply and to a terminal of a resistor whose potential, under certain operating conditions of the circuit, exceeds the supply voltage; base terminals connected to each other and to a current source; and collector terminals connected electrically (12) to an epitaxial tub housing the resistor. A resistor is preferably provided between the two collectors, so that, when the potential of the terminal of the resistor exceeds the supply voltage, the second transistor saturates and maintains the epitaxial tub of the resistor at a potential close to that of the resistor terminal, thus preventing the parasitic diode formed between the resistor and the epitaxial tub from being switched on.

Abstract: A power transistor having an epitaxial layer within an isolation region is formed in a semiconductor substrate. A buried diffusion within the substrate with vertical diffusions contacting it form the isolation region. A drain, source, gate, and drift region are formed within the epitaxial layer such that a RESURF LDMOS transistor is formed having its source isolated from the substrate. Multiple power transistors may share the buried isolation region. A P type semiconductor substrate allows the power transistor and high performance CMOS circuitry to be formed on the same semiconductor die.

Abstract: A semiconductor device includes an impurity doped polycrystalline silicon layer formed on a first conductivity type semiconductor substrate with an oxide film provided therebetween, an interlayer insulation layer formed on the polycrystalline silicon layer and provided with a contact hole using the surface of the silicon layer as a bottom surface, and a conductive wiring layer formed on the surface of the interlayer insulation layer and on the inner wall surface of said contact hole. A second conductivity type impurity diffusion layer is formed at a region of the surface of the semiconductor substrate located below the contact hole. A pn junction formed between the impurity diffusion layer and the semiconductor substrate ensures insulation against its reverse bias voltage to prevent leakage current to the semiconductor substrate.

Abstract: A power integrated circuit includes a substrate with an overlying epitaxial surface layer of opposite conductivity type. A semiconductor power device, such as a high-power diode or lateral MOS transistor, is located in the epitaxial layer and forms a p-n junction diode with the substrate. The power integrated circuit also includes a separate semiconductor well region in the epitaxial layer, in which one or more low-power semiconductor circuit elements are formed. In order to minimize the problem of latch up in the low-power circuit elements due to the injection of minority carriers from the substrate, the power integrated circuit is provided with a collector region and an isolation region between the power device and the well region having the low-power circuit elements.

Abstract: A radiation hardened NMOS transistor structure suited for application to radiation hardened CMOS devices, and the method for manufacturing it is disclosed. The new transistor structure is characterized by "P" doped guard bands running along and immediately underlying the two bird's beak regions perpendicular to the gate. The transistor and the CMOS structure incorporating it exhibit speed and size comparable to those of conventional non-rad-hard CMOS structure, relatively simple manufacturing, and excellent total-dose radiation hardness.

Abstract: Buried layers of a second conductivity type are formed in a plurality of portions of a surface region of a semiconductor substrate of a first conductivity type, and an epitaxial layer of the first conductivity type is formed on the buried layers and the semiconductor substrate. A plurality of well regions of the second conductivity type are formed in the epitaxial layer in contact with the buried layers, and a region of the second conductivity type with a high impurity concentration is formed in one of the well regions in contact with the buried layers. A field insulating layer is formed on a surface region of the semiconductor substrate between the well regions. An impurity is ion-implanted in a portion substantially immediately below the field insulating film a plurality of times to form inversion preventing layers of the first conductivity type having a plurality of impurity concentration peaks. Active elements are formed in the epitaxial layer of the first conductivity type and the well regions.

Abstract: A semiconductor device composed of a substrate provided with a groove filled with insulating material to define an element isolating region. The groove corners are rounded and the substrate contains impurity material below the groove and in a region adjacent the groove. The impurity material is introduced to have essentially the same impurity density profile below the bottom of the groove and below the substrate surface in the region adjacent the groove.The device may additionally be provided, if the region below and adjacent the groove is of P-type conductivity, with a buried P-type layer which opposes penetration of .alpha. particle radiation into the substrate.

Abstract: This invention relates to a semiconductor integrated circuit device wherein guardring regions are formed between a first element region and a second element region so as to surround the first element region, wherein gate electrodes are provided to cross the guardring regions, wherein the guardring regions are continuously formed even directly below the gate electrodes, and wherein an insulator film directly below the gate electrodes is relatively thick.