At Least One Layer Of Organic Material Patents (Class 257/642)
  • Patent number: 7041586
    Abstract: A semiconductor device includes a multilayer interconnection structure including an organic interlayer insulation film in which a conductor pattern is formed by a damascene process, wherein the organic interlayer insulation film carries thereon an organic spin-on-glass film.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: May 9, 2006
    Assignee: Fujitsu Limited
    Inventors: Hiroshi Kudo, Masanobu Ikeda, Kenichi Watanabe, Yoshiyuki Ohkura
  • Patent number: 7042163
    Abstract: An organic electroluminescence display includes a substrate and a plurality of light emitting parts formed on the substrate, each of the light emitting parts including an organic electroluminescence device and an organic thin film transistor connected to the organic electroluminescence device. The organic electroluminescence device has a pair of opposed electrodes and an organic material layer including an organic light-emitting layer laminated between the pair of electrodes. The organic thin film transistor has a source electrode and a drain electrode opposed to each other, an organic semiconductor film laminated so as to form a channel between the source electrode and the drain electrode, and a gate electrode for applying a field to the organic semiconductor film between the source electrode and the drain electrode.
    Type: Grant
    Filed: September 5, 2003
    Date of Patent: May 9, 2006
    Assignee: Pioneer Corporation
    Inventor: Kenichi Nagayama
  • Patent number: 7038303
    Abstract: An object of the present invention is to increase adhesiveness between thin films, particularly a high molecular film formed on an insulating surface, and the present invention provides a semiconductor device with high reliability and a method for manufacturing the semiconductor device with high yield. A semiconductor device of the present invention comprises a laminate structure formed in close contact with an organic insulating film on a hydrophobic surface of an inorganic insulating film including silicon and nitrogen. A film having the hydrophobic surface is an insulating film having a contact angle of water of equal to or more than 30°, preferably of equal to or more than 40°.
    Type: Grant
    Filed: March 25, 2004
    Date of Patent: May 2, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Koji Muranaka
  • Patent number: 7034381
    Abstract: A resin material having low dielectric constant is used as an inter-layer insulating film and its bottom surface is contacted with a silicon oxide film across the whole surface thereof. Thereby, the surface may be flattened and capacity produced between a thin film transistor and an pixel electrode may be reduced. Further, it allows to avoid a problem that impurity ions and moisture infiltrate into the lower surface of the resin material, thus degrading the reliability of whole semiconductor device.
    Type: Grant
    Filed: August 27, 2004
    Date of Patent: April 25, 2006
    Assignee: Semiconductor Energey Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 7034380
    Abstract: The present invention describes a structure having a multilayer stack of thin films, the thin films being a low-dielectric constant material, the thin films having pores, and a method of forming such a structure.
    Type: Grant
    Filed: September 12, 2003
    Date of Patent: April 25, 2006
    Assignee: Intel Corporation
    Inventor: Ebrahim Andideh
  • Patent number: 7035140
    Abstract: Embodiments of organic-polymer-based memory elements that are stable to repeated READ access operations are disclosed. Organic-polymer-based memory elements can suffer cumulative degradation that occurs over repeated READ access operations due to the introduction of electrons into the organic-polymer layer. In general, entry of electrons into the organic-polymer layer generally lags initiation of a hole current within the organic-polymer layer following application of a voltage potential across the memory elements. Therefore, stable memory elements can be fabricated by introducing electron-blocking layers and/or limiting the duration of applied voltages during READ access operations.
    Type: Grant
    Filed: January 16, 2004
    Date of Patent: April 25, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Warren B. Jackson, Sven Moller
  • Patent number: 7019386
    Abstract: Semiconductor devices employing siloxane epoxy polymers as low-? dielectric films are disclosed. The devices include a semiconductor substrate, one or more metal layers or structures and one or more dielectric films, wherein at least one dielectric film in the devices is a siloxane epoxy polymer. Use of siloxane epoxy polymers is advantageous, in part, because the polymers adhere well to metals and have dielectric constants as low as 1.8. Thus, the disclosed semiconductor devices offer much better performance than devices fabricated using conventional dielectric materials. Furthermore, the siloxane epoxy polymer dielectrics are fully curable at low temperatures, exhibit low leakage currents, and remain stable at temperatures greater than 400° C.
    Type: Grant
    Filed: April 27, 2004
    Date of Patent: March 28, 2006
    Assignees: Polyset Company, Inc., Rensselaer Polytechnic Institute
    Inventors: Ramkrishna Ghoshal, Pei-I Wang, Toh-Ming Lu, Shyam P. Murarka
  • Patent number: 7019328
    Abstract: A transistor is formed by applying modifier coatings to source and drain contacts and/or to the channel region between those contacts. The modifier coatings are selected to adjust the surface energy pattern in the source/drain/channel region such that semiconductor printing fluid is not drawn away from the channel region. For example, the modifier coatings for the contacts can be selected to have substantially the same surface energy as the modifier coating for the channel region. Semiconductor printing fluid deposited on the channel region therefore settles in place (due to the lack of a surface energy differential) and forms a relatively thick active semiconductor region between the contacts. Alternatively, the modifier coatings can be selected to have lower surface energies than the modifier coating in the channel region, which actually causes semiconductor printing fluid to be drawn towards the channel region.
    Type: Grant
    Filed: June 8, 2004
    Date of Patent: March 28, 2006
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Michael L. Chabinyc, Ana C. Arias
  • Patent number: 7015513
    Abstract: An organic adhesive light-emitting device with a vertical structure is provided. The organic adhesive light-emitting device comprises a conductive substrate with a concavo-convex upper surface; a first metal layer formed on the concavo-convex upper surface of the conductive substrate; an organic adhesive material formed over the first metal layer; a second metal layer formed over the organic adhesive material, wherein all or part of the first metal layer over the concavo-convex upper surface is in ohmic contact with the second metal layer through the organic adhesive material; a reflective layer formed over the second metal layer; and a light-emitting stack layer formed over the second metal layer. The process for manufacturing the present invention organic adhesive light-emitting device is less complex than that for manufacturing prior art diodes.
    Type: Grant
    Filed: January 5, 2005
    Date of Patent: March 21, 2006
    Assignee: Epistar Corporation
    Inventor: Min-Hsun Hsieh
  • Patent number: 7009281
    Abstract: A system and method of processing a substrate including loading a substrate into a plasma chamber and setting a pressure of the plasma chamber to a pre-determined pressure set point. Several inner surfaces that define a plasma zone are heated to a processing temperature of greater than about 200 degrees C. A process gas is injected into the plasma zone to form a plasma and the substrate is processed.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: March 7, 2006
    Assignee: Lam Corporation
    Inventors: Andrew D. Bailey, III, Tuqiang Ni
  • Patent number: 7009280
    Abstract: An interlevel dielectric layer (ILD) comprises a low-k dielectric layer; and a low-k dielectric film, deposited under compressive stress, atop the dielectric layer. The dielectric layer comprises a low-k material, such as an organosilicon glass (OSG) or a SiCOH material. The dielectric film has a thickness, which is 2%–10% of the thickness of the dielectric layer, has a similar chemical composition to the dielectric layer, but has a different morphology than the dielectric layer. The dielectric film is deposited under compressive stress, in situ, at or near the end of the dielectric layer deposition by altering a process that was used to deposit the low-k dielectric layer.
    Type: Grant
    Filed: April 28, 2004
    Date of Patent: March 7, 2006
    Assignee: International Business Machines Corporation
    Inventors: Matthew Angyal, Edward Paul Barth, Sanjit Kumar Das, Charles Robert Davis, Habib Hichri, William Francis Landers, Jia Lee
  • Patent number: 6992371
    Abstract: A novel device, such as a semiconductor device, a microfluidic device, a surface acoustic wave device an imprint template, or the like, including an amorphous carbon layer for improved adhesion of organic layers and method of fabrication. The device includes a substrate having a surface, an amorphous carbon layer, formed overlying the surface of the substrate, and a low surface energy material layer overlying the surface of the substrate. The device is formed by providing a substrate having a surface, depositing a low surface energy material layer and an amorphous carbon layer overlying the surface of the substrate adjacent the low surface energy material layer using plasma enhanced chemical vapor deposition (PECVD) or sputtering.
    Type: Grant
    Filed: July 16, 2004
    Date of Patent: January 31, 2006
    Assignee: Freescale Semiconductor, Inc.
    Inventors: David P. Mancini, Jaime A. Quintero, Doug J. Resnick, Steven M. Smith
  • Patent number: 6984875
    Abstract: A semiconductor device includes an insulating layer, a conducting portion, and a modified layer. The insulating layer is formed on a semiconductor substrate. The conducting portion is formed in the insulating layer. The modified layer is formed between the insulating layer and the conducting portion. The insulating layer includes hydrogenated polysiloxane. The modified layer is a layer to which the hydrogenated polysiloxane is modified. A portion of the modified layer far from the semiconductor substrate may be thicker than a portion of the modified layer near the semiconductor substrate.
    Type: Grant
    Filed: January 28, 2004
    Date of Patent: January 10, 2006
    Assignee: NEC Electronics Corporation
    Inventor: Tatsuya Usami
  • Patent number: 6974970
    Abstract: Thin films are disclosed that are suitable as dielectrics in IC's and for other similar applications. In particular, the invention concerns thin films comprising compositions obtainable by hydrolysis of two or more silicon compounds, which yield an at least partially cross-linked siloxane structure. The invention also concerns a method for producing such films by preparing siloxane compositions by hydrolysis of suitable reactants, by applying the hydrolyzed compositions on a substrate in the form of a thin layer and by curing the layer to form a film. In one example, a thin film comprising a composition is obtained by hydrolyzing a monomeric silicon compound having at least one hydrocarbyl radical, containing an unsaturated carbon-to-carbon bond, and at least one hydrolyzable group attached to the silicon atom of the compound with another monomeric silicon compound having at least one aryl group and at least one hydrolyzable group attached to the silicon atom of the compound to form a siloxane material.
    Type: Grant
    Filed: January 17, 2003
    Date of Patent: December 13, 2005
    Assignee: Silecs Oy
    Inventors: Juha T. Rantala, Jason S. Reid, Nungavram S. Viswanathan, T. Teemu T. Tormanen
  • Patent number: 6974762
    Abstract: A method of silanizing the surface of a low-k interlayer dielectric oxides (carbon doped oxides or organo-silicate glasses) to improve surface adhesion to adjacent thin film layers in damascene integration of microelectronic devices. A low-k interlayer dielectric oxide may be exposed to the vapor of a silane-coupling agent in order to modify its surface energy to improve adhesion with adjacent thin film layers. A low-k interlayer dielectric oxide can also be silanized by dipping the low-k interlayer dielectric oxide in a solution of silane-coupling agent. The silane-coupling agent will cause covalent bonds between the low-k interlayer dielectric oxide and the adjacent thin film thereby improving adhesion.
    Type: Grant
    Filed: August 1, 2002
    Date of Patent: December 13, 2005
    Assignee: Intel Corporation
    Inventors: David H. Gracias, Vijayakumar S. Ramachandrarao
  • Patent number: 6972431
    Abstract: The present invention generally relates to organic photodetectors. Further, it is directed to an optimized organic photodetector having reduced dark current and high efficiency and response time.
    Type: Grant
    Filed: November 26, 2003
    Date of Patent: December 6, 2005
    Assignee: Trustees of Princeton University
    Inventors: Stephen R. Forrest, Jiangeng Xue
  • Patent number: 6967389
    Abstract: A semiconductor chip module and forming method is provided. The module includes a support member having at least one well being open to receive a semiconductor chip. Each well depth is substantially equal to the thickness of a chip. The support member has a planar region surrounding each well. A chip is in each well. A dielectric sheet of material is laminated over each chip and extends onto the planar area surrounding the wells and has a face oriented away from the chip. Electrical circuitry including capture pads is formed on the face of the dielectric sheet and extends onto the sheet that overlies the planar region. Conducting vias are formed in the dielectric sheet connecting the electrical circuitry on the dielectric sheet with the contact pads on the chip. A multilayer, circuitized laminate having a fan-out pattern is laminated to the dielectric sheet.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: November 22, 2005
    Assignee: International Business Machines Corporation
    Inventors: William Infantolino, Voya R. Markovich, Sanjeev B. Sathe, George H. Thiel
  • Patent number: 6965158
    Abstract: Multi-layer components such as circuit panels are fabricated by connecting conductive features such as traces one two or more superposed substrates using leads extending through an intermediate dielectric layer. The leads can be closely spaced to provide a high density vertical interconnection, and can be selectively connected to provide customization of the structure.
    Type: Grant
    Filed: June 11, 2002
    Date of Patent: November 15, 2005
    Assignee: Tessera, Inc.
    Inventors: John W. Smith, Belgacem Haba
  • Patent number: 6963137
    Abstract: This invention relates to low dielectric constant layers formed on the substrate having: (a) a base zone, adjacent the substrate, having pores distributed therein, at least the majority of the pores having diameters in the range 1 to 10 nm; (b) an atomically smooth surface zone, spaced from the substrate; and (c) an intermediate zone having pores distributed therein, at least the majority of the pores having diameters equal to or less than 2 nm so that there is a general reduction in pore size from the bottom of the layer towards the top.
    Type: Grant
    Filed: July 15, 2002
    Date of Patent: November 8, 2005
    Assignee: Trikon Holdings Limited
    Inventor: Kathrine Giles
  • Patent number: 6963136
    Abstract: Circuit elements and wirings constituting a circuit, and first electrodes electrically connected to such a circuit are provided on one main surface of a semiconductor substrate. An organic insulating film is formed on the circuit except for openings on the surfaces of the first electrodes. First and second external connecting electrodes are provided on the organic insulating film. At least one conductive layer for electrically connecting the first and second external connecting electrodes and the first electrodes is placed on the organic insulating film.
    Type: Grant
    Filed: December 17, 2001
    Date of Patent: November 8, 2005
    Assignees: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Masao Shinozaki, Kenji Nishimoto, Takashi Akioka, Yutaka Kohara, Sanae Asari, Shusaku Miyata, Shinji Nakazato
  • Patent number: 6958525
    Abstract: A low dielectric film forming material contains siloxane resin and polycarbosilane dissolved in solvent. By using this solution, a low dielectric film is formed which contains siloxane resin and polycarbosilane bonded to the siloxane resin. Material of a low dielectric film is provided which is suitable for inter-level insulating film material. A semiconductor device is also provided which has a low dielectric constant film and high reliability.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: October 25, 2005
    Assignee: Fujitsu Limited
    Inventors: Yoshihiro Nakata, Shun-ichi Fukuyama, Katsumi Suzuki, Ei Yano, Tamotsu Owada, Iwao Sugiura
  • Patent number: 6958524
    Abstract: A method of manufacturing an insulating layer, including forming a first dielectric layer having a first pore size over a substrate, shrinking the first pore size to a second pore size by a first densification process, forming a second dielectric layer over the first dielectric layer, and increasing an aggregate dielectric constant of the first and second dielectric layers by a second densification process.
    Type: Grant
    Filed: November 6, 2003
    Date of Patent: October 25, 2005
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lih-Ping Li, Yung-Cheng Lu
  • Patent number: 6958526
    Abstract: An apparatus and method is described incorporating one or more layers of SiCOH and one or more layers of patterned conductors in an integrated circuit chip. The invention overcomes the problem of capacitance by lowering the k of the delectric and overcomes the problem of breakdown voltage and the leakage curent by tailoring the composition of SiCOH.
    Type: Grant
    Filed: January 27, 2004
    Date of Patent: October 25, 2005
    Assignee: International Business Machines Corporation
    Inventors: Stephen McConnell Gates, Alfred Grill
  • Patent number: 6955998
    Abstract: Disclosed is a method for forming a low dielectric layer of a semiconductor device. The method includes the steps of forming a low dielectric polymer layer on a semiconductor substrate and performing an in-situ plasma-assistant surface modification process with respect to the low dielectric polymer layer, thereby forming an adhesion promoter layer on the low dielectric polymer layer. The method prevents a film from being delaminated at an interfacial surface due to film stress or adhesion fault, after processes for forming the low dielectric layer and a low resistance metal wiring have been completed to achieve semiconductor devices operated at a high speed.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: October 18, 2005
    Assignee: Hynix Semiconductor Inc.
    Inventor: Tae Kyung Kim
  • Patent number: 6953984
    Abstract: A low dielectric constant, thermally stable hydrogenated oxidized silicon carbon film which can be used as an interconnect dielectric in IC chips is disclosed. Also disclosed is a method for fabricating a thermally stable hydrogenated oxidized silicon carbon low dielectric constant film utilizing a plasma enhanced chemical vapor deposition technique. Electronic devices containing insulating layers of thermally stable hydrogenated oxidized silicon carbon low dielectric constant materials that are prepared by the method are further disclosed. To enable the fabrication of thermally stable hydrogenated oxidized silicon carbon low dielectric constant film, specific precursor materials having a ring structure are preferred.
    Type: Grant
    Filed: April 19, 2004
    Date of Patent: October 11, 2005
    Assignee: International Business Machines Corporation
    Inventors: Alfred Grill, Christopher Vincent Jahnes, Vishnubhai Vitthalbhai Patel, Laurent Claude Perraud
  • Patent number: 6952036
    Abstract: The present invention provides a thin film transistor structure in which at least a trench is formed in an insulating polymer film formed on a substrate. In the thin film transistor structure, a trench formed in the insulating polymer film accommodates a gate wiring constituted of a plurality of conductive layers. Provided also are a method of manufacturing the thin film transistor structure, and a display device including a thin film transistor array composed of the thin film transistors constituted as described above.
    Type: Grant
    Filed: December 18, 2001
    Date of Patent: October 4, 2005
    Assignee: International Business Machines Corporation
    Inventors: Hiroshi Suzuki, Kuniaki Sueoka
  • Patent number: 6943432
    Abstract: The invention includes a semiconductor construction comprising a semiconductor substrate, and a first layer comprising silicon and nitrogen over the substrate. A second layer comprising at least 50 weight% carbon is over and physically against the first layer, and a third layer consisting essentially of a photoresist system is over and physically against the second layer. The invention also includes methodology for forming the semiconductor construction.
    Type: Grant
    Filed: April 2, 2003
    Date of Patent: September 13, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Yoshiki Hishiro
  • Patent number: 6943431
    Abstract: A semiconductor element is formed over a surface of a semiconductor substrate. A first insulating film is formed over the surface of the semiconductor substrate, the first insulating film covering the semiconductor element. A second insulating film is formed over the first insulating film, the second insulating film having a dielectric constant lower than that of the first insulating film. A first wiring pattern is formed over the second insulating film. A conductive connection member buried in the second and first insulating films electrically interconnects the first wiring pattern and semiconductor element.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: September 13, 2005
    Assignee: Fujitsu Limited
    Inventors: Shun-ichi Fukuyama, Tamotsu Owada, Hiroko Inoue, Ken Sugimoto
  • Patent number: 6943451
    Abstract: Novel semiconductor devices containing a discontinuous cap layer and possessing a relatively low dielectric constant are provide herein. The novel semiconductor devices includes at least a substrate, a first dielectric layer applied on at least a portion of the substrate, a first set of openings formed through the dielectric layer to expose the surface of the substrate so that a conductive material deposited within and filling the openings provides a first set of electrical contact conductive elements and a discontinuous layer of cap material covering at least the top of the conductive elements to provide a first set of discontinuous cap elements. Methods for forming the semiconductor devices are also provided.
    Type: Grant
    Filed: July 2, 2001
    Date of Patent: September 13, 2005
    Assignee: International Business Machines Corporation
    Inventors: Stanley Joseph Whitehair, Stephen McConnell Gates, Sampath Purushothaman, Satyanarayana V. Nitta, Maurice McGlashan-Powell, Kevin S. Petrarca
  • Patent number: 6933246
    Abstract: A low k porous dielectric film is described wherein the exposed surface or surfaces of the film are substantially non-porous. A densification method is described for treating such exposed surfaces to render porous surfaces non-porous.
    Type: Grant
    Filed: June 13, 2003
    Date of Patent: August 23, 2005
    Assignee: Trikon Technologies Limited
    Inventors: Keith Edward Buchanan, Joon-Chai Yeoh
  • Patent number: 6924545
    Abstract: A low-dielectric-constant interlayer insulating film, which is composed of at least one selected from the group consisting of: (i) a low-dielectric-constant borazine-silicon-based polymer substance obtainable by reaction of, in the presence of a platinum catalyst, B,B?,B?-triethynyl-N,N?,N?-trimethylborazine with a specific silicon compound having at least two hydrosilyl groups; and (ii) a low-dielectric-constant borazine-silicon-based polymer substance obtainable by reaction of, in the presence of a platinum catalyst, B,B?,B?-triethynyl-N,N?,N?-trimethylborazine with a specific cyclic silicon compound having at least two hydrosilyl groups. A semiconductor device, which has the low-dielectric-constant interlayer insulating film. A low-refractive-index material, which is composed of the polymer substance (i) and/or (ii).
    Type: Grant
    Filed: March 11, 2002
    Date of Patent: August 2, 2005
    Assignees: National Institute of Advanced Industrial Science, Technology Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yuko Uchimaru, Masami Inoue
  • Patent number: 6914258
    Abstract: A field effect transistor in sandwiched configuration having organic semiconductor, comprising: a substrate (1), a gate electrode (2) formed on the surface of the substrate (1), a gate insulation layer (3) formed on the substrate (1) and the gate insulation layer (2), which is characterized in that, further comprising: an active layer (4) formed on the gate insulation layer (3) but leaving a part of the gate insulation layer (3) to be exposed, a source and drain electrodes (5) formed on a part of the gate insulation layer (3) and a part of the active layer (4), and an active layer (6) formed on the exposed part of the gate insulation layer (3), the active layer (4), the source electrode and the drain electrode (5).
    Type: Grant
    Filed: August 21, 2003
    Date of Patent: July 5, 2005
    Assignee: Changchun Institute of Applied Chemistry Chinese Academy of Science
    Inventors: Donghang Yan, Jun Wang, Jian Zhang
  • Patent number: 6913814
    Abstract: A lamination process and structure of a high layout density substrate is disclosed. The lamination process comprises the following steps. First of all, a plurality of laminating layers are individually formed, wherein each laminating layer has a first dielectric layer, a plurality of first vias and a patterned conducting layer. Next, a bottom layer having a second dielectric layer and a plurality of second vias is formed. Then, the laminating layers and the bottom layer are stacked. Finally, the laminating layers and the bottom layer are laminated simultaneously to form a multiplayer substrate at one time.
    Type: Grant
    Filed: November 19, 2003
    Date of Patent: July 5, 2005
    Assignee: Via Technologies, Inc.
    Inventors: Kwun Yao Ho, Moriss Kung
  • Patent number: 6891190
    Abstract: An organic semiconductor device (11) can be embedded within a printed wiring board (10). In various embodiments, the embedded device (11) can be accompanied by other organic semiconductor devices (31) and/or passive electrical components (26). When so embedded, conductive vias (41, 42, 43) can be used to facilitate electrical connection to the embedded device. In various embodiments, specific categories of materials and/or processing steps are used to facilitate the making of organic semiconductors and/or passive electrical components, embedded or otherwise.
    Type: Grant
    Filed: May 23, 2002
    Date of Patent: May 10, 2005
    Assignee: Motorola, Inc.
    Inventors: Ke Keryn Lian, Robert T. Croswell, Aroon Tungare, Manes Eliacin
  • Patent number: 6885025
    Abstract: The present invention relates to organic light emitting devices (OLEDs). The devices of the present invention are efficient white or multicolored phosphorescent OLEDs which have a high color stability over a wide range of luminances. The devices of the present invention comprise an emissive region having at least two emissive layers, with each emissive layer comprising a different host and emissive dopant, wherein at least one of the emissive dopants emits by phosphorescence.
    Type: Grant
    Filed: July 10, 2003
    Date of Patent: April 26, 2005
    Assignee: Universal Display Corporation
    Inventors: Yeh-Jiun Tung, Michael Lu, Raymond C. Kwong
  • Patent number: 6879026
    Abstract: An adhesive film for protecting the surface of a semiconductor wafer wherein the adhesive layer is formed on one surface of a substrate film, the substrate film comprising at least one layer which satisfies the following requisites (A) and at least one of (B) or (C): requisite (A): high elastic modulus properties in which the storage modulus is 1×109 Pa to 1×1010 Pa under the total temperature range of from 18 to 50° C. requisite (B): high elastic modulus properties in which the storage modulus within at least part of the temperature range of from 50 to 90° C. is not more than 1×108 Pa. requisite (C): high elastic modulus properties with expansibility by water absorption in which the size-changing ratio by absorbing water for four hours is 0.05 to 0.5% at 23° C. and 90% RH.
    Type: Grant
    Filed: January 10, 2003
    Date of Patent: April 12, 2005
    Assignee: Mitsui Chemicals, Inc.
    Inventors: Hideki Fukumoto, Takanobu Koshimizu, Makoto Kataoka, Yoshihisa Saimoto
  • Patent number: 6878961
    Abstract: A method of making organic memory cells made of two electrodes with a controllably conductive media between the two electrodes is disclosed. The controllably conductive media contains an organic semiconductor layer that contains a photosensitive compound. The organic semiconductor layer is formed into memory cells using patterning techniques.
    Type: Grant
    Filed: September 28, 2004
    Date of Patent: April 12, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Christopher F. Lyons, Ramkumar Subramanian, Mark S. Chang
  • Patent number: 6867434
    Abstract: A resin material having a small relative dielectric constant is used as a layer insulation film 114. The resin material has a flat surface. A black matrix or masking film for thin film transistors is formed thereon using a metal material. Such a configuration prevents the problem of a capacity generated between the masking film and a thin film transistor.
    Type: Grant
    Filed: April 30, 2002
    Date of Patent: March 15, 2005
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 6864580
    Abstract: A semiconductor device having a structure in which no short circuit occurs between plug interconnections even when a void occurs in an insulating layer in a gap between wiring layers and a method of manufacturing the same are attained. The method includes: a step of forming transfer gates so as to be close to each other with a gap on a semiconductor substrate; a step of burying the gap and covering a wiring layer; a step of opening a contact hole in an insulating layer in the gap portion; a step of depositing a short-circuit preventing insulating film in the contact hole; an etch back step of removing the short-circuit preventing insulating film at least on the bottom of the gap to expose the semiconductor substrate; and a step of forming a plug interconnection.
    Type: Grant
    Filed: July 27, 2001
    Date of Patent: March 8, 2005
    Assignees: Renesas Technology Corp., Ryoden Semiconductor System Engineering Corporation
    Inventors: Shoichiro Nakazawa, Heiji Kobayashi
  • Patent number: 6861763
    Abstract: A method for forming packaged substrates includes using a stereolithographic process to form a protective dielectric polymeric sealing structure on at least the active surface of the substrate which includes one or more flip-chip dice. In addition, the invention encompasses forming a similar layer on a second substrate to be joined to the first substrate. Contact pads of the second substrate are exposed through the layer thereon to facilitate joining of the two substrates. Semiconductor devices formed by the method are also disclosed.
    Type: Grant
    Filed: December 11, 2002
    Date of Patent: March 1, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Salman Akram
  • Patent number: 6861670
    Abstract: The object is to pattern extremely fine integrated circuits by forming fine contact holes. The dry etching method is employed to form contact holes to pattern a wiring (114), using a mask made of metallic film (112) and an organic material as an inter-layer insulating film (111) for covering switching elements and each of the wirings.
    Type: Grant
    Filed: March 28, 2000
    Date of Patent: March 1, 2005
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisashi Ohtani, Misako Nakazawa, Satoshi Murakami, Etsuko Fujimoto
  • Patent number: 6849926
    Abstract: A composite containing nano magnetic particles is provided. The composite includes nano magnetic particles in a dielectric matrix. The matrix is made of an inorganic material such as silica, alumina, or hydrosilsesquioxane, or an organic material such as polyimide, polymethyl methacrylate, or methyl silsesquioxane. The nano magnetic particles consist of Fe2O3, chromium oxide, europium oxide, NiZn-ferrite, MnZn-ferrite, yttrium-iron garnet, or indium In.
    Type: Grant
    Filed: April 23, 2001
    Date of Patent: February 1, 2005
    Assignee: Pohang University of Science and Technology Foundation
    Inventors: Chan Eon Park, Jin Ho Kang
  • Patent number: 6849927
    Abstract: A typical integrated circuit interconnects millions of microscopic transistors and resistors with aluminum wires buried in silicon-dioxide insulation. Yet, aluminum wires and silicon-dioxide insulation are a less attractive combination than gold, silver, or copper wires combined with polymer-based insulation, which promise both lower electrical resistance and capacitance and thus faster, more efficient circuits. Unfortunately, conventional etch-based techniques are ineffective with gold, silver, or copper, and conventional polymer formation promote reactions with metals that undermine the insulative properties of polymer-based insulations. Accordingly, the inventor devised methods which use a liftoff procedure to avoid etching problems and a non-acid-polymeric precursor and non-oxidizing cure procedure to preserve the insulative properties of the polymeric insulator. The resulting interconnective structures facilitate integrated circuits with better speed and efficiency.
    Type: Grant
    Filed: February 20, 2001
    Date of Patent: February 1, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Paul A. Farrar
  • Patent number: 6838054
    Abstract: Biochemical devices comprising a sensing surface that is at least partially covered by a nanocrystalline metal oxide semiconductor film which provides a recipient surface for immobilizing biochemical species on. The film has a mesoporous surface that gives up to a 1000 increase in biochemical species adsorption when compared to a flat surface. The biochemical devices comprising these surfaces can be optical and electrochemical biosensors and reactors for synthetic or biodegradation reactions.
    Type: Grant
    Filed: March 31, 1999
    Date of Patent: January 4, 2005
    Assignee: Imperial College of Science, Technology and Medicine
    Inventor: James Robert Durrant
  • Patent number: 6835950
    Abstract: An organic electronic device structure, according to a first aspect of the invention, includes: (a) a substrate layer; (b) an organic electronic region disposed over the substrate layer; (c) a pressure sensitive adhesive layer disposed over the organic electronic device; and (d) a barrier layer disposed over the adhesive layer. According to a second aspect of the present invention, an organic electronic device structure includes: (a) a substrate layer; (b) an organic electronic region disposed over the substrate layer; (c) a barrier layer disposed over the organic electronic region; (d) a pressure sensitive adhesive layer disposed over the substrate layer and over the barrier layer; and (e) an additional layer disposed over the adhesive layer. In many preferred embodiments, the organic electronic device region is an OLED region.
    Type: Grant
    Filed: April 12, 2002
    Date of Patent: December 28, 2004
    Assignee: Universal Display Corporation
    Inventors: Julia J. Brown, Jeffrey Alan Silvernail, Michael Stuart Weaver, Anna Chwang
  • Patent number: 6831366
    Abstract: A low-k dielectric metal conductor interconnect structure having no micro-trenches present therein and a method of forming such a structure are provided. Specifically, the above structure is achieved by providing an interconnect structure which includes at least a multilayer of dielectric materials which are applied sequentially in a single spin apply tool and then cured in a single step and a plurality of patterned metal conductors within the multilayer of spun-on dielectrics. The control over the conductor resistance is obtained using a buried etch stop layer having a second atomic composition located between the line and via dielectric layers of porous low-k dielectrics having a first atomic composition. The inventive interconnect structure also includes a hard mask which assists in forming the interconnect structure of the dual damascene-type.
    Type: Grant
    Filed: March 25, 2003
    Date of Patent: December 14, 2004
    Assignee: International Business Machines Corporation
    Inventors: Stephen McConnell Gates, Jeffrey Curtis Hedrick, Satyanarayana V. Nitta, Sampath Purushothaman, Cristy Sensenich Tyberg
  • Patent number: 6828683
    Abstract: In one aspect, the invention encompasses a semiconductor processing method wherein a conductive copper-containing material is formed over a semiconductive substrate and a second material is formed proximate the conductive material. A barrier layer is formed between the conductive material and the second material. The barrier layer comprises a compound having silicon chemically bonded to both nitrogen and an organic material. In another aspect, the invention encompasses a composition of matter comprising silicon chemically bonded to both nitrogen and an organic material. The nitrogen is not bonded to carbon. In yet another aspect, the invention encompasses a semiconductor processing method. A semiconductive substrate is provided and a layer is formed over the semiconductive substrate. The layer comprises a compound having silicon chemically bonded to both nitrogen and an organic material.
    Type: Grant
    Filed: December 23, 1998
    Date of Patent: December 7, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Weimin Li, Zhiping Yin
  • Patent number: 6812551
    Abstract: Defect-free dielectric coatings comprised of porous polymeric matrices are prepared using nitrogen-containing polymers as pore-generating agents. The dielectric coatings are useful in a number of contexts, including the manufacture of electronic devices such as integrated circuit devices and integrated circuit packaging devices. The dielectric coatings are prepared by admixing, in a solvent, a polymeric nitrogenous porogen with a high temperature, thermosetting host polymer miscible therewith, coating a substrate surface with the admixture, heating the uncured coating to cure the host polymer and provide a vitrified, two-phase matrix, and then decomposing the porogen. The dielectric coatings so prepared have few if any defects, and depending on the amount and molecular weight of porogen used, can be prepared so as to have an exceptionally low dielectric constant on the order of 2.5 or less, preferably less than about 2.0.
    Type: Grant
    Filed: February 21, 2003
    Date of Patent: November 2, 2004
    Assignee: International Business Machines Corporation
    Inventors: Craig Jon Hawker, James Lupton Hedrick, Elbert Emin Huang, Victor Yee-Way Lee, Teddie Magbitang, David Mecerreyes, Robert Dennis Miller, Willi Volksen
  • Publication number: 20040201011
    Abstract: Disclosed are an organic semiconductor material having high charge mobility characteristics and an organic semiconductor element. The organic semiconductor material has rodlike low-molecular liquid crystallinity, comprising: a skeleton structure comprising L 6 &pgr; electron aromatic rings, M 10 &pgr; electron aromatic rings, and N 14 &pgr; electron aromatic rings, wherein L, M, and N are each an integer of 0 (zero) to 4 and L+M+N=1 to 4; and a terminal structure attached to both ends of the skeleton structure. The terminal structure can develop liquid crystallinity. The phase angle &thgr; of impedance of the organic semiconductor material is −80°≦&thgr;≦−90° as determined in the measurement of impedance in a frequency f range of 100 Hz≦f≦1 MHz in such a state that the organic semiconductor material in an isotropic phase state is held between a pair of opposed substrates with an interelectrode spacing of 9 &mgr;m.
    Type: Application
    Filed: October 30, 2003
    Publication date: October 14, 2004
    Inventors: Shinobu Sakurada, Ken Tomino, Hiroki Maeda, Masanori Akada, Jun-Ichi Hanna
  • Publication number: 20040195660
    Abstract: The object of the invention is to provide a porous film having the dielectric constant of 2.2 or less and having practicable mechanical strength.
    Type: Application
    Filed: March 23, 2004
    Publication date: October 7, 2004
    Applicants: Shin-Etsu Chemical Co., Ltd., Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshitaka Hamada, Takeshi Asano, Hideo Nakagawa, Masaru Sasago