Abstract: An object of the present invention is to provide a method for manufacturing an electronic circuit component such as an organic TFT 1, which can manufacture an electronic circuit component excellent in reliability and having quality on a practical level, because an insulating layer and a conductive layer which have more excellent characteristics can be formed, particularly, on a general-purpose plastic substrate or the like by treatment at a process temperature of 200° C. or lower which has no influence on the above-mentioned plastic substrate. The method for manufacturing an electronic circuit component according to the invention includes heating a layer containing at least one of a polyimide and a precursor thereof at a temperature of 200° C.

Abstract: A method for manufacturing a semiconductor device including covering a portion of at least one semiconductor device with a foil, including covering at least one target region of the semiconductor device, and illuminating the foil with a laser to singulate from the foil a portion covering the at least one target region of the at least one semiconductor device.

Abstract: In order to improve the reliability of a semiconductor device having a fuse formed by a Damascene technique, a barrier insulating film and an inter-layer insulating film are deposited over a fourth-layer wiring and a fuse. The barrier insulating film is an insulating film for preventing the diffusion of Cu and composed of a SiCN film deposited by plasma CVD like the underlying barrier insulating film. The thickness of the barrier insulating film covering the fuse is larger than the thickness of the underlying barrier insulating film so as to improve the moisture resistance of the fuse.

Abstract: The present invention relates to a dicing film having an adhesive film for dicing a wafer and a die adhesive film, which are used for manufacturing a semiconductor package, and a method of manufacturing a semiconductor package using the same. More particularly, the present invention relates to a dicing film wherein a shrinkage release film is inserted between an adhesive film for dicing a wafer and a die adhesive film so that the die adhesive film and a die can be easily separated from the adhesive film for dicing a wafer when picking up a semiconductor die, and a method of manufacturing a semiconductor package using the same.

Abstract: An electronic device includes a substrate, a first organic electronic component overlying the substrate, wherein, from a plan view, the first organic electronic component defines a perimeter of a first pixel area, and at least one post structure, wherein the at least one post structure lies within the perimeter of the first pixel area. The electronic device can also include a confinement structure overlying the substrate and having a first opening, wherein from a plan view, the first opening has a perimeter that substantially corresponds to a perimeter of the first organic electronic component.

Abstract: Methods of forming a light emitting device include selectively forming a wavelength conversion structure on a light emitting element using stereolithography. Selectively forming the wavelength conversion structure may include covering the light emitting element with a photo-curable liquid polymer containing a luminescent material, and exposing the liquid polymer to light for a time sufficient to at least partially cure the liquid polymer. Multiple layers of polymer can be selectively built up to form a wavelength conversion structure having a custom shape on the light emitting element.

Abstract: In one embodiment, the present invention is a method and apparatus for chip cooling. One embodiment of an inventive method for bonding a liquid metal to an interface surface (e.g., a surface of an integrated circuit chip or an opposing surface of a heat sink) includes applying an adhesive to the interface surface. A metal film is then bonded to the adhesive, thereby easily adapting the interface surface for bonding to the liquid metal.

Abstract: The present invention provides a semiconductor device for which thermal stress at mounting is reduced and a reduction in reliability with regard to moisture absorption is prevented. The semiconductor device includes a uppermost metal layer 12, a solder bump 17, metals 15 and 16 which connect an uppermost metal layer 12 and the solder bump 17, and, a polyimide multilayer 14 having formed therein an opening 14x in which the metals 15 and 16 are provided. The polyimide multilayer 14 includes a first polyimide layer 14A and a second polyimide layer 14B formed on the first polyimide layer 14A. The second polyimide layer 14B is softer than the first polyimide layer 14A. A thermal stress at mounting is reduced by the second polyimide layer 14B. Since the first polyimide layer 14A has a higher strength than the second polyimide layer 14B, even if cracking occurs in the second polyimide layer 14B, the cracks are prevented from developing in the first polyimide layer 14A.

Abstract: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer.

Abstract: Embodiments of semiconductor devices are provided. In one embodiment, the semiconductor device includes a substrate, an etch stop layer formed on the substrate, an adhesion promotion layer formed directly on the etch stop layer, and a dielectric layer formed directly on the adhesion promotion layer. The etch stop layer may include silicon, carbon, and nitrogen. The dielectric layer may include silicon, oxygen, and carbon. The adhesion promotion layer may include carbon, oxygen, and nitrogen. An example of an adhesion promotion layer includes polyimide.

Abstract: Methods for the addition polymerization of cycloolefins using a cationic Group 10 metal complex and a weakly coordinating anion of the formula: [(R?)zM(L?)x(L?)y]b[WCA]d wherein [(R?)zM(L?)x(L?)y] is a cation complex where M represents a Group 10 transition metal; R? represents an anionic hydrocarbyl containing ligand; L? represents a Group 15 neutral electron donor ligand; L? represents a labile neutral electron donor ligand; x is 1 or 2; and y is 0, 1, 2, or 3; and z is 0 or 1, wherein the sum of x, y, and z is 4; and [WCA] represents a weakly coordinating counteranion complex; and b and d are numbers representing the number of times the cation complex and weakly coordinating counteranion complex are taken to balance the electronic charge on the overall catalyst complex.

Abstract: A resin composition for sealing a light-emitting device of the present invention includes a silsesquioxane resin including two or more oxetanyl groups, an aliphatic hydrocarbon including one or more epoxy groups and a cationic polymerization initiator. Furthermore, a lamp of the present invention includes a package equipped with a cup-shaped sealing member, an electrode exposed in the bottom portion of the sealing member, and a light-emitting device arranged on the bottom portion and electrically connected with the electrode, wherein the light-emitting device is sealed with the above-described resin composition for sealing a light-emitting device filled in the sealing member.

Abstract: Various semiconductor chip reinforcement structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor chip that has a side and forming a polymer layer on the side. The polymer layer has a central portion and a first frame portion spatially separated from the central portion to define a first channel. An underfill material may be provided to invade the channel and establish a mechanical joint between the polymer layer and the underfill material.

Abstract: A transistor including a semiconductive layer; and a gate dielectric layer comprising an insulating polymer, characterised in that the insulating polymer is crosslinked and comprises one or more units having a low cohesive-energy-density and one or more crosslinking groups and the insulating polymer includes substantially no residual —OH leaving groups.

Abstract: The present invention provides patterned features of dimensions of less than 50 nm on a substrate. According to various embodiments, the features may be “Manhattan” style structures, have high aspect ratios, and/or have atomically smooth surfaces. The patterned features are made from polymer brushes grafted to a substrate. In some embodiments, the dimensions of the features may be determined by adjusting the grafting density and/or the molecular weight of the brushes. Once the brushes are patterned, the features can be shaped and reshaped with thermal or solvent treatments to achieve the desired profiles. The chemical nature of the polymer brush is thus independent of the patterning process, which allows for optimization of the polymer brush used for specific applications. Applications include masks for pattern transfer techniques such as reactive ion etching.

Abstract: The present invention relates to a resin for optical-semiconductor-element encapsulation containing a polyimide which is produced by imidizing a polyimide precursor obtained by subjecting 5-norbornene-2,3-dicarboxylic anhydride or maleic anhydride, an aliphatic tetracarboxylic dianhydride, and an aliphatic diamine compound to a condensation polymerization reaction. The resin of the invention has excellent heat resistance and excellent light-transmitting properties. In addition, the present invention also relates to an optical semiconductor device containing an optical semiconductor element encapsulated with the resin.

Abstract: Dielectric materials comprising release agents are described. Also described are a process for improving the processability of dielectric materials during hot embossing, substrates prepared by hot embossing, and integrated-circuit packages comprising the improved substrate.

Abstract: According to one aspect of the invention, a method of constructing a memory array is provided. An insulating layer is formed on a semiconductor wafer. A first metal stack is then formed on the insulating layer and etched to form first metal lines. A polymeric layer is formed over the first metal lines and the insulating layer. A puddle of smoothing solvent is then allowed to stand on the wafer. The smoothing solvent is then removed. After the smoothing solvent is removed, the polymeric layer has a reduced surface roughness. A second metal stack is then formed on the polymeric layer and etched to form second metal lines.

Abstract: Structures are provided that include a conducting layer disposed on a layered arrangement of a diffusion barrier layer and a seed layer in an integrated circuit. Apparatus and systems having such structures and methods of forming these structures for apparatus and systems are disclosed.

Abstract: A bilayer porous low dielectric constant (low-k) interconnect structure and methods of fabricating the same are presented. A preferred embodiment having an effective dielectric constant of about 2.2 comprises a bottom deposited dielectric layer and a top deposited dielectric layer in direct contact with the former. The bottom layer and the top layer have same atomic compositions, but a higher dielectric constant value k. The bottom dielectric layer serves as an etch stop layer for the top dielectric layer, and the top dielectric layer can act as CMP stop layer. One embodiment of making the structure includes forming a bottom dielectric layer having a first porogen content and a top dielectric layer having a higher porogen content. A curing process leaves lower pore density in the bottom dielectric layer than that left in the top dielectric layer, which leads to higher dielectric value k in the bottom dielectric layer.

Abstract: A method for forming self-assembled patterns on a substrate surface is provided. First, a block copolymer layer, which comprises a block copolymer having two or more immiscible polymeric block components, is applied onto a substrate that comprises a substrate surface with a trench therein. The trench specifically includes at least one narrow region flanked by two wide regions, and wherein the trench has a width variation of more than 50%. Annealing is subsequently carried out to effectuate phase separation between the two or more immiscible polymeric block components in the block copolymer layer, thereby forming periodic patterns that are defined by repeating structural units. Specifically, the periodic patterns at the narrow region of the trench are aligned in a predetermined direction and are essentially free of defects. Block copolymer films formed by the above-described method as well as semiconductor structures comprising such block copolymer films are also described.

Abstract: An image sensor including a second line formed at an upper part of a photodiode region as a transparent electrode for passing light. The second line is composed of a polymeric material having transparency and conductivity.

Abstract: A semiconductor device and an electro-optical device that ensures a stable output are provided even when there is a change in a source-drain current in a saturated operation region of a thin film transistor due to kink effects. The thin film transistor has a multi-gate structure with a polycrystalline silicon film as an active layer, and a source-side first thin film transistor portion and a drain-side second thin film transistor portion connected in series. The first thin film transistor portion has a drain-side back gate electrode that is connected with a first front gate electrode. The second thin film transistor portion has a source-side back gate electrode that is connected with a second front gate electrode.

Abstract: Disclosed are semiconductor devices containing a polymer dielectric and at least one active device containing an organic semiconductor material and a passive layer. Also disclosed are semiconductor devices further containing a conductive polymer. Such devices are characterized by light weight and robust reliability.

Abstract: In order to improve the reliability of a semiconductor device having a fuse formed by a Damascene technique, a barrier insulating film and an inter-layer insulating film are deposited over a fourth-layer wiring and a fuse. The barrier insulating film is an insulating film for preventing the diffusion of Cu and composed of a SiCN film deposited by plasma CVD like the underlying barrier insulating film. The thickness of the barrier insulating film covering the fuse is larger than the thickness of the underlying barrier insulating film so as to improve the moisture resistance of the fuse.

Abstract: The present invention provides a semiconductor device for which thermal stress at mounting is reduced and a reduction in reliability with regard to moisture absorption is prevented. The semiconductor device includes a uppermost metal layer 12, a solder bump 17, metals 15 and 16 which connect an uppermost metal layer 12 and the solder bump 17, and, a polyimide multilayer 14 having formed therein an opening 14x in which the metals 15 and 16 are provided. The polyimide multilayer 14 includes a first polyimide layer 14A and a second polyimide layer 14B formed on the first polyimide layer 14A. The second polyimide layer 14B is softer than the first polyimide layer 14A. A thermal stress at mounting is reduced by the second polyimide layer 14B. Since the first polyimide layer 14A has a higher strength than the second polyimide layer 14B, even if cracking occurs in the second polyimide layer 14B, the cracks are prevented from developing in the first polyimide layer 14A.

Abstract: Provided is a field-effect transistor (10) which comprises a metal or carbon source electrode (14) and a layer of a functional organic semiconductor (28). A column of an injection material (48) extends through the layer of the functional organic semiconductor (28), the column being in contact with both the source electrode (14) and the layer of the functional organic semiconductor (28). This column (48) facilitates the transfer charge carriers between the source electrode (14) and semiconductor layer (28). The injection material is preferably an organic compound such as 3-hexylthiophene, polyarylamine, poly(3,4-ethylenedioxythiophene)-polystyrenesulphonic acid or polyaniline.

Abstract: A method for manufacturing an alignment layer is provided, which includes the following steps. First, a substrate is provided. Next, an auxiliary layer is formed on the substrate. Then, an alignment solution is sprayed on the auxiliary layer through an inkjet printing process. The alignment solution includes an alignment material and a first solvent, and the auxiliary layer has the same polarity as the first solvent. Then, by performing a curing process, the alignment solution is cured to form an alignment layer. As mentioned above, the method for manufacturing an alignment layer may be applied to manufacture an alignment layer with preferred smoothness.

Abstract: A method of forming an organic semiconductor pattern is provided. A pattern is formed on a first substrate. An adhesive is coated on the pattern to form an adhesive pattern. An organic semiconductor layer is formed on a second substrate. The second substrate is combined with the first substrate to remove a portion of the organic semiconductor layer attached to the pattern from the second substrate to form the organic semiconductor pattern.

Abstract: The present invention relates to interlayer dielectric materials and pre-applied die attach adhesives, more specifically pre-applied die attach adhesives (such as wafer and other substrate-applied die attach adhesives), methods of applying the interlayer dielectric materials onto substrates to prepare low K dielectric semiconductor chips, methods of applying the pre-applied die attach adhesives onto wafer and other substrate surfaces, and assemblies prepared therewith for connecting microelectronic circuitry.

Abstract: Polymerized materials for forming the underfill and encapsulation structures for semiconductor package are disclosed. A filler constituent, such as boron nitride, silicates, elemental metals, or alloys, may be added to a liquid photopolymer resin to tailor the physical properties thereof upon curing. The filler constituents may be employed to alter the coefficient of thermal expansion, thermal conductivity, or electrical conductivity of the polymerized material. A number of different embodiments are disclosed that employ the above materials in selected regions of the underfill and encapsulation structures of the semiconductor package. The polymerized materials may also be used to form support structures and covers for optically interactive semiconductor devices. Methods for forming the above structures using stereolithography are also disclosed.

Abstract: The present invention provides patterned features of dimensions of less than 50 nm on a substrate. According to various embodiments, the features may be “Manhattan” style structures, have high aspect ratios, and/or have atomically smooth surfaces. The patterned features are made from polymer brushes grafted to a substrate. In some embodiments, the dimensions of the features may be determined by adjusting the grafting density and/or the molecular weight of the brushes. Once the brushes are patterned, the features can be shaped and reshaped with thermal or solvent treatments to achieve the desired profiles. The chemical nature of the polymer brush is thus independent of the patterning process, which allows for optimization of the polymer brush used for specific applications. Applications include masks for pattern transfer techniques such as reactive ion etching.

Abstract: Organic polymers for use in electronic devices, wherein the polymer includes repeat units of the formula: wherein: each R1 is independently H, an aryl group, Cl, Br, I, or an organic group that includes a crosslinkable group; each R2 is independently H, an aryl group or R4; each R3 is independently H or methyl; each R5 is independently an alkyl group, a halogen, or R4; each R4 is independently an organic group that includes at least one CN group and has a molecular weight of about 30 to about 200 per CN group; and n=0-3; with the proviso that at least one repeat unit in the polymer includes an R4. These polymers are useful in electronic devices such as organic thin film transistors.

Abstract: An improved structure for supporting a microcalorimeter device is disclosed. The structure comprises a substrate with superconducting wiring elements disposed on a surface of the substrate. A membrane layer is suspended above the wiring elements and the substrate surface by a tab element, and a microcalorimeter is disposed on top of the membrane layer. The tab and the membrane layer reside in a common plane, and the membrane layer comprises a material that can be applied and cured at low temperatures (e.g. 350 degrees Celsius or less), so as to have minimal affect on the superconductive wiring elements. The in-plane tab/membrane structure has improved reliability when subject to thermal cycling associated with cryogenic temperatures. A method for forming the structure is also disclosed.

Abstract: An electronic device is provided using wiring comprising aluminum to prevent hillock or whisker from generating, wherein the wiring contains oxygen atoms at a concentration of 8×1018 atoms·cm?3 or less, carbon atoms at a concentration of 5×1018 atoms·cm?3 or less, and nitrogen atoms at a concentration of 7×1017 atoms·cm?3 or less; furthermore, a silicon nitride film is formed on the aluminum gate, and an anodic oxide film is formed on the side planes thereof.

Abstract: Provided are semiconductor low-K Si die wire bonding packages with package stress control and fabrication methods for such packages. The packages include molding interface material applied onto the low-K Si die. In general, the molding interface material is selectively applied onto the low-K Si die surface in order to minimize to safe levels the package stress experienced by the low-K Si die. Selective application includes defining various combinatorial patterns of coated and non-coated regions. In addition, selective application may also include a general application of molding interface material to create a stress buffer zone. The results are packages with less stress experienced by the low-K Si die and so improved reliability (in compliance with industry specifications).

Abstract: A method for producing a chip carrier, the method includes selecting at least one core with a low coefficient of thermal expansion; selecting at least one build-up layer wherein each build-up layer includes a dielectric material and circuitry; and connecting selected cores and selected build-up layers together in a pre-determined order.

Abstract: A method of forming a hydrocarbon-containing polymer film on a semiconductor substrate by a capacitively-coupled plasma CVD apparatus. The method includes the steps of: vaporizing a hydrocarbon-containing liquid monomer (C?H?X?, wherein ? and ? are natural numbers of 5 or more; ? is an integer including zero; X is O, N or F) having a boiling point of about 20° C. to about 350° C. which is not substituted by a vinyl group or an acetylene group; introducing the vaporized gas and CO2 gas or H2 gas into a CVD reaction chamber inside which a substrate is placed; and forming a hydrocarbon-containing polymer film on the substrate by plasma polymerization of the gas, thereby reducing extinction coefficient (k) at 193 nm and increasing mechanical hardness.

Abstract: The present invention provides a COF flexible printed wiring board whose insulating layer is not melt-adhered to a heating tool, and which exhibits no drop in bonding strength during panel bonding carried out after mounting of semiconductor chips, whereby reliability and productivity of a semiconductor chip mounting line is enhanced. The invention also provides a method of producing the COF flexible printed wiring board.

Abstract: The present memory device has first and second electrodes, a passive layer between the first and second electrodes and on and in contact with the first electrode, and an active layer between the first and second electrodes and on and in contact with the passive layer and second electrode, for receiving a charged specie from the passive layer. The active layer is a mixture of (i) a first polymer, and (ii) a second polymer for enhancing ion transport, improving the interface and promoting a rapid and substantially uniform distribution of the charged specie in the active layer, i.e., preventing a localized injection of the charged species. These features result in a memory element with improved stability, a more controllable ON-state resistance, improved switching speed and a lower programming voltage.

Abstract: Dielectric materials comprising release agents are described. Also described are a process for improving the proccessability of dielectric materials during hot embossing, substrates prepared by hot embossing, and integrated-circuit packages comprising the improved substrate.

Abstract: Embodiments of buffer coatings for semiconductor and integrated circuit manufacturing are presented herein.

Abstract: A novel micro optical system as a platform technology for electrical and optical interconnections, thermal and mechanical assembly and integration of electronic, optoelectronic, passive and active components. This platform provides optical coupling and chip-to-chip interconnection by microwave electrical, optical guided and unguided waves, and power or bias electrical contacts or interfaces by a novel chip in flexible circuit, rigid or inflexible embodiments.

Abstract: Systems and methodologies are provided for forming three dimensional memory structures that are fabricated from blocks of individual polymer memory cells stacked on top of each other. Such a polymer memory structure can be formed on top of control component circuitries employed for programming a plurality of memory cells that form the stacked three dimensional structure. Such an arrangement provides for an efficient placement of polymer memory cell on a wafer surface, and increases amount of die space available for circuit design.

Abstract: An electronic device is provided using wiring comprising aluminum to prevent hillock or whisker from generating, wherein the wiring contains oxygen atoms at a concentration of 8×1018 atoms·cm?3 or less, carbon atoms at a concentration of 5×1018 atoms·cm?3 or less, and nitrogen atoms at a concentration of 7×1017 atoms·cm?3 or less; furthermore, a silicon nitride film is formed on the aluminum gate, and an anodic oxide film is formed on the side planes thereof.

Abstract: A semiconductor package including a flexible tape having a mounting portion and an extended portion, a plurality of arrayed connection electrodes provided on the mounting portion of the flexible tape, and a semiconductor chip mounted on the mounting portion of the flexible tape. The semiconductor package further includes a high-speed signal electrode formed at the front end of the extended portion of the flexible tape, and a transmission line provided on the flexible tape for connecting the semiconductor chip and the high-speed signal electrode. A stiffener is mounted on the mounting portion of the flexible tape.

Abstract: A three-dimensionally formed circuit sheet comprises a resin film and a circuit pattern formed of an electrically conductive paste on the resin film. The electrically conductive paste contains, as a binder, a resin that is three-dimensionally formable. The resin film and the circuit pattern are formed in a three-dimensional shape. A method for manufacturing the three-dimensionally formed circuit sheet is also provided. The method comprises forming a circuit pattern on a resin film using an electrically conductive paste by means of printing, wherein the electrically conductive paste contains a resin that is three-dimensionally formable, and press molding the resin film including the circuit pattern into a three-dimensional shape. Additionally, a three-dimensionally formed circuit component comprising a three-dimensionally formed circuit sheet and a base member and a method for manufacturing the same are disclosed.

Abstract: A substrate structure includes a substrate and a number of banks formed on the substrate. The banks and the substrate cooperatively define a number of accommodating rooms. The accommodating rooms are configured for accommodating ink. A spread-control layer is formed on the substrate beneath the accommodating rooms. The spread-control layer enables the ink applied on the spread-control layer to spread at a lower spreading rate than the rate on the substrate without the spread-control layer formed thereon.

Abstract: There are included a semiconductor substrate provided with a desirable element region, an electrode pad formed to come in contact with a surface of the semiconductor substrate or a wiring layer provided on the surface of the semiconductor substrate, a bonding pad formed on a surface of the electrode pad through an intermediate layer, and a resin insulating film for covering a peripheral edge of the bonding pad such that an interface of the bonding pad and the intermediate layer is not exposed to a side wall.

Abstract: A flexible wiring board for tape carrier package having improved flame resistance is disclosed. The flexible wiring board has an insulating film having a bending slit, a wiring pattern formed thereon and crossing the bending slit, an adhesive layer adhering the wiring pattern to the insulating film, a flex resin layer protecting the wiring pattern at the bending slit, and an overcoat layer protecting the wiring pattern, in which the overcoat layer is obtained from a curable resin composition, when cured into a form of film, the film has an initial modulus of 10 to 1,500 MPa at 25° C., an electrical insulation of sufficient level, a soldering resistance of 10 seconds at 260° C., and an oxygen index exceeding 22.0.