Abstract: A thin film transistor and a method of manufacturing the same are disclosed. More specifically, there is provided a thin film transistor having a thin film transistor and a method of manufacturing the same wherein an inorganic layer and an organic planarization layer are sequentially formed on the surface of a substrate on source/drain electrode of a thin film transistor having a semiconductor layer, a gate, source/drain areas and the source/drain electrodes, and a blanket etching process is performed to the organic planarization layer to planarize the inorganic layer. After forming a photoresist pattern on the inorganic layer, an etching process is performed to form a hole coupling a pixel electrode with one of the source/drain electrodes. According to the manufacturing method, the hole may be formed using one mask, thereby simplifying a manufacturing process, and improving an adhesion with the pixel electrode by the inorganic layer formed above.

Abstract: An organic semiconductor element is provided which has the controlled crystalline state of a vapor-deposited pentacene layer and a high mobility with low voltage driving. The organic semiconductor element is formed by providing a gate electrode 101 on the surface of a substrate 102, providing thereon a gate insulating layer 103, providing on the surface of the gate insulating layer 103 an island-shaped protrusion layer 104 having dispersed and island-shaped protrusions with a low surface energy, providing on the island-shaped protrusion layer 104 a source electrode 106 and a drain electrode 107 with a distance therebetween, providing thereon an organic semiconductor layer 105 in contact with the island-shaped protrusion layer 104 and both electrodes 106 and 107, and further providing a protective film 108 on the organic semiconductor layer 105.

Abstract: A resin material having low dielectric constant is used as an inter-layer insulating film and its bottom surface is contacted with a silicon oxide film across the whole surface thereof. Thereby, the surface may be flattened and capacity produced between a thin film transistor and an pixel electrode may be reduced. Further, it allows to avoid a problem that impurity ions and moisture infiltrate into the lower surface of the resin material, thus degrading the reliability of whole semiconductor device.

Abstract: Sealing a via using a soventless, low viscosity, high temperature stable polymer or a high solids content polymer solution of low viscosity, where the polymeric material is impregnated within the via at an elevated temperature. A supply chamber is introduced to administer the polymeric material at an elevated temperature, typically at a temperature high enough to liquefy the polymeric material. The polymeric material is introduced through heated supply lines under force from a pump, piston, or a vacuum held within said supply chamber.

Abstract: (1) A metal oxide dispersion for a dye-sensitized solar cell, which contains metal oxide fine particles, a binder composed of a polymer compound having an action to bind to the fine particles and a solvent; (2) a method for producing a photoactive electrode for a dye-sensitized solar cell by coating a dispersion containing the above-mentioned binder and metal oxide fine particles on a sheet-shaped electrode; (3) a photoactive electrode for a dye-sensitized solar cell, obtained by the method, which electrode has metal oxide containing the above-mentioned binder and metal oxide fine particles; and (4) a dye-sensitized solar cell with the above-mentioned photoactive electrode.

Abstract: A circuitized substrate comprising a first layer comprised of a dielectric material including a low moisture absorptive polymer resin in combination with a nodular fluoropolymer web encased within the resin, the resulting dielectric layer formed from this combination not including continuous or semi-continuous fibers as part thereof. The substrate further includes at least one circuitized layer positioned on the dielectric first layer. An electrical assembly and a method of making the substrate are also provided, as is an information handling system (e.g., computer) incorporating the circuitized substrate of the invention as part thereof.

Abstract: Dielectric compositions comprised of porous polymeric matrices are prepared using nitrogen-containing polymers as pore-generating agents. The compositions are useful in the manufacture of electronic devices such as integrated circuit devices and integrated circuit packaging devices. The dielectric compositions are prepared by admixing a polymeric nitrogenous porogen with a high temperature, thermosetting host polymer in a suitable solvent, heating the admixture to cure the polymer and provide a vitrified matrix, and then decomposing the porogen using heat, radiation, or a chemical reagent effective to degrade the porogen. The highly porous dielectric materials so prepared have an exceptionally low dielectric constant on the order of 2.5 or less, preferably less than about 2.0. Integrated circuit devices and integrated circuit packaging devices manufactured so as to contain the dielectric material of the invention are provided as well.

Abstract: In the vicinity of the exposed part 1A of the multiply formed plural wiring conductors 1, of the thicknesses of the insulating cover layer 2 made of a polyimide layer, the thickness (T1) of a part located at about the middle point between the adjacent wiring conductors 1 is made smaller than the thickness (T2) of a part located on wiring conductor 1. Preferably, the difference in the thicknesses of a part located at about the middle point between the adjacent wiring conductors of the insulating cover layer 2 and that of a part located on wiring conductor is made to fall within the range of 1–5 ?m. As a result, the insulating cover layer does not peel off easily.

Abstract: There is disclosed a coating material formulation for layering a plurality of electrodes to provide a substrate for the electrochemical synthesis of organic oligomers. Specifically, there is disclosed a coating layer of from about 0.5 to about 100 microns thick and is composed of a mixture of controlled porosity glass (CPG) particles having an average particle size of from about 0.25 to about 25 microns, and a thickening agent.

Abstract: An electrical interconnect structure on a substrate, which includes: a first low-k dielectric layer; a spin-on low k CMP protective layer that is covalently bonded to the first low-k dielectric layer; and a CVD deposited hardmask/CMP polish stop layer is provided. Electrical vias and lines can be formed in the first low k dielectric layer. The spin-on low k CMP protective layer prevents damage to the low k dielectric which can be created due to non-uniformity in the CMP process from center to edge or in areas of varying metal density. The thickness of the low-k CMP protective layer can be adjusted to accommodate larger variations in the CMP process without significantly impacting the effective dielectric constant of the structure.

Abstract: A stereolithographic method of applying material to form a protective layer on a preformed semiconductor die with a high degree of precision, either in the wafer stage, when attached to a lead frame, or to a singulated, bare die. The method is computerized and may utilize a machine vision feature to provide precise die-specific alignment. A semiconductor die may be provided with a protective structure in the form of at least one layer or segment of dielectric material having a controlled thickness or depth and a very precise boundary. The layer or segment may include precisely sized, shaped and located apertures through which conductive terminals, such as bond pads, on the surface of the die may be accessed. A plurality of discrete protective structures may be formed on corresponding semiconductor devices that are carried by a large-scale semiconductor substrate. Dielectric material may also be employed as a structure to mechanically reinforce the die-to-lead frame attachment.

Abstract: A semiconductor integrated circuit device includes: Si substrate; multilevel interconnect layer formed on the Si substrate; and dielectric layer formed on the multilevel interconnect layer. External-component-connecting wire, ordinary wire, fuse wire, stepper alignment mark, and target mark are formed out of an identical copper film in the uppermost metal layer. External-component-connecting pad electrode, testing-processing alignment mark, and stepper alignment mark are formed out of an identical aluminum alloy film on the dielectric film. In laser-machining the fuse wire, alignment using the target mark formed in the metal layer including the fuse wire reduces alignment errors caused from the machining.

Abstract: The present invention describes a structure having a multilayer stack of thin films, the thin films being a low-dielectric constant material, the thin films having pores, and a method of forming such a structure.

Abstract: A transistor is formed by applying modifier coatings to source and drain contacts and/or to the channel region between those contacts. The modifier coatings are selected to adjust the surface energy pattern in the source/drain/channel region such that semiconductor printing fluid is not drawn away from the channel region. For example, the modifier coatings for the contacts can be selected to have substantially the same surface energy as the modifier coating for the channel region. Semiconductor printing fluid deposited on the channel region therefore settles in place (due to the lack of a surface energy differential) and forms a relatively thick active semiconductor region between the contacts. Alternatively, the modifier coatings can be selected to have lower surface energies than the modifier coating in the channel region, which actually causes semiconductor printing fluid to be drawn towards the channel region.

Abstract: A substrate and an organic electroluminescence device employing the substrate are provided. The substrate has at least one non-continuous photo-resist coating layer formed on at least one surface of a supporting substrate and the non-continuous photo-resist coating has a plurality of continuous portions. The continuous portions may have high surface energy areas and low surface energy areas. A second photo-resist coating layer is used to at least temporarily overlap the continuous portion which corresponds to the high surface energy area in order to form the low surface energy area.

Abstract: An electronic device is provided using wiring comprising aluminum to prevent hillock or whisker from generating, wherein the wiring contains oxygen atoms at a concentration of 8×1018 atoms·cm?3 or less, carbon atoms at a concentration of 5×1018 atoms·cm?3 or less, and nitrogen atoms at a concentration of 7×1017 atoms·cm?3 or less; furthermore, a silicon nitride film is formed on the aluminum gate, and an anodic oxide film is formed on the side planes thereof.

Abstract: A semiconductor device assembly having a lead frame and a semiconductor die configured to be attached to each other is disclosed. An adhesive is applied at room temperature through a stencil to the lead frame. The semiconductor die is urged against the adhesive to effect the attachment between the semiconductor device and the lead frame. The adhesive preferably is from about 75 percent to about 95 percent isobutyl acetal diphenol copolymer and from about 25 percent to about 5 percent, respectively, of titanium oxide.

Abstract: Multi-layer components such as circuit panels are fabricated by connecting conductive features such as traces one two or more superposed substrates using leads extending through an intermediate dielectric layer. The leads can be closely spaced to provide a high density vertical interconnection, and can be selectively connected to provide customization of the structure.

Abstract: In the air or in an inert gas atmosphere, powder raw materials are deposited on a flexible sheet for forming a film, an electrode, and a protective film under pressing a heating roller, and a device can be manufactured by continuous operations in which all the steps are integrated. There is provided a cheap device, by which the manhours for manufacturing a device is reduced, the throughput is improved in comparison with those of a previous device by which a film, an electrode, and a protective film have been manufactured on a crystal substrate in a vacuum.

Abstract: Low-k dielectric materials have desirable insulating characteristics for use in insulating sub micron conductors in semiconductor devices. However, certain physical and material characteristics of the low-k dielectric materials make them difficult to work with. More particularly, the soft, porous, leakage-prone characteristics of low-k materials makes it difficult to accommodate electrical contacts for electrical probing to conductors covered by such materials. The present invention provides methods and structures for facilitating the electrical probing of semiconductor device conductors insulated by overlying low-k layers of dielectric material.

Abstract: Via-shaped copper interconnect lines (2) buried in an interlayer insulating film (8) are connected to gate interconnect lines (1) in the lowermost layer. A copper interconnect line (6) of a shield ring (5) is buried in the interlayer insulating film (8), closer to outside than the copper interconnect lines (2). A silicon nitride film (9) is provided on the via-shaped copper interconnect lines (2), on the copper interconnect line (6) of the shield ring (5), and on the interlayer insulating film (8). Provided on the silicon nitride film (9) is a silicon oxide film (10) which holds therein a fuse line (3) for connecting different ones of copper interconnect lines (2). The silicon oxide film (10) is also provided on the upper surfaces of the fuse line (3) and the aluminum interconnect line (7). A silicon nitride film (11) is provided on the silicon oxide film (10). The silicon nitride film (11) defined over the fuse line (3) is removed, thereby creating an opening (4).

Abstract: A Langmuir-Blodgett film may be utilized as a chemically amplified photoresist layer. Langmuir-Blodgett films have highly vertically oriented structures which may be effective in reducing line edge or line width roughness in chemically amplified photoresists.

Abstract: A planarized conductive material is formed over a substrate including narrow and wide features. The conductive material is formed through a succession of deposition processes. A first deposition process forms a first layer of the conductive material that fills the narrow features and at least partially fills the wide features. A second deposition process forms a second layer of the conductive material within cavities in the first layer. A flexible material can reduce a thickness of the first layer above the substrate while delivering a solution to the cavities to form the second layer therein. The flexible material can be a porous membrane attached to a pressurizable reservoir filled with the solution. The flexible material can also be a poromeric material wetted with the solution.

Abstract: The semiconductor device comprises an insulating film 114 formed mainly of a film of polyallyl ether resin; an interconnection structure 116 buried in the insulating film 114, and having a via portion buried in a groove-shaped via hole and an interconnection portion formed on the via portion and having an eave-shaped portion horizontally extended beyond the via portion; an insulating film 118 formed on the insulating film 114 with the interconnection structure 116 buried in and formed mainly of a film of organosilicate glass; and an interconnection structure 120 buried in the insulating film 118 and connected to the interconnection structure 116. Thus, the stresses to be exerted to the insulating films are decreased, the generation of cracks and peelings generated in the interfaces between the insulating films and in the insulating films due to the stresses generated at the ends of the interconnection structures can be effective prevented.

Abstract: A typical integrated circuit interconnects millions of microscopic transistors and resistors with aluminum wires buried in silicon-dioxide insulation. Yet, aluminum wires and silicon-dioxide insulation are a less attractive combination than gold, silver, or copper wires combined with polymer-based insulation, which promise both lower electrical resistance and capacitance and thus faster, more efficient circuits. Unfortunately, conventional etch-based techniques are ineffective with gold, silver, or copper, and conventional polymer formation promote reactions with metals that undermine the insulative properties of polymer-based insulations. Accordingly, the inventor devised methods which use a liftoff procedure to avoid etching problems and a non-acid-polymeric precursor and non-oxidizing cure procedure to preserve the insulative properties of the polymeric insulator. The resulting interconnective structures facilitate integrated circuits with better speed and efficiency.

Abstract: A composite containing nano magnetic particles is provided. The composite includes nano magnetic particles in a dielectric matrix. The matrix is made of an inorganic material such as silica, alumina, or hydrosilsesquioxane, or an organic material such as polyimide, polymethyl methacrylate, or methyl silsesquioxane. The nano magnetic particles consist of Fe2O3, chromium oxide, europium oxide, NiZn-ferrite, MnZn-ferrite, yttrium-iron garnet, or indium In.

Abstract: An uppermost interlayer isolation film is provided on a semiconductor substrate. An uppermost wire is provided on the uppermost interlayer isolation film. A silicon oxide film is provided to cover the upper surface and the side wall of the uppermost wire. A nitride film is provided on the uppermost interlayer isolation film to cover the uppermost wire through the silicon oxide film. A polyimide film is provided on the nitride film. A portion of the uppermost interlayer isolation film other than a portion located under the uppermost wire is downwardly scooped. The nitride film covers the scooped portion of the uppermost interlayer isolation film. According to the present invention, a semiconductor device improved to be capable of improving coverage of a silicon nitride passivation film is obtained.

Abstract: There are included a semiconductor substrate provided with a desirable element region, an electrode pad formed to come in contact with a surface of the semiconductor substrate or a wiring layer provided on the surface of the semiconductor substrate, a bonding pad formed on a surface of the electrode pad through an intermediate layer, and a resin insulating film for covering a peripheral edge of the bonding pad such that an interface of the bonding pad and the intermediate layer is not exposed to a side wall.

Abstract: An organic light emitting device display may include transverse row and column lines. In a passively driven OLED display, a fuse may be positioned between the OLED material and the row electrode. When a short occurs, the single pixel may be separated from the circuit by the fuse, avoiding the possibility that an entire row of pixels may be adversely affected by the short associated with one single pixel along a row.

Abstract: A resin material having low dielectric constant is used as an inter-layer insulating film and its bottom surface is contacted with a silicon oxide film across the whole surface thereof. Thereby, the surface may be flattened and capacity produced between a thin film transistor and an pixel electrode may be reduced. Further, it allows to avoid a problem that impurity ions and moisture infiltrate into the lower surface of the resin material, thus degrading the reliability of whole semiconductor device.

Abstract: A semiconductor device includes a semiconductor substrate having a center area where an IC is formed and a peripheral area surrounding the center area, a first wiring pattern formed on the substrate in the center area, a second wiring pattern formed in the peripheral area wherein the second wiring pattern encompasses the center area, a first insulating layer formed over the center and peripheral areas, and a second insulating layer formed on the first insulating layer which is formed on the semiconductor substrate wherein the second insulating layer is not formed over the second wiring pattern.

Abstract: There are included a semiconductor substrate provided with a desirable element region, an electrode pad formed to come in contact with a surface of the semiconductor substrate or a wiring layer provided on the surface of the semiconductor substrate, a bonding pad formed on a surface of the electrode pad through an intermediate layer, and a resin insulating film for covering a peripheral edge of the bonding pad such that an interface of the bonding pad and the intermediate layer is not exposed to a side wall.

Abstract: A method for producing a semiconductor component with the following steps. A semiconductor chip is provided having electrical contacts in a contact making region. A housing including a rear plate and a side area is provided and surrounds the semiconductor chip. A first compliant buffer layer is applied on a rear plate. The semiconductor chip is applied to the first compliant buffer layer, and a second compliant buffer layer is applied to and around the semiconductor chip except in the contact making region. A contact passage plate is provided with an opening over the contact areas and the contact passage plate is fixed to the second compliant buffer layer.

Abstract: A semiconductor device wherein a coating film which is made of a polyimide resin or a polyimide isoindoloquinazolinedione resin and which is at least 10 &mgr;m thick is disposed on at least an active region of a semiconductor substrate, and the resultant semiconductor substrate is encapsulated in a ceramic package. The semiconductor device has troubles relieved conspicuously, the troubles being ascribable to alpha-rays which come flying from impurities contained in the material of the package.

Abstract: To provide means for forming projected and recessed portions for preventing mirror face reflection of a reflecting electrode without increasing steps, in a method of fabricating a reflection type liquid crystal display device, to achieve light scattering performance by providing recessed and projected portions at a surface of a pixel electrode, projected portions 701 and 702 are formed by the same photomask as that in forming TFT to thereby form projected and recessed portions at a surface of a pixel electrode 169.

Abstract: Porous insulation films 28, 40, 50 are formed of an insulation forming material including a silicon compound having a skeleton containing C—C bonds, a pore forming compound which is decomposed or evaporated by a heat treatment, and a solvent which dissolves the silicon compound with the pore forming compound, whereby the porous insulation film can have good mechanical strength and low dielectric constant.

Abstract: A method and structure for protecting a flowable oxide insulator in a semiconductor by oxidizing sidewalls of the FOX insulator, optionally nitridizing the oxidized FOX sidewalls, and then covering all surfaces of a trough or plurality of troughs in the FOX insulator, including the sidewalls, with a conductive secondary protective layer. In a multiple layer damascene structure, the surface of the FOX insulator is also oxidized, an additional oxide layer is deposited thereon, and a nitride layer deposited on the oxide layer. Then steps are repeated to obtain a comparable damascene structure. The materials can vary and each damascene layer may be either a single damascene or a dual damascene layer.

Abstract: A spin-on cap useful as a post-CMP cap for Cu interconnect structures is provided. The inventive spin-on cap includes a low-k dielectric (on the order of 3.5 or less) and at least one additive. The at least one additive employed in the present invention is capable of binding Cu ions, and is soluble in the spun-on low-k dielectric. The spin-on cap of the present invention may further include a spun-on low-k (on the order of 3.5 or less) reactive-ion etch (RIE) stop layer. Spin-on caps containing a bilayer of low-dielectric plus at least additive and low-k RIE stop layer are preferred. It is noted that the inventive spin-on cap of the present invention does not significantly increase the effective dielectric constant of the interconnect structure and does not add additional cost to the fabrication of the interconnect structure since a single deposition tool, i.e., spin coating tool, is employed. Moreover, because of the presence of the additive in the spin-on cap, Cu migration is substantially minimized.

Abstract: Methods for forming porous insulative materials for use in forming dielectric structures of semiconductor devices are disclosed. Each insulative material may include a first, substantially nonporous state and a second, porous state. When in the first state, the insulative materials may be processed or support layers or structures which are being processed. When in the second state, the insulative materials have a reduced dielectric constant and, thus, increased electrical insulation properties. Semiconductor device structures including layers or other features formed from one of the insulative materials are also disclosed. Methods for forming the insulative material and for causing the insulative material to become porous are also disclosed.

Abstract: A novel dielectric composition is provided that is useful in the manufacture of electronic devices such as integrated circuit devices and integrated circuit packaging devices. The dielectric composition is prepared by crosslinking a thermally decomposable porogen to a host polymer via a coupling agent, followed by heating to a temperature suitable to decompose the porogen. The porous materials that result have dielectric constants of less than 2.4.

Abstract: A passivation layer is deposited onto the surface of a substrate followed by deposition of a polymer layer, through the application of a plasma enhanced chemical vapor deposition process, in which the substrate is placed on a chuck within a reaction chamber and fluorocarbon gas is introduced into the reaction chamber under the influence of at least one plasma source. The fluorocarbon gas can be a CFX gas. The at least one plasma source can include a first plasma source that ionizes the fluorocarbon gas by applying RF plasma energy, and a second plasma source that applies a near-zero self-bias to the substrate at an RF frequency during deposition of the passivation layer and a greater bias during deposition of the polymer layer. The passivation layer is deposited prior to the polymer layer to protect the surface of the substrate from damage during the deposition of the polymer layer.

Abstract: Disclosed is a conductive fuse for a semiconductor device, comprising: a pair of contact portions integrally connected to a fusible portion by connecting portions; the contact portions thicker than the connecting portions and the connecting portions thicker than the fusible portion; a first dielectric under the connecting portions and the fusible portion and extending between the pair of contact portions; and a second dielectric between the first dielectric and the fusible portion, the second dielectric extending between the connecting portions and defining the length of the fusible portion.

Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. A cerium-conductor interconnect cap is disposed over the conductor core with a capping layer over the dielectric layer and the cerium-conductor interconnect cap.

Abstract: A semiconductor device including a substrate, a mesa post overlying the substrate and having a substantially cylindrical shape, a resin member surrounding the mesa post and a stress moderating member received in the mesa post for moderating stress between the mesa post and the resin member. The stress applied to the mesa post is reduced because the entire volume of the resin member is divided by the stress moderating member and each of the divided resin members reduces the stress.

Abstract: An air gap semiconductor structure and corresponding method of manufacture. The method includes forming a sacrificial polymer film over a substrate having metal lines thereon. A portion of the sacrificial polymer film is subsequently removed to form first spacers. A micro-porous structure layer is formed over the substrate and the metal lines and between the first spacers. A portion of the micro-porous structure layer is removed to form second spacers. The first spacers are removed by thermal dissociation to form air gaps. A dielectric layer is formed over the substrate and the metal lines and between the second spacers.

Abstract: A metal interconnect structure and method of making the same implants ions of an alloy elements into a copper line through a via. Then ion implantation of the alloy elements in the copper line through the via provides improved electromigration properties at the copper line at a critical electromigration failure site, without attempting to provide alloy elements throughout the entire copper line.

Abstract: A typical integrated circuit interconnects millions of microscopic transistors and resistors with aluminum wires buried in silicon-dioxide insulation. Yet, aluminum wires and silicon-dioxide insulation are less attractive than copper wires and polymer-based insulation, which promise both lower electrical resistance and capacitance and thus faster, more efficient circuits. Unfortunately, current techniques cannot realize the promise because copper reacts with the polymer-based insulation to form copper dioxide within the polymer, reducing effectiveness of the copper-polymer combination. Accordingly, the inventor devised a method which uses a non-acid-precursor to form a polymeric layer and then cures, or bakes, it in a non-oxidizing atmosphere, thereby making the layer resistant to copper-dioxidizing reactions. Afterward, the method applies a copper-adhesion material, such as zirconium, to the layer to promote adhesion with a subsequent copper layer.

Abstract: In the present invention, provided are a semiconductor device having a semiconductor-element-mounting substrate on which a semiconductor element has been mounted via an adhesive having an exothermic-reaction curing start temperature of 130° C. or below as measured with a differential scanning calorimeter at a heating rate of 10° C./minute, and a process for its fabrication.

Abstract: A method for forming a thin film includes the steps of: supplying a deposition material in the form of a liquid onto a heated surface; heating and vaporizing the deposition material on the heated surface while the deposition material is undergoing movement; and depositing the deposition material onto a deposition surface. The deposition material is supplied onto a position of the heated surface where the vaporized deposition material does not reach the deposition surface.

Abstract: The specification describes techniques for applying under bump metallization (UBM) for solder bump interconnections on IC chips with Al bonding sites. The UBM of the invention comprises a copper layer applied directly to the aluminum bonding sites. Reliable bonds are obtained if the Al surface is a nascent surface. Such a surface can be provided by back sputtering an aluminum bonding site, or by a freshly sputtered aluminum layer. The copper layer is deposited on the nascent aluminum surface in e.g. a cluster tool without breaking vacuum. The UBM can be patterned using subtractive techniques.