Abstract: An integrated circuit is provided. The integrated circuit includes a substrate and at least one dielectric layer and a metal layer formed upon the substrate. The at least one dielectric layer includes a terminal dielectric layer. The integrated circuit further includes a planar passivating layer formed upon the terminal dielectric layer.

Abstract: The present invention provides polymeric materials that can be used as a moisture/ion barrier layer for inhibiting the penetration of moisture and/or ions for coming into contact with the metal wiring found in chip level interconnects. The present invention also provides a means to protect the chip backside from being contaminated by metal atoms or metal ions which are capable of forming mobile silicides, which can migrate to the active sites of the semiconductor and destroy them. The present invention further provides methods of forming such polymeric barrier layers on at least one surface of an interconnect structure.

Abstract: A dual damascene structure includes a semiconductor substrate, a metal-oxide-semiconductor (MOS) transistor formed on the substrate and a metal layer. The metal layer is electrically connected to the conducting regions of the MOS transistor through interconnect. The metal layer further includes first metal spacing regions and second metal spacing regions, wherein the width of a first metal spacing region is about 1 to 10 times of the linewidth of the device, and the width of a second spacing region is about 0.8 to 1.2 times of the linewidth of the device. The first metal spacing regions includes a high-permittivity dielectric for a better thermal transferring rate, and the second spacing regions includes a low-permittivity dielectric for a shorter resistance-capacitance delay.

Abstract: A surface-protecting film is formed on the surface of the semiconductor element of a resin-sealed semiconductor device to prevent the peeling and cracking of the sealing member used in said device, by coating on said surface a polyimide precursor composition containing a polyimide precursor having a recurring unit constitution represented by the following general formula (1) and heat-curing the coated polyimide precursor composition: ##STR1## wherein R.sup.1 is a trivalent or tetravalent aromatic group; R.sup.2 and R.sup.3 are each a tetravalent organic group having 4 or more carbon atoms; R.sup.4 is a bivalent organic group having 4 or more carbon atoms; X is a bivalent organic group containing at least one member selected from the group consisting of oxygen and nitrogen: Y is a monovalent organic group having 15 or less carbon atoms; n=5-100 and m=0-95 with a proviso that n+m=100; and p is 1 or 2).

Abstract: A semiconductor device assembly having a support such as a lead frame paddle comprises a coating thereon to reduce or eliminate the flow of die attach adhesive from under the die and over bond sites or encapsulation regions. Thus undesirable effects resulting from this flow of adhesive, such as wire bonding problems and encapsulation problems, are reduced. A method for forming the assembly is also described.

Abstract: A composite bump structure and methods of forming the composite bump structure. The composite bump structure comprises a polymer body of relatively low Young's Modulus compared to metals covered by a conductive metal coating formed at the input/output pads of an integrated circuit element or substrate. The composite bump is formed using material deposition, lithography, and etching techniques. A layer of soldering metal can be formed on the composite bumps if this is desired for subsequent processing. A base metal pad covering the integrated circuit element input/output pad can be used to provide added flexibility in location of the composite bump. The composite bump can be formed directly on the input/output pad or on the base metal pad.

Abstract: An integrated circuit (IC) is provided. The IC includes a silicon substrate and a dielectric layer formed upon the silicon substrate. The IC further includes a terminal metal layer (TML) formed upon the dielectric layer. The dielectric layer and the TML form a die active area. The TML has formed therein a plurality of spaced locking structures. The plurality of space locking structures are electrically isolated therebetween. Each locking structure is formed outside the die active area. The IC further includes a passivation layer adhering to the locking structures.

Abstract: A structure and method of fabrication of a semiconductor integrated circuit is described. A first patterned electrically conductive layer contains a low dielectric constant first insulating material such as organic polymer within the trenches of the pattern. A second insulating material such as a silicon dioxide or other insulating material having a greater mechanical strength and thermal conductivity and a higher dielectric constant than the first insulating material is formed over the first patterned electrically conductive layer. Vias within the second insulating material filled with electrically conductive plugs and a second patterned electrically conductive layer may be formed on the second insulating material. The structure can be repeated as many times as needed to form a completed integrated circuit.

Abstract: A semiconductor processing method is provided for making contact openings. It includes depositing several insulative layers and performing an anisotropic etch. One layer is a conformal oxide covering the contact area and adjacent structures. A second layer is a breadloafed oxide deposited over the contact area and adjacent structures. A third layer is a doped oxide deposited over the two lower layers. The anisotropic etch is performed through the oxide layers to the contact area located on a lower substrate. The etch is selectively more rapid in the third oxide than in the two other oxides. The breadloafed oxide provides additional protection and reduces the risk of etch-through to conductive structures adjacent the contact area. An alternate embodiment replaces the two lowest oxide layers by a breadloafed nitride layer. In this embodiment, the anisotropic etch is selectively more rapid in oxides than in nitrides.

Abstract: A microstrip line device is disclosed of the type which typically includes a strip conductor disposed on the top of a substrate. The device further includes a layer of dielectric material disposed between the strip conductor and the substrate for reducing the dissipation loss in these devices. In order to accomplish this, the dielectric layer has a dielectric constant which is less than the dielectric constant of the substrate.

Abstract: A method for manufacturing a liquid crystal display device includes the steps of forming a switching element having an electrode on substrate, forming an organic layer over the substrate and the switching element, forming an ion doped layer by doping ions selected from a group consisting of Si, P, Ge, B, As, Ba, Ti, Tb, and Bi into the organic layer, forming a contact hole in the ion doped layer exposing a portion of the electrode, and forming an inorganic layer connected to the electrode through the contact hole on the ion doped layer.

Abstract: A semiconductor device assembly has a lead frame and a semiconductor device configured to be attached to each other. An adhesive is applied at room temperature through a stencil to the lead frame. The semiconductor device is urged against the adhesive to effect the attachment between the semiconductor device and the lead frame. The adhesive preferably is from about 75 percent to about 95 percent isobutyl acetal diphenol copolymer and from about 25 percent to about 5 percent, respectively, of titanium oxide.

Abstract: A method of forming a resin film pattern, comprising the steps of (A) producing a resin film layer soluble in an organic solvent, on a substrate such as silicon wafer, even engineering plastics being usable as a resin of the resin film layer; (B) forming a resist image of desired pattern on the organic solvent-soluble resin film layer; (C) etching each of those parts of the organic solvent-soluble resin film layer which are not covered with the resist image, using the organic solvent; and (D) removing the resist image from the resulting, organic solvent-soluble resin film layer using a resist image remover which contains 0.01-10.0 parts-by-weight of arylsulfonic acid with respect to 100 parts-by-weight of solvent having a solubility parameter of 5.0-11.0. The step (D) may well be followed by the step (E) of processing the substrate which includes the resin film layer, with alcohol.

Abstract: A resin material having a small relative dielectric constant is used as a layer insulation film 114. The resin material has a flat surface. A black matrix or masking film for thin film transistors is formed thereon using a metal material. Such a configuration prevents the problem of a capacity generated between the masking film and a thin film transistor.

Abstract: A multi-layered wiring structure includes a lower wiring having an upper surface, a first inter-level insulating layer having a first flat upper surface substantially coplanar with the upper surface of the lower conductive wiring and a recess contiguous to the first flat upper surface, a spin-on-glass layer filling the recess and having a second flat upper surface substantially coplanar with the first flat upper surface, a second inter-level insulating layer covering the first and second flat surfaces and the upper surface of the lower conductive wiring and an upper conductive wiring extending on the second inter-level insulating layer and passing through a contact hole of the second inter-level insulating layer so as to be held in contact with the lower conductive wiring, and the first and second flat upper surfaces are created through an etch-back using gaseous etchant equally etching the first inter-level insulating layer and the spin-on-glass layer, thereby creating smooth surface under the second inter-l

Abstract: An interconnect platform and its method of fabrication is presented. The interconnect platform of the present invention includes a metal conductor, a dielectric layer, and a buffer layer separating at least one interface between the conductor and the dielectric layer when the buffer has a lower modulus of elasticity than the dielectric layer.

Abstract: On manufacturing a semiconductor device, preparation is made of an organic layer (101) of a resin which has a relative dielectric constant between 1.8 and 3.5, both inclusive, and which is selected from the group consisting of a polyimide resin and a fluororesin. The organic layer has a slit. A first metal (105) is buried in the slit. A silicon oxide layer (106) containing fluorine is formed on the organic layer so that the silicon oxide layer has a hole on the first metal. A second metal (107) is buried in the hole. Preferably, an additional organic layer (101') of the resin is formed on the silicon oxide layer so that the additional organic layer has an additional slit on the second metal. In this case, a first additional metal (105') is buried in the additional slit. In addition, an additional silicon oxide layer (106') containing fluorine may be formed on the additional organic layer so that the additional silicon oxide layer has an additional hole on the first additional metal.

Abstract: A wafer edge seal ring structure is disclosed to provide reduced particulate contaminant generation during wafer processing of high density integrated circuits. The structure is formed by delimiting the deposition of layers at the peripheral edges of wafers. It is shown that as each layer is deposited and then essentially trimmed back from the edge of the wafer through a judicious use of mask and etching, and/or edge-bead rinsing (EBR) and later sealed by wafer edge exposure (WEE), the otherwise present abnormal growth of layers are prevented from building up into protrusions at the edge of wafer that later peel or break up to form particulate matter and fine dust. The method, which is also disclosed, teaches how each layer is recessed at appropriate distances from the wafer edge and how the whole ring structure is sealed against attacking particles.

Abstract: A low RC delay interconnection pattern is formed with a low resistivity metal, such as copper, and a low dielectric constant material, such as organic polymers. An intermediate bonding layer is formed between the low resistivity metal and low dielectric constant material employing an adhesion promoter, such as a silane-based adhesion promoter. The adhesion promoter can be applied between the metal and dielectric layers or incorporated in the dielectric layer.

Abstract: The invention relates to a semiconductor device with a substrate, with at least one isolation layer with at least one window, with a passivation layer scheme lying on the isolation layer and a metallization lying on the passivation layer scheme, the latter comprising at least two dielectric layers of which the first dielectric layer covers the isolation layer with its edges as well as the substrate in an outer edge zone of the window, and of which the second dielectric layer covers the first dielectric layer also over the edge of the isolation layer and in a portion of the outer region of the window.

Abstract: A connection component for a microelectronic device such as a semiconductor chip incorporates a dielectric layer and leads extending across a surface of the dielectric layer. Each lead has one end permanently fastened to the dielectric layer and another end releasably bonded to the dielectric layer. The releasable end is held in place by a bond having a relatively low peel strength, desirably less than about 0.35.times.10.sup.6 dynes/cm.

Abstract: A low RC delay interconnection pattern is formed with a low resistivity metal, such as copper, and a low dielectric constant material, such as organic polymers. An intermediate bonding layer is formed between the low resistivity metal and low dielectric constant material employing an adhesion promoter, such as a silane-based adhesion promoter. The adhesion promoter can be applied between the metal and dielectric layers or incorporated in the dielectric layer.

Abstract: A microstrip line device is disclosed of the type which typically includes a strip conductor disposed on the top of a substrate. The device further includes a layer of dielectric material disposed between the strip conductor and the substrate for reducing the dissipation loss in these devices. In order to accomplish this, the dielectric layer has a dielectric constant which is less than the dielectric constant of the substrate.

Abstract: A method of forming low dielectric insulation between those pairs of conductive lines, of a level of interconnection for integrated circuits, having a gap of about 0.5 microns or less by depositing a nonconformal source with a poor step function for the insulating material, such as silane (SiH.sub.4) as the silicon (Si) source for silicon dioxide (SiO.sub.2), so as to create, in the gap, a large void whose dielectric constant is slightly greater than 1. After all of the conductive lines have received a deposit of conformal insulating material and a flowable insulating material, the composite insulating materials are removed, preferably by etching, from those pairs of conductive lines with a gap of about 0.5 microns or less. Now, a nonconformal insulating material with a poor step function is deposited and creates a large void in the open gaps of 0.5 microns or less. After creating the void, the deposition continues and is planarized at the desired composite thickness of insulation.

Abstract: An electronic chip component includes an electrode formed on a wafer, a passivation film formed on the wafer, and an organic protective film covering an entire surface of exposed portions of the electrode and the passivation film. A package for packing the component includes a carrier tape having therethrough a space for receiving the component with one end or side of the space opened, and a cover tape for closing the open end of the space after the component is stored in the space. A method for packing the component includes the steps of storing the component in the space of the carrier tape with one end of the space opened, and closing the open end of the space with the cover tape.

Abstract: A semiconductor device using an organic resin substrate, wherein an organic resin coating is provided on the surface of said organic resin substrate and a method for forming the same.

Abstract: A multilayered interconnection substrate which prevents contact failure from occurring and a process for fabricating the same, said multilayered interconnection substrate comprising a first interconnection layer formed on a substrate, at least two layers of insulation films differing in composition from each other and being formed on said first interconnection layer, provided that the insulation layers comprise at least one contact hole formed in such a manner to expose the selected portion of said first interconnection layer, a resin wall which buries the stepped portions formed on the inner peripheral portion of said contact hole, and a second interconnection layer formed inside said contact hole along said resin wall and being electrically connected to the first interconnection layer exposed at the bottom portion of the contact hole.

Abstract: In a photosensitive chip suitable for full-color imaging, separate photosites on the chip correspond to different primary colors in an original image. Each primary-color photosite is filtered with a polyimide doped to a particular primary color. The red-filtering layer and the blue-filtering layer are left on the non-photosensitive portions of the main surface of the chip, and together serve as a non-reflective area which prevents stray reflections from the chip. The chip is further provided with a base layer of infrared-filtering polyimide.

Abstract: A bonding pad structure for use with compliant dielectric materials and a method for wire bonding is described in which a rigid layer is formed between the bonding pad and the compliant dielectric layer. The rigid layer increases the stiffness of the bonding structure such that an effective bond may be achieved by conventional ultrasonic and thermosonic bonding methods.

Abstract: A process for producing a plurality of metallized vias in a polyimide dielectric is disclosed. The process includes depositing a polyimide precursor, then a silane and finally a metal, after patterning the polyimide and silane. The sandwich is heated to completely imidize the polyimide, crosslink the silane and anneal the metal simultaneously. The excess metal overlying the polyimide between the vias is removed by chemical mechanical polishing using the crosslinked silane as a polish stop.

Abstract: This invention provides an improved porous structure for semiconductor devices and a process for making the same. This process may be applied to an existing porous structure 28, which may be deposited, for sample, between patterned conductors 24. The process may include baking the structure in a reducing atmosphere, preferably a forming gas, to dehydroxylate the pore surfaces. The process may include baking the structure in a halogen-containing atmosphere to bond halogens to the pore surfaces. It has been found that a porous structure treated in such a manner generally exhibits improved dielectric properties relative to an untreated sample.

Abstract: In a nonvolatile memory apparatus having a special information memory cell, which keeps special information undesirable to be erased at the time of illumination of an ultraviolet ray, in addition to an ultraviolet-erasable memory cell mainframe, an ultraviolet impermeability resin film having an electrically insulating characteristic is provided on the special information memory cell so as to guard the information of the portion, covered by the ultraviolet impermeability resin film, at the time of the illumination of an ultraviolet ray. Since the ultraviolet impermeability resin film has an electrically insulating characteristic, it is possible to widely cover the special information memory cell to prevent the ultraviolet ray from passing around the ultraviolet impermeability resin film without a restriction on a wiring pattern formation, thereby improving the reliability.

Abstract: A hybrid semiconductor device which comprises a semiconductor substrate having electrical devices therein with a plurality of spaced apart relatively rigid standoffs of electrically insulating material disposed over the substrate. Each of the standoffs has a substantially planar exposed surface remote from the substrate. A first layer of electrically insulating material more resilient than the standoffs is disposed over the substrate and between the standoffs and has an upper surface coplanar with the planar exposed surfaces of the standoffs. A semiconductor superstrate is secured to the first layer of electrically insulating material, the superstrate containing electrical devices. A connection connects the electrical devices contained in the superstrate to the electrical devices in the substrate.

Abstract: A photosensor includes a substrate; a photoconductive layer formed on the substrate; a pair of electrodes mounted on and electrically connected to the photoconductive layer; a light reception portion formed between the electrodes; and a protective layer formed on the light reception portion; wherein an organic silicon film with a small content of metal ion is formed at least at the uppermost portion of the protective layer.

Abstract: A semiconductor device has a conductive interconnection layer formed on a semiconductor substrate covered with a protection insulation film. A pad electrode opening is provided in the protection insulation film so that the surface of the conductive interconnection layer is exposed in the region which becomes the pad electrode. The conductive interconnection layer is electrically connected to an external terminal by a bonding wire. At least the surface of the protection insulation film in the proximity of the pad electrode opening and the inner peripheral side face of the pad electrode opening are covered with an elastic insulation film. The pad electrode opening is covered with the bonding wire. Since the conductive interconnection layer is not exposed at the pad electrode opening according to this structure, the phenomenon of moisture intruding into the pad electrode opening to corrode the conductive interconnection layer is prevented to improve reliability.

Abstract: A semiconductor device wherein a coating film which is made of a polyimide resin or a polyimide isoindoloquinazolinedione resin and which is at least 10 .mu.m thick is disposed on at least an active region of a semiconductor substrate, and the resultant semiconductor substrate is encapsulated in a ceramic package. The semiconductor device has troubles relieved conspicuously, the troubles being ascribable to alpha-rays which come flying from impurities contained in the material of the package.

Abstract: An electrically blowable fuse structure usable with organic insulators in microelectronic parts is provided. The fuse structure is made of a first heat resistant member, a fusing element and a second heat resistant member. The heat resistant members are in substantial contact with the fuse and thermally insulate the fuse from the organic insulator. The ends of each fuse are electrically connected to a pair conductors.

Abstract: Positive working polyamic acid photoresist compositions are disclosed having improved high resolution upon image development and exhibiting stable photosensitivity and superior dielectric performance. The compositions comprise polyamic acid condensation products of an aromatic dianhydride and an aromatic di-primary amine wherein a percentage of the diamine comprises special dissolution inhibiting monomers. The compositions may be further improved by the presence of particular supplemental additives.

Abstract: A semiconductor structure according to the present invention includes a diffusion preventing layer for preventing a diffusion of a brazing metal layer, for instance, Au/In. The structure is interconnected to another structure by brazing.

Abstract: The present invention relates to a circuit assembly comprising the polyimide poly(3,4'-oxydiphenylene pyromellitimide).