Abstract: A new method of creating a relatively thick layer of PE silicon nitride. A conventional method of creating a layer of silicon nitride applies a one-step process for the creation thereof. Film stress increases as the thickness of the created layer of PE silicon nitride increases. A new method is provided for the creation of a crack-resistant layer of PE silicon nitride by providing a multi-step process. The main processing step comprises the creation of a relatively thick, compressive film of PE silicon nitride, over the surface of this relatively thick layer of PE silicon nitride is created a relatively thin (between about 150 and 500 Angstrom) layer of tensile stress PE silicon nitride. This process can be repeated to create a layer of PE silicon nitride of increasing thickness.

Abstract: The present invention provides a technique to reduce a stress of thick spin-on dielectric layer by forming a sandwich dielectric structure, wherein a first dielectric layer is formed on a substrate by spin coating, a liquid phase deposited (LPD) silica layer is formed the first dielectric layer, and a second dielectric layer is formed on the LPD silica layer by spin coating. The LPD silica layer can be further subjected to a nitrogen plasma treatment to enhance its thermal stability and anti-water penetration ability.

Abstract: A method of manufacturing a semiconductor device comprises preparing a substrate to be treated, and forming an insulation film above the substrate, which includes applying an insulation film raw material above the substrate, the insulation film raw material including a substance or a precursor of the substance, the insulation film comprising the substance, curing the insulation film raw material by irradiating an electron beam on the substrate while heating the substrate in a reactor chamber, changing at least one of parameter selected from the group consisting of pressure in the reactor chamber, temperature of the substrate, type of gas having the substrate exposed thereto, flow rate of gas introduced into the reactor chamber, position of the substrate, and quantity of electrons incident to the substrate per unit time when the electron beam is being irradiated on the substrate.

Abstract: A method of manufacturing an insulating layer that ensures reproducibility across like manufacturing apparatus. The insulating layer is formed on the substrate by (a) flowing an oxidizing gas at an oxidizing gas flow rate, (b) flowing a first carrier gas at a first carrier gas flow rate while carrying a first impurity including boron flowing at a first impurity flow rate, (c) flowing a second carrier gas at a second carrier gas flow rate while carrying a second impurity including phosphorus flowing at a second impurity flow rate, and (d) flowing a silicon source material at a silicon source flow rate. The second carrier gas flow rate is greater than the first carrier gas flow rate.

Abstract: Supports (3) are formed to be arrayed on a support base (1), a sacrifice layer (15) is formed of a resin material, and the sacrifice layer (15) is planarized so as to expose the top of the respective supports (3), thereby forming a thin-film substrate (5) on top of the sacrifice layer (15) as planarized, and the supports (3). The sacrifice layer (15) is removed by plasma selective etching thereof through the intermediary of the thin-film substrate, and thereby a large-area thin-film substrate (5) floatingly spaced by a space (7) away from the support base (1) can be fabricated.

Abstract: A semiconductor structure includes a substrate, a dielectric layer disposed on the substrate, a layer of undoped silicate glass disposed on the dielectric layer, a layer of borophosphorous silicate glass on the layer of undoped silicate glass, and a planar dielectric layer disposed on the layer of borophosphorous silicate glass, the layers of undoped silicate glass, borophosphorous silicate glass, and planar dielectric together forming a pre-metal dielectric stack. The planar dielectric may include plasma-enhanced tetraethyl orthosilicate.

Abstract: A method for controlling silver doping of a chalcogenide glass in a resistance variable memory element is disclosed herein. The method includes forming a thin metal containing layer having a thickness of less than about 250 Angstroms over a second chalcogenide glass layer, formed over a first metal containing layer, formed over a first chalcogenide glass layer. The thin metal containing layer preferably is a silver layer. An electrode may be formed over the thin silver layer. The electrode preferably does not contain silver.

Abstract: A device for the detection of electromagnetic radiation, wherein the device has (i) a photoactive layer of a semiconductor having a band gap of greater than 2.5 eV, (ii) a dye applied to the semiconductor, and (iii) a charge transport layer comprising a hole conductor material, where the hole conductor material is preferably solid and amorphous.

Abstract: A semiconductor device of the present invention has (1) an active element provided on a semiconductor substrate, (2) an interlayer insulating film formed so as to cover the active element, (3) a pad metal for an electrode pad which is provided on the interlayer insulating film, (4) a barrier metal layer which is provided on the active element with the interlayer insulating film therebetween, so that the pad metal is i formed on the barrier metal layer, and (5) an insulating layer having high adherence to the barrier metal layer, the insulating layer being provided between the interlayer insulating film and the barrier metal layer. With this arrangement, the adherence between the barrier metal layer, the insulating film and the interlayer insulating film is surely improved, even in the case where an external force is applied to the electrode pad upon bonding or after bonding, the barrier metal layer hardly comes off the part thereunder.

Abstract: A semiconductor device comprising organic semiconductor material (14) has one or more barrier layers (16) disposed at least partially thereabout to protect the organic semiconductor material (14) from environment-driven changes that typically lead to inoperability of a corresponding device. If desired, the barrier layer can be comprised of partially permeable material that allows some substances therethrough to thereby effect disabling of the encapsulated organic semiconductor device after a substantially predetermined period of time. Getterers (141) may also be used to protect, at least for a period of time, such organic semiconductor material.

Abstract: A miniature semiconductor apparatus is outstanding in reflow resistance, temperature cycle property, and PCT resistance corresponding to high density packing, high densification, and speeding up of processing. The semiconductor apparatus has at least one stress cushioning layer on a semiconductor element with an electrode pad formed, having a conductor on the stress cushioning layer, having a conductor for conducting the electrode pad and conductor via a through hole passing through the stress cushioning layer between the electrode pad and the conductor, having an external electrode on the conductor, and having a stress cushioning layer in an area other than the area where the external electrode exists and a conductor protection layer on the conductor, wherein the stress cushioning layer includes crosslinking acrylonitrile-butadiene rubber having an epoxy resin which is solid at 25° C. and a carboxyl group.

Abstract: A fully hermetically sealed semiconductor chip and its method of manufacture. The semiconductor chip of the present invention is fully hermetically sealed on both sides and the edges thereof through the use of suitable coatings applied thereto, such as glass, to prevent an environmental attack of the semiconductor chip. The fully hermetically sealed semiconductor chip of the present invention does not require the use of a separate package for the hermetic sealing of the chip, thereby reducing the size of such a chip. The method of the manufacture of the semiconductor chip of the present invention provides a simple process for the fully hermetic sealing of both sides and the edges of the semiconductor chip without the use of a separate package.

Abstract: A contact to a semiconductor substrate including a contact opening extending through an insulating layer to a doped active region of the semiconductor substrate. The contact opening can have a relatively high aspect ratio of 2:1 or greater. The contact further includes a refractory metal germanosilicide region at the bottom of the contact opening, a refractory metal germanide layer at the sidewalls of the contact opening, and an overlying refractory metal nitride layer. The refractory metals of the invention include at least tantalum, titanium, cobalt and mixtures thereof. The contact is metallized, preferably using tungsten or aluminum. The method of manufacturing the contact comprises etching the contact opening. A germane gas is used to clean native silicon dioxide from the bottom of the contact opening and to deposit a germanium layer thereon. A refractory metal layer is deposited over the germanium layer. After annealing in a nitrogen atmosphere at a temperature of about 600° C.

Abstract: Strong adhesion to doped low-k inter-layer dielectrics is provided by varying the composition of dopant near the surface layers of the inter-layer dielectric. The concentration of dopant is gradually increased from about zero atomic % at the interface between the inter-layer dielectric and semiconductor substrate to improve adhesion of the inter-layer dielectric to the semiconductor substrate. The concentration of dopant at the upper surface of the inter-layer dielectric is gradually decreased to about zero atomic % at the upper surface of the inter-layer dielectric film in order to improve adhesion of additional layers to the inter-layer dielectric.

Abstract: An integrated circuit comprising a conductive region formed on a semiconductor substrate, a silicate glass layer formed on the conductive region, and an etch stop layer formed on the silicate glass layer. The integrated circuit also includes a borderless contact that is coupled to the conductive region.

Abstract: An interlayer film covering a semiconductor device formed on the semiconductor substrate has a film having ability of gettering the metal impurities invading from an upper portion of the interlayer film, and with this ability, the metal impurities are prevented from reaching the semiconductor substrate.

Abstract: The present invention relates to low dielectric constant nanoporous silica films and to processes for their manufacture. A substrate, e.g., a wafer suitable for the production of an integrated circuit, having a plurality of raised lines and/or electronic elements present on its surface, is provided with a relatively high porosity, low dielectric constant, silicon-containing polymer film composition.

Abstract: A novel technology is provided for encapsulating electronics for use in harsh media applications, such as biomedical implants. The present invention includes electroplating a metal film on top of an insulating layer to hermetically seal an electronic system, microstructure, or micro device.

Abstract: A structure/method for reducing the stress between a dielectric, passivation layer and a metallic structure comprising coating the metallic structure with a low stress modulus buffer material, and forming the dielectric passivation layer covering the low stress modulus buffer material. The low stress modulus buffer material is composed of a layer of a polymeric material selected from at least one of the group consisting of a hydrogen/alkane SQ (SilsesQuioxane) resin, polyimide, and a polymer resin. The dielectric, passivation layer is composed of at least one layer of a material selected from at least one of the group consisting of silicon oxide and silicon nitride. A protective layer is formed over the dielectric, passivation layer. The low stress modulus buffer material has a thermal coefficient of expansion between that of the metallic structure and that of the dielectric passivation layer.

Abstract: This invention relates to a method of fabricating a light modulation system having a semiconductor substrate. In one exemplary method, an optical layer is applied over a semiconductor substrate which includes a plurality of integrated circuits. Each of these integrated circuits is capable of creating a separate display device. A protective layer is then applied over the optical layer. The plurality of integrated circuits is then singulated. Various other embodiments of apparatuses and methods are disclosed.

Abstract: A semiconductor device of the present invention has (1) an active element provided on a semiconductor substrate, (2) an interlayer insulating film formed so as to cover the active element, (3) a pad metal for an electrode pad which is provided on the interlayer insulating film, (4) a barrier metal layer which is provided on the active element with the interlayer insulating film therebetween, so that the pad metal is formed on the barrier metal layer, and (5) an insulating layer having high adherence to the barrier metal layer, the insulating layer being provided between the interlayer insulating film and the barrier metal layer. With this arrangement, the adherence between the barrier metal layer, the insulating film and the interlayer insulating film is surely improved, and even in the case where an external force is applied to the electrode pad upon bonding or after bonding, the barrier metal layer hardly comes off the part thereunder.

Abstract: A semiconductor device having an improved contact hole through an interlayer insulator. A first insulating film comprising silicon nitride is deposited. A second insulating film comprising silicon oxide is deposited on the first insulating film. The deposition condition of the second insulating film is varied during the deposition so that the etching rate of the second insulating film increases from a lower portion toward an upper portion. Thereby, a contact hole which is formed by etching through the first and second insulating films has a tapered configuration to improve a reliability of a connection made therein.

Abstract: The present invention provides a bonding pad on a semiconductor chip such that peeling of bonding pads during interconnection in the packaging process is avoided. The bonding pad is used to electrically connect an integrated circuit in the semiconductor chip with an external circuit. The semiconductor chip comprises a first dielectric layer positioned in a predetermined area on the surface of the semiconductor chip, a second dielectric layer positioned on the surface of the semiconductor chip outside the predetermined area wherein the first dielectric layer is harder than the second dielectric layer, and a bonding pad positioned on the first dielectric layer for electrically connecting anintegrated circuit (IC) in the semiconductor chip with an external circuit.

Abstract: A substrate, preferably silicon, or other suitable material has a layer of glass material disposed thereon. The glass material of the present disclosure has a substantially increased uniformity due to the reduction in bubbles as well as a relatively smooth top surface. By virtue of the reduction in the number and size of the bubbles in the glass the dielectric properties of the glass are more uniform. Additionally, the fact that the surface of the glass is much more smooth reduces the potential of prior structures to have an unacceptably thin glass layer due to the need to grind the surface smooth.

Abstract: A semiconductor device includes a substrate and wirings located on the substrate. A passivation film including a first insulating film containing an impurity is located on the wirings. The first insulating film is formed from silicon oxide film materials containing greater than one percent carbon.

Abstract: The invention includes a semiconductor wafer assembly, comprising: a) a semiconductor wafer substrate; and b) alternating first and second layers over the semiconductor wafer substrate, the alternating layers comprising at least one first layer and at least one second layer, the first layer comprising a first material and the second layer comprising a second material, the second material comprising atoms selected from the group consisting of yttrium, lanthanides, actinides, calcium, magnesium and mixtures thereof.

Abstract: A reinforced semiconductor package (20,30) and method utilizes at least one of the grooves (15,16) and ridges (24,25) formed on the package body (17,23) to reinforce the package body (17,23) to prevent warping of the package after molding.

Abstract: A structure and method for forming a hermetically sealed semiconductor chip having an active and a passive surface and four edge sides, each edge side having only a single plane; said active surface having an integrated circuit including multiple deposited layers and a plurality of contact pads, said contact pads having bondable and non-corrodible surface; said deposited layers having exposed portions at said side edges; a protective overcoat impermeable to moisture overlying said integrated circuit; and a continuous sealant layer impermeable to moisture overlying all area of said four side edges, whereby said edge sides are sealed and said chip is rendered hermetic.

Abstract: A semiconductor device is fabricated first by thermocompression-bonding a silicon oxide film onto a plurality of conductive films under vacuum using a film having the silicon oxide film formed thereon and then by separating the base film from the silicon oxide film. During the separation, the base film, being composed of a fluorine-containing resin, has smaller surface energy than a silicon oxide film and thus is easy to separate, leaving the silicon oxide film on the conductive films. As a result, the silicon oxide film is adhered on the conductive films so as to cover the conductive films, and an air gap is hence provided between the conductive films. Thus, a highly reliable semiconductor device capable of high-speed operation is provided by controlling parasitic capacitances between interconnections arranged accurately and adequately adjacent to each other so that recent needs for further miniaturization and higher integration of semiconductor elements can be met.

Abstract: A semiconductor device comprises a semiconductor substrate having an area in which a circuit element is formed; and a passivation film formed on an upper surface of the semiconductor substrate,

Abstract: The present invention provides a bonding pad on a semiconductor chip such that peeling of bonding pads during interconnection in the packaging process is avoided. The bonding pad is used to electrically connect an integrated circuit in the semiconductor chip with an external circuit. The semiconductor chip comprises a first dielectric layer positioned in a predetermined area on the surface of the semiconductor chip, a second dielectric layer positioned on the surface of the semiconductor chip outside the predetermined area wherein the first dielectric layer is harder than the second dielectric layer, and a bonding pad positioned on the first dielectric layer for electrically connecting anintegrated circuit (IC) in the semiconductor chip with an external circuit.

Abstract: A semiconductor device having an insulation protection film with increased reliability and improved device characteristics, and a manufacturing method thereof which improves the planarization and reduces the interlayer capacitance of the device. The semiconductor device has a semiconductor substrate including a MOS device, a plurality of wiring regions formed on the semiconductor substrate, and a protective insulation film formed on the top layer of the wiring regions. The protective insulation film includes a first silicon oxide film, a second silicon oxide film formed on the first silicon oxide film, and a silicon nitride film composing the top layer.

Abstract: A method for insulating metal conductors by spin-on-glass in inter-metal dielectric layers and devices formed by such method are disclosed. In the method, an additional step of scrubber clean is incorporated after an etch-back process on the spin-on-glass layer is conducted. Contaminating metal ions such as those of calcium is thus removed to eliminate formation of voids by such particles. The method can be easily implemented by including the additional scrubber clean step into a total wafer fabrication recipe.

Abstract: Providing a method for die bonding semiconductor elements surely without causing damage thereto in a shorter time with less steps of operations, thereby improving the productivity.

Abstract: A non-volatile memory device includes a floating-gate electrode overlying a tunnel oxide layer. A portion of the floating-gate electrode forms the control gate electrode for a sense transistor that is used to determine the presence of charge on the floating-gate electrode. A composite insulation layer overlies the floating-gate electrode. The composite insulation layer includes a dielectric layer, a doped insulating layer overlying the dielectric layer, and a planarization layer overlying the doped insulating layer. The thicknesses of the dielectric layer and the doped insulating layer are precisely determined, such that the doped insulating layer getters mobile ions, such as hydrogen ions, away from the floating-gate electrode, while not capacitively coupling with the floating-gate electrode.

Abstract: In a laser beam make-link programmable semiconductor device, a pair of conductor strips are formed in the same level plane on a lower level insulator film formed on a semiconductor substrate, and are separated from each other in such a manner that opposing ends of the pair of conductor strips are separated by a predetermined distance smaller than a film thickness of the upper level insulator film. An upper level insulator film substantially transparent to a laser beam, is formed on the conductor strips. With this arrangement, even if a trimming laser beam has a small energy, the laser beam permeates through the upper level insulator film to reach and melt the opposing ends of the pair of conductor strips, with the result that the opposing ends of the pair of conductor strips are short-circuited.

Abstract: An etchant including C.sub.2 H.sub.x F.sub.y, where x is an integer from two to five, inclusive, where y is an integer from one to four, inclusive, and where x plus y equals six. The etchant etches doped silicon dioxide with selectivity over both undoped silicon dioxide and silicon nitride. Thus, undoped silicon dioxide and silicon nitride may be employed as etch stops in dry etch processes which utilize the C.sub.2 H.sub.x F.sub.y -containing etchant. C.sub.2 H.sub.x F.sub.y may be employed as either a primary etchant or as an additive to another etchant or etchant mixture. The invention also includes semiconductor devices that include structures that have been patterned with an etchant of the present invention or in accordance with the method of the present invention. Specifically, the present invention includes semiconductor devices including doped silicon oxide structures with substantially vertical sidewalls and adjacent undoped silicon oxide or silicon nitride structures exposed adjacent the sidewall.

Abstract: A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm.sup.3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 10.sup.21 atoms/cm.sup.3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.

Abstract: A process is provided for forming dielectric structures having a relatively low dielectric constant arranged adjacent to the opposed lateral edges of a trench isolation structure. In an embodiment, an opening is etched vertically through a masking layer arranged upon a semiconductor substrate, thereby exposing the surface of the substrate. A patterned photoresist layer is formed upon the masking layer using optical lithography to define the region to be etched. Sidewall spacers made of a low K dielectric material are formed upon the opposed sidewall surfaces of the masking layer within the opening. The sidewall spacers are formed by CVD depositing a dielectric material within the opening and anisotropically etching the dielectric material until only a pre-defined thickness of the material remains upon the masking layer sidewall surfaces. Thereafter, a trench defined between the exposed lateral edges of the sidewall spacers is formed within the substrate.

Abstract: A process for the formation of a device edge morphological structure for protecting and sealing peripherally an electronic circuit integrated in a major surface of a substrate of semiconductor material. The electronic circuit is of the type that calls for formation above the major surface of at least one dielectric multilayer. The dielectric multilayer includes a layer of amorphous planarizing material having a continuous portion extending between two contiguous areas with a more internal first area and a more external second area in the morphological structure. The device edge morphological structure includes in the substrate an excavation on the side of the major surface at the more internal first area of the morphological structure in a zone in which is present the continuous portion of the dielectric multilayer.

Abstract: Spacings between metal features are gap filled with HSQ without degradation of the electromigration resistance by depositing a conformal dielectric liner encapsulating the metal features before depositing the HSQ gap fill layer. Embodiments include depositing a conformal layer of a high density plasma oxide by high density plasma chemical deposition to a thickness of about 100 .ANG. to about 1,000 .ANG..

Abstract: A semiconductor processing method is provided for making contact openings. It includes depositing several insulative layers and performing an anisotropic etch. One layer is a conformal oxide covering the contact area and adjacent structures. A second layer is a breadloafed oxide deposited over the contact area and adjacent structures. A third layer is a doped oxide deposited over the two lower layers. The anisotropic etch is performed through the oxide layers to the contact area located on a lower substrate. The etch is selectively more rapid in the third oxide than in the two other oxides. The breadloafed oxide provides additional protection and reduces the risk of etch-through to conductive structures adjacent the contact area. An alternate embodiment replaces the two lowest oxide layers by a breadloafed nitride layer. In this embodiment, the anisotropic etch is selectively more rapid in oxides than in nitrides.

Abstract: A process for fabricating a semiconductor device using an etching stopper film which does not increase the number of photo-etching steps and does not cause a deterioration in device characteristics comprises the steps of: forming an impurity region at the surface of a semiconductor substrate; forming a first insulating layer on the semiconductor substrate; forming a first hole in the first insulating layer and thereby exposing the impurity region; forming a first metal layer on the first insulating layer and the inner surface of the first hole; forming a second metal layer on the region of the first metal layer formed on the inner surface of the first hole and filling the first hole with the second metal layer; oxidizing the first metal layer with the second metal layer as a mask; forming a second insulating layer on the first metal layer and the second metal layer; forming a second hole in the second insulating layer exposing the second metal layer by etching the second insulating layer with the first metal

Abstract: A method for planarizing integrated circuit topographies, wherein, after a first layer of spin-on glass is deposited, a layer of low-temperature oxide is deposited before a second layer of spin-on glass.

Abstract: The MOSFET has a stacked gate structure which has a first silicon layer, a second silicon layer, and a spacer structure. The first silicon layer is formed over the semiconductor substrate. The second silicon layer contains second type dopants and is formed on the first silicon layer. The spacer structure containing first type dopants is formed on the sidewall of the first silicon layer and the second silicon layer. A gate insulator layer is formed between the first silicon layer and the semiconductor substrate. The second silicon layer is also formed on the semiconductor substrate at a region uncovered by the stacked gate structure. A junction region is formed in the semiconductor substrate under the second silicon layer but not under the stacked gate structure. An extended junction is formed in the semiconductor substrate under the spacer structure.

Abstract: Significant amounts of pattern distortion were found to be the result of reflowing borophosphosilicate glass (BPSG) and silicon dioxide shrinkage during high temperature junction anneals. In order to remedy this problem, a method for suppressing the pattern distortion by subjecting the wafer coated with BPSG and with silicon dioxide layers to a high temperature anneal before patterning is disclosed. The high temperature anneal densifies the undoped silicon dioxide before patterning, so that shrinkage of the undoped silicon dioxide does not affect the patterning steps.

Abstract: A process for the formation of a device edge morphological structure for protecting and sealing peripherally an electronic circuit integrated in a major surface of a substrate of semiconductor material includes formation above an intermediate process structure of a dielectric multilayer comprising a layer of amorphous planarizing material. The process also includes the partial removal of the dielectric multilayer so as to create at least one peripheral termination of the multilayer in the device edge morphological structure. Removal of the dielectric multilayer requires that the peripheral termination thereof be located in a zone of the intermediate process structure relatively higher than the level of the major surface, if compared with adjacent zones of the intermediate structure itself at least internally toward the circuit and in so far as to the device edge morphological structure.

Abstract: A method for forming air gaps 22 between metal leads 16 of a semiconductor device and semiconductor device for same. A metal layer is deposited on a substrate 12. The metal layer is etched to form metal leads 16. A disposable solid layer 18 is deposited between the metal leads 16. A porous dielectric layer 20 is deposited on the disposable solid layer 18 and the tops of the leads 16, and the disposable solid layer 18 is removed through the porous dielectric layer 20, to form air gaps 22 between the metal leads 16 beneath the porous dielectric layer 20. The air gaps have a low-dielectric constant and result in reduced sidewall capacitance of the metal leads.

Abstract: A process for forming a structure including an epitaxial layer of a oxide material such as yttria-stabilized zirconia on a thick layer of amorphous silicon dioxide having a thickness of at least about 500 Angstroms on a single crystal silicon substrate and the resultant structures derived therefrom are provided.

Abstract: A semiconductor device (11) has a spin on glass layer or region, and the spin on glass has a method of synthesis and use. The spin on glass composition is formed which comprises on the order of 0% to 20% by volume of tetraethylorthosilicate (TEOS), on the order of 0.01% to 20% by volume of tetraethylorthogermanate (TEOG), on the order of 0% to 1% by volume the equivalent of nitric acid (HNO.sub.3), on the order of 70% to 85% by volume of alcohol, and a remaining balance of the spin on glass composition being water. The spin on glass is applied to a semiconductor substrate and heated and/or densified to form the spin on glass layer or region.