Abstract: A semiconductor device which contains an electrode or an interconnection subjected to a high voltage prevents current leakage due to polarization of a mold resin. In this semiconductor device, a glass coat film 13a covering a semiconductor element has an electrical conductivity in a range defined by the following formula (1) under the conditions of temperature between 17.degree. C. and 145.degree. C.:conductivity.gtoreq.1.times.10.sup.-10 /E (1)(E: an electric field intensity ?V/cm!, E.gtoreq.2.times.10.sup.4 ?V/cm!)Owing to employment of the electrically conductive glass coat film, an electron current flowing through the conductive glass coat film suppresses an electric field caused by polarization of a mold resin.

Abstract: A method is provided for improving the adhesion between a photoresist layer and a dielectric, and an integrated circuit formed according to the same. A conformal dielectric layer is formed over the integrated circuit. An interlevel dielectric layer is formed over the conformal dielectric layer. The interlevel dielectric layer is doped such that the doping concentration allows the layer to reflow while partially inhibiting the adhesion of the doped layer to photoresist at an upper surface of the doped layer. An undoped dielectric layer is formed over the doped dielectric layer. A photoresist layer is formed and patterned over the undoped dielectric layer which adheres to the undoped dielectric layer. The undoped dielectric, the interlevel dielectric and the conformal dielectric layers are etched to form an opening exposing a portion of an underlying conductive region.

Abstract: A low dielectric insulation layer for an integrated circuit structure material, and a method of making same, are disclosed. The low dielectric constant insulation layer comprises a porous insulation layer, preferably sandwiched between non-porous upper and lower insulation layers. The presence of some gases such as air or an inert gas, or a vacuum, in the porous insulation material reduces the overall dielectric constant of the insulation material, thereby effectively reducing the capacitance of the structure. The porous insulation layer is formed by a chemical vapor deposition of a mixture of the insulation material and a second extractable material; and then subsequently selectively removing the second extractable material, thereby leaving behind a porous matrix of the insulation material, comprising the low dielectric constant insulation layer.

Abstract: A static random access memory device includes: a semiconductor substrate divided into a cell array portion and a periphery circuit portion; a first insulating layer for insulating devices formed on the substrate from a thin-film transistor; a conductive layer formed on the first insulating layer in the cell array portion, for supplying power; a buffer layer formed on the conductive layer in the cell array portion; a second insulating layer formed on the buffer layer in the cell array portion and on the first insulating layer of the periphery circuit portion; and a metal wiring pattern formed on the second insulating layer. A first portion of the metal wiring pattern connects to the conductive layer via a first contact hole which is formed passing through the second insulating layer and the buffer layer, thus exposing the conductive layer in the cell array portion.

Abstract: The invention proposes methods for producing integrated circuits wherein the dielectric constant between closely spaced and adjacent metal lines is approaching 1. One method of the invention uses low-melting-point dielectric to form a barrier form a void between conductive lines. Another method of the invention uses sidewall film to form a similar barrier.

Abstract: A semiconductor device has a memory cell area which contains a component having a height and a peripheral circuit area free of a component having a height. The first area includes a interlayer insulating film comprising a first interlayer film as an uppermost insulating film. The second area includes an interlayer insulating film comprising the first interlayer film and a second interlayer film disposed directly on the first interlayer film and having a chemical mechanical polishing rate greater than the first interlayer film. The interlayer insulating film in the memory cell area has a surface higher than the interlayer insulating film in the peripheral circuit area.

Abstract: A method is provided for forming contact via in an integrated circuit. Initially, a first buffer layer is formed over an insulating layer in an integrated circuit. The first buffer layer has a different etch rate from the insulating layer. A second buffer layer is then formed over the first buffer layer, with the second buffer layer having an etch rate which is faster than the first buffer layer. An isotropic etch is performed to create an opening through the second buffer layer and a portion of the first buffer layer. Because the second buffer layer etches faster than the first buffer layer, the slant of the sideswalls of the opening can be controlled. An anisotropic etch is then performed to complete formation of the contact via.

Abstract: This invention deals with the formation of the multi-level electrode metal structure and the interconnecting inter-level metal studs used in the fabrication of VLSI circuits. After the metal layers have been formed the inter-level dielectric material used in forming the structure is etched away leaving an air dielectric between the levels. The electrode metal and the inter-level metal studs are coated with a thin envelope oxide and the entire structure is covered with a passivation layer using material with a poor step coverage. The structure of this invention provides reduced parasitic capacitance, better step coverage in interconnecting layers, and improved circuit performance.

Abstract: A method of planarizing wide bandgap semiconductor devices selected from a group including SiC, GaN and diamond having a mesa defined thereon by a trench with a depth of 1 to 2 micrometers and a width of 2 to 10 micrometers. A layer of dielectric material is deposited on the substrate overlying and surrounding the mesa, to a height approximately equal to the height of the mesa and the dielectric material is etched from atop the mesa and from a surrounding area. Layers of spin on glass are deposited to fill the surrounding area and etched to achieve a planar surface including the mesa and the layer of dielectric material.

Abstract: A method and structure for self-aligned zero-margin contacts to active and poly-1, using silicon nitride (or another dielectric material with low reflectivity and etch selectivity to oxide) for an etch stop layer and also for sidewall spacers on the gate.

Abstract: A MOS type transistor with a gate is formed on the surface of a semiconductor substrate, and thereafter an interlayer insulating film and a first level wiring layer on the insulating film are formed. The wiring layer is patterned to cover the gate electrode. A second level interlayer insulating film is formed covering the wiring layer 16, and a second level wiring layer is formed on the second level interlayer insulating film. The second level interlayer insulating film is a laminate of a silicon oxide film formed by plasma CVD using tetraethoxysilane, a spin-on-glass (SOG) film, and another similar silicon oxide film, sequentially formed in this order. An auxiliary electrode layer (blocking layer) of the first level wiring layer covering the gate electrode prevents moisture contents from being diffused from the second level interlayer insulating film toward the gate electrode.

Abstract: A resin molded semiconductor device having wiring layers and interlayer insulating layers inclusive of an SOG film, capable of suppressing generation of cracks in an SOG film to be caused by thermal stress. In the outer peripheral area of a semiconductor chip, via holes are formed in an interlayer insulating layer inclusive of an SOG film to substantially reduce residual SOG film. As an underlying layer of the interlayer insulating layer inclusive of the SOG film, dummy wiring patterns are formed to thin the SOG film on the dummy wiring patterns. Dummy wiring patterns may also be formed by using a higher level wiring layer, burying the via holes and contacting the lower level dummy wiring patterns.

Abstract: The invention relates to MOS devices and methods for fabricating MOS devices having multilayer metallization. In accordance with preferred embodiments, internal passivation is used for suppressing device degradation from internal sources. Preferred devices and methods for fabricating such devices include formation of one or more oxide layers which are enriched with silicon to provide such an internal passivation and improve hot carrier lifetime. Preferred methods for fabricating MOS devices having multi-level metallization include modifying the composition of a PECVD oxide film and, in some embodiments, the location and thickness of such an oxide. In an exemplary preferred embodiment, PECVD oxide layers are modified by changing a composition to a silicon enriched oxide.

Abstract: A process and resulting product is described for forming an oxide in a semiconductor substrate which comprises initially implanting the substrate with atoms of a noble gas, then oxidizing the implanted substrate at a reduced temperature, e.g., less than 900.degree. C., to form oxide in the implanted region of the substrate, and then etching the oxidized substrate to remove a portion of the oxide. The resulting oxidation produces a dual layer of oxide in the substrate. The upper layer is an extremely porous and frothy layer of oxide, while the lower layer is a more dense oxide. The upper porous layer of oxide can be selectively removed from the substrate by a mild etch, leaving the more dense oxide layer in the substrate. Further oxide can then be formed adjacent the dense layer of oxide in the substrate, either by oxide deposition over the dense oxide or by growing further oxide beneath the dense oxide layer.

Abstract: A semiconductor device which contains an electrode or an interconnection subjected to a high voltage prevents current leakage due to polarization of a mold resin. In this semiconductor device, a glass coat film 13a covering a semiconductor element has an electrical conductivity in a range defined by the following formula (1) under the conditions of temperature between 17.degree. C. and 145.degree. C.:conductivity.gtoreq.1.times.10.sup.-10 /E . . . (1)(E: an electric field intensity ?V/cm!, E.gtoreq.2.times.10.sup.4 ?V/cm!)Owing to employment of the electrically conductive glass coat film, an electron current flowing through the conductive glass coat film suppresses an electric field caused by polarization of a mold resin.

Abstract: The present invention provides a structure and method of manufacturing an interlevel/intermetal dielectric layer for a semiconductor device. The method begins by forming a stepped pattern 16 on a semiconductor structure 12. A barrier layer 20 composed of silicon oxide is formed on the semiconductor substrate so as to cover the surface of the stepped pattern 16. A first insulating layer 22 composed of silicon oxide is then formed over the barrier layer 20. A high P (phosphorous) content silicon glass layer 24 preferably is formed over the first insulating layer 22. The high P content silicon glass layer 24 has a phosphorous concentration in a range of about 4 and 10 weight percent. Next, in an important step, a graded P content silicon glass layer 26 is formed over the high P content silicon glass layer 24. The graded P content silicon glass layer 26 has a phosphorous concentration in a range of about 0.1 and 4 weight percent.

Abstract: A method and structure for reducing short circuits in semiconductor devices is disclosed. A three layer interlevel dielectric structure is formed over a semiconductor substrate, which typically comprises a first metallization level, M1. The three layer dielectric includes a first insulator layer, a middle spin-on glass (SOG) layer, and a top second insulator layer. The spin-on glass fills defects in the surface of the first insulator layer created during planarization using chemical-mechanical-polishing (CMP). Prior to deposition of the second insulator, a first via is etched through the SOG film and the first insulator layer to expose a portion of the semiconductor substrate, typically a conductive metal. A conductive metal is deposited into the first via and planarized to form a metal interconnection stud. Because the surface defects are filled and covered with the SOG film, none of the deposited metal enters the defects, and short circuits with the stud are greatly reduced.

Abstract: A ROM device with an array of cells has conductors formed in a substrate. Insulation is formed, and parallel conductors are formed orthogonally to the line regions, as thin as about 2000 .ANG.. Glass insulation having a thickness of about 3000 .ANG. or less, formed over the conductors is is reflowed. Contacts and a metal layer on the glass insulation are formed. Resist is patterned and used for etching the resist pattern in the metal. Removal of the second resist and device passivation with a layer having a thickness of about 1000 .ANG., precede activation of the impurity ions by annealing the device at less than or equal to about 520.degree. C. in a reducing gas atmosphere. After resist removal, a second resist is formed and exposed with a custom code pattern to form a mask. Ions are implanted into the substrate with a dosage of between about 1 E 14 and 3 E 14 atoms/cm.sup.2 with an energy of less than or equal to 200 keV adjacent to the conductors through the openings in the insulation.

Abstract: A solid state image picking-up device such as a charge coupled device (CCD) includes a channel region and a photo-diode region formed on a semiconductor region apart from each other, a first insulating film formed on the semiconductor region including the channel region and the second semiconductor region to have a concave portion above the photo-diode region, and a charge transfer electrode interposed in said first insulating film and extending over the channel region and a region between the channel region and the photo-diode region. A light shielding film is formed on the first insulating film over the channel region and a second insulating film is formed on the light shielding film and the first insulating film. A protection film composed of BPSG or PSG is formed to fill the concave portion on the second insulating film. A third insulating film is formed on the protection film and a flattening resin film is formed on the third insulating film. The protection film is formed of a BPSG film containing P.sub.

Abstract: An insulating layer with at least one via is provided over a metal plate. A sacrificial layer is applied over a portion of the insulating layer so that the sacrificial layer extends into the via. A metal bridge having at least one opening is provided over a portion of the sacrificial layer and a portion of the insulating layer so that the metal bridge extends over the via and the opening is situated adjacent a portion of the sacrificial layer. A reinforcing seal layer with a well is provided over the metal bridge so that the well is situated adjacent to at least a portion of the opening. The sacrificial layer is then removed.

Abstract: A method for planarizing integrated circuit topographies, wherein, after a first layer of spin-on glass is deposited, a layer of low-temperature oxide is deposited before a second layer of spin-on glass.

Abstract: A method for improved adhesion between dielectric material layers at their interface during the manufacture of a semiconductor device, comprising operations for forming a first layer (1) of a dielectric material, specifically silicon oxynitride or silicon nitride, on a circuit structure (7) defined on a substrate of a semiconductor material (6) and subsequently forming a second layer (3) of dielectric material (silicon oxynitride or silicon nitride particularly) overlying the first layer (1). Between the first dielectric material layer and the second, a thin oxide layer (2), silicon dioxide in the preferred embodiment, is formed in contact therewith. This interposed oxide (2) serves an adhesion layer function between two superimposed layers (1,3).

Abstract: A low dielectric insulation layer for an integrated circuit structure material, and a method of making same, are disclosed. The low dielectric constant insulation layer comprises a porous insulation layer, preferably sandwiched between non-porous upper and lower insulation layers. The presence of some gases such as air or an inert gas, or a vacuum, in the porous insulation material reduces the overall dielectric constant of the insulation material, thereby effectively reducing the capacitance of the structure. The porous insulation layer is formed by a chemical vapor deposition of a mixture of the insulation material and a second extractable material; and then subsequently selectively removing the second extractable material, thereby leaving behind a porous matrix of the insulation material, comprising the low dielectric constant insulation layer.

Abstract: A planarization process for the manufacturing of highly-planar interlayer dielectric thin films in integrated circuits, particularly in non-volatile semiconductor memory devices, comprises the steps of: forming a first barrier layer over a semiconductor substrate wherein integrated devices have been previously obtained; forming a second layer of oxide containing phosphorous and boron over the first undoped oxide the concentration of boron being lower than the concentration of phosphorous; forming a third layer of oxide containing phosphorous and boron over the second oxide layer, the concentration of phosphorous being lower than or equal to the concentration of boron; performing a thermal process at a temperature sufficient to melt the third oxide layer, to obtain a planar surface.

Abstract: A ROM device includes cells with buried bit lines in a semiconductor substrate. A thin insulating layer covers the substrate has closely spaced, parallel, word lines formed thereon arranged orthogonally relative to the bit lines. The word lines are covered with reflowed glass insulating layers about 2500.ANG. thick. The glass insulating layers comprise a sublayer of undoped glass and an overlayer of doped glass, the underlayer about 500.ANG.-1500.ANG. thick and the overlayer about 1000.ANG.-1500.ANG. thick. An etched, patterned metal layer is formed on the glass insulating layer. The overlayer has been substantially removed by etching where the metal layer has been etched. An ion implantation pattern has been implanted into the substrate adjacent to the conductive lines. The device has been passivated. The implanted impurity ions having been activated by annealing the device.

Abstract: A multilevel metallization is deposited on a microelectronic device base structure (40). The process includes depositing a glassy dielectric layer (48) of a thickness that is from about two to about three times as thick as the topography thickness (D) of the base structure (40). The glassy dielectric layer (48) is heated to a temperature above its glass transition temperature to flow the glassy dielectric layer (48). The glassy dielectric layer (48) is thinned to a preselected thickness, and a first patterned metallization layer (54) is deposited. The process further includes depositing an interlevel dielectric layer (58), dry etching the interlevel dielectric layer (58) to thin the interlevel dielectric layer (58) and, optionally, depositing additional interlevel dielectric layer (58') material to achieve a preselected thickness. A second patterned metallization layer (64) is deposited over the interlevel dielectric layer ( 58/58').

Abstract: An interconnect structure and method is described herein. First, interconnect lines 14a-d are formed on a semiconductor body 10. Then, a dielectric layer 20 is coated over the semiconductor body and the interconnect lines 14a-d to a thickness sufficient to more than fill the gaps between adjacent interconnect lines. The dielectric layer 20 is baked and then cured at a elevated temperature greater than the baking temperature. By using baking, then curing, the dielectric layer 20 inside the gaps has a lower density than that above interconnect lines and that in open fields. The removal of dielectric layer from the top of the interconnect lines by etchback is optional. Finally, a layer of silicon dioxide 12 is deposited over the interconnect lines 14a-d and the dielectric layer 20. In one embodiment, contact vias 11 are then etched through the silicon dioxide 12 and dielectric layer 20 to the interconnect lines 14a-c. Preferably, the dielectric material is spun on.

Abstract: A layered dielectric structure is provided, which separates a first layer of metal interconnects from each other in semiconductor devices and also separates the first layer from a second, overlying layer of metal interconnects for making electrical contact to the first layer of metal interconnects. The layered dielectric structure comprises: (a) a layer of an organic spin-on-glass material filling gaps between metal interconnects in the first layer of metal interconnects; (b) a layer of an inorganic spin-on-glass material to provide planarization to support the second layer of metal interconnects; and (c) a layer of a chemically vapor deposited oxide separating the organic spin-on-glass layer and the inorganic spin-on-glass layer. The layered dielectric structure provides capacitances on the order of 3.36 to 3.46 in the vertical direction and is about 3.2 in the horizontal direction. This is a reduction of 10 to 15% over the prior art single dielectric layer, using existing commercially available materials.

Abstract: An LED array is fabricated by forming an insulating film on a semiconductor substrate of a first conductive type, forming a plurality of windows in the insulating film, and diffusing an impurity of a second conductive type through these windows to create a plurality of diffusion regions. In addition, an anti-reflection coating consisting of one or more transparent dielectric thin films is formed on the diffusion regions where they are exposed in the windows. The thickness of the anti-reflection coating, or of its constituent thin films, is optimized for maximum transmission of light.

Abstract: An LED array, including a semiconductor substrate of a first conductive type; a first insulating film formed on the substrate, comprising aluminum oxide and having a plurality of first windows; a second insulating film formed on the first insulating film, having a plurality of second windows aligned respectively with the plurality of first windows, the plurality of second windows being formed by a photolithography process that does not etch the first insulting film; a plurality of diffusion regions of a second conductive type, formed by diffusion of an impurity of the second conductive type through the plurality of first windows into the semiconductive substrate, for creating pn junctions from which and from near which light is emitted, principally through the plurality of first windows and the plurality of second windows; and a plurality of electrodes formed on the second insulating film, extending through the plurality of first windows and the plurality of second windows, and making electrical contact with

Abstract: Reduced soft errors in charge-sensitive circuit elements such as volatile memory cells 200 occur by using boron-11 to the exclusion of boron-10 or essentially free of boron-10 in borosilicate glass 230, 240 deposited on the substrate 206 directly over the arrays of memory cells. Boron-10 exhibits a high likelihood of fission to release a 1.47 MeV alpha particle upon capture of a naturally occurring cosmic ray neutron. This capture occurs frequently in boron-10 because of its high neutron capture cross-section. Boron-11 does not fission.

Abstract: A new method of forming stress releasing voids within the intermetal dielectric of an integrated circuit is achieved. A first layer of patterned metallization is provided over semiconductor device structures in and on a semiconductor substrate. A silicon oxide layer is deposited overlying the first patterned metal layer. A silicon nitride layer is deposited over the silicon oxide layer. A metal layer is deposited over the silicon nitride layer and etched to form silicon nodules on the surface of the silicon nitride layer. The silicon nitride layer is etched away to the underlying silicon oxide layer wherein the silicon nitride under the silicon nodules remains in the form of pillars. The surface of the silicon oxide layer is coated with a spin-on-glass material which is baked and cured. The silicon nodules and silicon nitride pillars are removed, leaving voids within the spin-on-glass layer.

Abstract: A CMOS integrated circuit uses self-aligned transistors combined with local planarization in the vicinity of the transistors so as allow local interconnects which are free of bridging, have good continuity over the planarized topography and are compatible with the self-alignment schemes, hence conserving chip real estate. After formation of self-aligned insulated transistor gates and active transistor regions, the integrated circuit structure is planarized by formation of an oxide layer and a reflowed overlying glass layer. The glass layer and underlying oxide layer are removed only in the area of the buried contact, while an overlying metal or polysilicon conductive layer contacts the upper surface of certain of the transistor gate structures, the topside insulating layer of which has been removed for this purpose.

Abstract: In the solid-state image pickup device of the invention, a photodiode is formed on a semiconductor substrate, and a transfer channel is formed at a specific gap to the photodiode. On the semiconductor substrate, a transfer gate electrode formed through a gate dielectric film is provided, and an interlayer film is formed on the transfer gate electrode. Furthermore, a first light-shield film for shielding the transfer channel from light is formed on the interlayer film. On the first light-shield film, a second light-shield film is formed at least through an interlayer dielectric film. In this case, the interlayer dielectric film is composed of multiple layers of at least first interlayer dielectric film and second interlayer dielectric film, and in etching of the interlayer dielectric film, the second interlayer dielectric film is smaller in the etching rate to the first interlayer dielectric film, and the second interlayer dielectric film is formed beneath the first interlayer dielectric film.

Abstract: A semiconductor device has a conductive interconnection layer formed on a semiconductor substrate covered with a protection insulation film. A pad electrode opening is provided in the protection insulation film so that the surface of the conductive interconnection layer is exposed in the region which becomes the pad electrode. The conductive interconnection layer is electrically connected to an external terminal by a bonding wire. At least the surface of the protection insulation film in the proximity of the pad electrode opening and the inner peripheral side face of the pad electrode opening are covered with an elastic insulation film. The pad electrode opening is covered with the bonding wire. Since the conductive interconnection layer is not exposed at the pad electrode opening according to this structure, the phenomenon of moisture intruding into the pad electrode opening to corrode the conductive interconnection layer is prevented to improve reliability.

Abstract: A structure is provided for improving the adhesion between a photoresist layer and a dielectric, and an integrated circuit formed according to the same. A conformal dielectric layer is formed over the integrated circuit. An interlevel dielectric layer is formed over the conformal dielectric layer. The interlevel dielectric layer is doped such that the doping concentration allows the layer to reflow while partially inhibiting the adhesion of the doped layer to photoresist at an upper surface of the doped layer. An undoped dielectric layer is formed over the doped dielectric layer. A photoresist layer is formed and patterned over the undoped dielectric layer which adheres to the undoped dielectric layer. The undoped dielectric, the interlevel dielectric and the conformal dielectric layers are etched to form an opening exposing a portion of an underlying conductive region.

Abstract: A method for forming contact vias in a integrated circuit which do not have planarizing material nearby. After a first insulating layer is deposited over the integrated circuit, a planarizing layer is deposited over the first insulating layer. The planarizing layer is etched back and portions of the planarizing layer may remain in the lower topographical regions of the first insulating layer to planarize the surface of the integrated circuit. A first masking layer is then formed over the surface of the integrated circuit. The openings created in the first masking layer have a size which is greater than the size of the contact vias to be formed. The first insulating layer is partially etched into so that portions of the planarizing layer near the locations of the contact vias are removed. The first masking layer is then removed, and a second insulating layer is deposited over the integrated circuit.

Abstract: An electrically programmable read only memory device store data bits in the form of electric charges accumulated in floating gate electrodes of the memory cells, and a spin-on glass film is incorporated in an inter-level insulating film structure over the memory cells so as to create a smooth surface for wirings, wherein a silicon oxynitride film is inserted between the floating gate electrodes and the spin-on-glass film for preventing the accumulated electric charges from undesirable ion-containing water diffused from the spin-on-glass film.

Abstract: A cryogenic radiation-hard dual-layer field oxide of reoxidized nitrided oxide (ONO) which provides radiation hardness for field-effect transistors and other semiconductor devices at cryogenic temperatures. The dual-layer field oxide includes a thin lower dielectric layer of reoxidized nitrided oxide and an upper deposited dielectric layer that remains charge neutral. The upper dielectric layer is preferably silicon nitride or a doped oxide, such as phospho silicate glass or boro phospho silicate glass. The lower dielectric layer can be made very thin since reoxidized nitrided oxide is a much better barrier layer to the diffusion of boron or phosphorous from the upper dielectric layer into the silicon substrate than silicon dioxide. A thin lower dielectric layer allows only a small amount of positive charge buildup, while the upper dielectric layer traps both holes and electrons and remains charge neutral.

Abstract: The method for fabrication of openings in semiconductor devices to improve metal step coverage includes forming an active region over a substrate. A metal oxide layer is then formed over the source/drain region. An insulating layer is formed over the metal oxide layer. A photoresist layer is formed over the insulating layer, and patterned to form an opening, exposing a portion of the insulating. The insulating layer is then etched to expose a portion of the metal oxide layer. The photoresist layer is removed and the insulating layer is reflowed so as to form rounded corners at the opening of the insulating layer. The exposed portion of the metal oxide layer is removed to expose a portion of the active region.

Abstract: A dynamic random access memory comprises a memory cell region and a sense amplifier region defined on a substrate, a plurality of memory cell capacitors provided on the memory cell region in correspondence to memory cell transistors, a first insulation layer provided on the semiconductor substrate to cover both the memory cell region and the sense amplifier region, a first conductor pattern provided on the first insulation layer, an intermediate connection pattern provided on the first insulation layer in correspondence to the sense amplifier region, a spin-on-glass layer provided on the first insulation layer to extend over both the memory cell region and the sense amplifier region, and a projection part provided on the substrate of the sense amplifier region in correspondence to the intermediate connection pattern under the first insulation layer for lifting the level of the surface of the first insulation layer such that the intermediate interconnection pattern is exposed above the upper major surface of t

Abstract: An integrated circuit structure is presented that includes a substrate in which integrated circuit elements are constructed, a first interconnection metalization over the substrate interconnecting selected ones of the integrated circuit elements, and an oxide layer over the substrate and the first metal interconnection pattern. A glass layer over the oxide layer is substantially planar between portions that overlie the metalization and portions that do not over lie the metalization.

Abstract: A radiation hardened MOSFET is fabricated by forming a dielectric layer of boro-phosphosilicate glass (BPSG) over the field oxide layer of the MOSFET. The BPSG covers only a small part of the gate electrode of the MOSFET. The gate electrode of the MOSFET is formed from two layers of polycrystalline silicon so as to prevent contamination of the gate oxide by the BPSG dopants.

Abstract: An integrated circuit has a silicon mesa disposed on a substrate and a field insulator structure in proximity to the mesa and having an opening over a top mesa surface. The opening, which exposes sidewalls in the structure, is positioned with respect to the mesa and has dimensions such that the structure is disposed to overlap a region of the mesa along an outer mesa periphery. A layer of polysilicon extends along a top surface of the structure and into the opening and adjacent to the mesa top surface. An insulator is disposed between the poly layer and the mesa top surface, the insulator having a layer of thermal gate oxide disposed adjacent to the poly layer and having a layer of pyrogenic oxide disposed between the thermal gate oxide layer and the mesa top surface.

Abstract: In a semiconductor integrated circuit comprising an array of memory cells of floating gate type MOS transistors, an insulating film is formed on the top surface and the side walls of the gate electrode portion. The insulating films on the side walls serve as an offset region of a channel contacting with the drain region. The side end portions of the drain region, contacting the channel region has a lower impurity concentration than the remaining portion of the drain region. A conductive layer covers the surface of the drain region and at least the insulating films on the side walls of the gate electrode, which upstands above both ends of the drain region. A metal interconnection layer is deposited on the conductive layer.