Abstract: A lead frame is fabricated by a stamping system, and the lead frame 1 having a predetermined pattern is fabricated by blanking a lead frame material by a progressive stamping die apparatus while the lead frame material is being consecutively transferred. A pressing force is applied to burrs occurring during the fabrication of the lead frame 1 so as to squeeze the burrs, thereby forming coined portions 6 and 7. Next, a coined groove 8 is formed horizontally on the surface of the lead frame 1 at a position slightly above a resin liquid level 4. Resin climbing 5 in which the resin rises from the liquid level due to a capillary phenomenon is stopped at the position of the coined groove 8 thus formed, thereby allowing soldering of the lead frame 1 to be effected without a hindrance.

Abstract: A semiconductor device comprising an insulating film on which a plurality of bumps and wires connected to the bumps are formed, a semiconductor chip connected to the wires and mounted to the insulating film, an epoxy resin provided in a connection portion between the semiconductor chip and the insulating film, and a radiating plate adhered to the semiconductor chip, wherein a space is formed between the insulating film and the radiating plate, and holes through which ventilation can be performed are formed in the insulating film at the positions corresponding to the space.

Abstract: The electrical interconnections between an integrated circuit chip assembly are encapsulated and reinforced with a high viscosity encapsulant material in a single step molding process wherein a mold is placed over an integrated circuit chip assembly and encapsulant material is dispensed through an opening in the mold and forced around and under the integrated circuit chip by external pressure encapsulating the integrated circuit chip assembly. An integrated circuit chip assembly having a reinforced electrical connection which is more resistant to weakening as a result is stress created by differences in coefficient of thermal expansion between the integrated circuit chip and the substrate to which the integrated circuit chip is attached is produced.

Abstract: In apparatus and method for shaping a lead frame for a semiconductor device, there are provided a lower die having a concave shape for forming a step portion on the lower surface of the lead frame through a slope shape, an upper die having a convex shape which is downwardly moved to press a part of the lead frame in cooperation with the lower die and form a step portion through a slope shape on the upper surface of the lead frame, and a press portion which is disposed around the upper die and presses the outer portion of the lead frame at the outside from the semiconductor element mount portion, wherein the lower die is divided into an outside portion having an inside surface whose outlook is coincident with that of the inside surface of the press portion, and an inside portion located so as to be adjacent to and extend inwardly from the outer portion, and the outside portion and the inside portion are designed so as to be relatively movable in up-and-down direction.

Abstract: After a semiconductor integrated circuit apparatus is put on a print wiring board so as to place each pad of the semiconductor integrated circuit apparatus on the corresponding lead terminal of the print wiring board and to place the semiconductor integrated circuit apparatus on a through hole of the print wiring board, a fixing portion of a suction and drawing unit is pressed into the through hole, and a suction portion of the suction and drawing unit makes contact with the lower surface of the semiconductor integrated circuit apparatus. Thereafter, when the pressure of gas existing in the inside of the suction and drawing unit is reduced, the suction portion suctions the semiconductor integrated circuit apparatus and draws the semiconductor integrated circuit apparatus toward the print wiring board to press each pad of the semiconductor integrated circuit apparatus on the corresponding lead terminal of the print wiring board.

Abstract: In a semiconductor device having a heat radiation plate, the tips of inner leads connected to a semiconductor chip have a lead width w and a lead thickness t, the width being less than the thickness. The inner leads are secured to the heat radiation plate. Fastening the inner leads to the heat radiation plate supports the latter and eliminates the need for suspending leads. A lead pitch p, the lead width w and lead thickness t of the inner lead tips connected to the semiconductor chip have the relations of w<t and p≦1.2t, with the inner leads secured to the heat radiation plate. The heat radiation plate has slits made therein to form radially shaped heat propagation paths between a semiconductor chip mounting area and the inner leads.

Abstract: The present invention relates to a die pad of a leadframe. The die pad is used for receiving a die. The die and the die pad are connected by a solder paste. The die pad comprises a plurality of slots. The slots extend through the die pad. A restrictive region is defined by the slots such that the solder paste is restricted within the restrictive region. The die is positioned on the restrictive region. Because of the cohesion of the solder paste, the solder paste does not flow into the slots. Therefore, the solder paste does not flow and expand everywhere during the heating process. The solder paste is restricted within the restrictive region so that the die on the solder paste does not drift so as to increase the packaging quality.

Abstract: A package is provided for surface mounting a semiconductor device to a board such that a first pad of the semiconductor device is operatively connected to a second pad on the board. The package includes a paddle having a front side and a back side with the front side being mated to the semiconductor device and at least partially enclosed in an encapsulant material and the backside being substantially exposed. In addition, the package has a region of the paddle that is at least partially isolated by the encapsulant material and aligned with the second pad an interconnect connected to the first pad of the semiconductor device and bonded to the region such that a conductive path is formed with the first pad, the region and the second pad when the backside is mated with the board.

Abstract: A semiconductor device includes a heat sink adjacent to a die. A dam is positioned at the peripheral edges of the heat sink. During a transfer molding process, the dam serves two purposes. First, the dam prevents damage to the mold. Second, the dam prevents encapsulant packaging compound material from flowing onto the heat sink. The dam may be a gasket. The dam may also be a burr created by, for example, stamping the bottom of the heat sink. The dam may include copper, polyamides, and leadlock tape. The dam may be permanently connected to the heat sink for removal following packaging. The dam may be removed mechanically, through the use of heat, or during an electrolytic deflash cycle.

Abstract: A semiconductor device in which a lead frame having inner connecting portions and outer connecting portions, a semiconductor chip having electrodes on the surface thereof, and metal wires for electrically connecting electrodes on the semiconductor chip and the inner connecting portions of the lead frame are sealed with a sealing resin. The bottom side of the sealing resin of the inner connecting portion is covered with an inner connecting portion sealing resin.

Abstract: A leadframe configuration for a semiconductor device has a die attach paddle with paddle support bars. In addition, clamp tabs extend outwardly from lesser supported locations of the paddle to underlie a conventional lead clamp. The clamp tabs are formed as an integral part of the paddle. Normal clamping during die attach and wire bonding operations prevents paddle movement and enhances integrity of the die bond and wire bonds.

Abstract: An integrated circuit chip package according to the present invention includes an integrated circuit chip that is mounted on a substrate by a reflow process and by a plurality of solder bumps. At least one standoff is located between the circuit chip and the substrate to maintain a distance between the circuit chip and the substrate during the reflow process. A mold compound is used for underfilling air gaps between the chip and the substrate. The integrated circuit chip package is formed by placing the chip and substrate within a mold cavity and pressing a transfer mold compound into the mold cavity. Air spaces between the integrated circuit chip and the substrate are underfilled by the mold compound as it is pressed in between the integrated circuit chip, the standoffs and the substrate. Air is allowed to escape from between the chip and the substrate during the underfilling through a vent which extends through the substrate.

Abstract: The present invention provides a packaged chip that includes at least one dam disposed between the chip and interposer, blocking an encapsulant flow path in the package formed by the assembly of the interposer and chip. In one preferred embodiment, the dam comprises a lead-like structure formed on the interposer that closes an encapsulant flow path in the package. The invention further provides a novel interposer that may be assembled with a chip into the novel packaged chip. Methods are also provided for making the packaged chip and the interposer.

Abstract: A method of manufacturing a leadless semiconductor chip package comprises the steps of: attaching a semiconductor die onto a die pad of a lead frame, wherein the lead frame comprises a plurality of leads arranged about the periphery of the die pad and each lead has a notch formed at the to-be-punched position thereof; wire bonding the inner ends of the leads to bonding pads on the semiconductor die; sucking a film against a lower part of a molding die; closing and clamping the molding die in a manner that the semiconductor die is positioned in a cavity of the molding die and the lead frame is disposed against the film; transferring a hardenable molding compound into the cavity; hardening the molding compound; opening the molding die to take out the molded product; and punching the molded product along the notches of the leads thereby making the singulation process more convenient and correct.

Abstract: A plurality of leads are arrayed around an island (1) to which a semiconductor chip (3) is bonded. A plurality of first wires (4) interconnects each electrode terminal of the semiconductor chip (3) and each of the plurality of leads (2), while a second wire (4b) electrically connects a ground terminal of the semiconductor chip (3) with the island (1). This island (1) is so formed that a slit (1c) may be interposed between a wire bonding portion (1b) and a die pad portion (1a). In this configuration, the island and the leads are covered by a resin package (6) in such a manner that their back faces may be exposed from this package. As a result, even in a QFN type resin-packaged semiconductor device in which the back faces of the island and the leads are exposed for direct soldering at the time of mounting, the wire bonded to the island can be prevented from being disconnected or cut off, thus making that resin-packaged semiconductor device more stable in quality.

Abstract: A lead frame and a semiconductor device fabricated by using the same. The lead frame comprises: first and second band shaped members disposed parallel to each other; a plurality of island portions for mounting semiconductor pellets thereon having first end portions connected to the first band shaped member; coupling strip each provided for one of the island portions whose first end portion connects to a second end portion of each of the island portions and whose second end portion connects to the second band shaped member. The lead frame further comprises at least one electrode portion for each of the island portions and electrically coupled with a corresponding electrode of the semiconductor pellet. The at least one electrode portion is disposed between each of the island portions and the second band shaped member, a first end portion thereof is connected to the second band shaped member, and a second end portion thereof is opposed to the second end portion of each of the island portions.

Abstract: There is provided an I/O pin by which an MCM is positively prevented from being damaged by solder flowing from the fore end to the base of the I/O pin when the I/O pin is soldered in the case of mounting the MCM. An I/O pin used for an electrical connection is provided, one end of which is perpendicularly fixed to an MCM and the other end of which is soldered to a predetermined position on the mother board in the case of mounting the MCM on the mother board. In an intermediate portion of the I/O pin, there is formed a solder dam composed of a plated layer of Ni of low solder wettability, a layer of highly heat-resistant resin or a layer of high-temperature solder.

Abstract: An integrated circuit package which has an integrated circuit mounted to a substrate. The package includes a plurality of bond wires that couple bond pads of the integrated circuit to corresponding bond pads of the substrate. The bond wires may have an essentially uniform bond wire density about an entire outer perimeter of the integrated circuit including the corners of the circuit. The integrated circuit and bond wires are enclosed by an injected molded plastic housing. It is believed that the bond wires located at the corners impede the flow of the injected plastic and reduce the amount of wire sweep in the package from packages in the prior art. Additionally, the essentially uniform bond wire density may create a uniform fluidic resistance to the injected plastic. The uniform resistance also reduces the amount of wire sweep from packages in the prior art. The bond wires located at the corners may be dummy wires that are not electrically connected to the integrated circuit.

Abstract: A method of manufacturing a solid-state image pickup device including the steps of preparing a package including a housing section to house a solid-state image pickup element chip and an opening section in an upper section thereof, sporadically applying adhesive with a predetermined thickness on a bottom surface of the housing section, moving the solid-state image pickup element toward the housing section, an upper surface of the package and an upper surface of the element each having desired parallelism with respect to a predetermined reference surface with high precision, bringing a rear surface of the solid-state image pickup element into contact with the adhesive and stopping the movement of the element before the element comes into contact with the bottom surface of the housing section, curing the adhesive while the solid-state image pickup element is floating on the adhesive and fixing the element in the housing section.

Abstract: A leadframe comprising a downset formed adjacent to an edge of the leadframe so as to direct the molding compound to flow evenly inside the mold cavity. The downset has an upward slope extending from the edge of the frame and levels off with the rest of the frame at a first transition point. The upward slope facilitates the upward flow of the molding compound entering from a bottom gate. Likewise, the leadframe also directs flow in a top gated mold by reversing the orientation of the leadframe or by forming a reverse downset on the leadframe.

Abstract: A semiconductor package containing a silicon chip, a lead frame, a plurality of conductive wires, a heat sink and some packaging material. Both the silicon chip and the heat sink are mounted on the lead frame, and the silicon chip is located between the heat sink and the lead frame. The silicon chip is electrically connected to some contact points on the lead frame by a plurality of conductive wires, and the space between the heat sink and the lead frame is filled with packaging material. The heat sink has a narrow pinhole gate and a plurality of conical positioning holes. The pinhole gate is formed in the middle of the heat sink so that packaging material can enter the mold cavity in the middle through the roof of the package. Both the pinhole gate and the positioning holes are filled with packaging material.

Abstract: A packaged semiconductor device having high reliability which can solve the problems that many pins are to be loaded, that is, that the density of the electrical wirings becomes high, and the heat loss properties thereof decrease, and which can discharge the high pressure moisture in a gas state from the inside thereof to the exterior, comprising: a strengthening ring arranged around a semiconductor chip comprising a process type electrode on an isolated substrate; a resin to fill spaces between the semiconductor chip and the isolated substrate; and a cap on the semiconductor chip and the strengthening ring, wherein at least one vent is formed perpendicular to the direction of the thickness of the semiconductor chip.

Abstract: A mounting substrate and related mounting method for a semiconductor device. The mounting substrate includes a mounting area to which the semiconductor device is to be mounted and fixed by an adhesive, a peripheral channel formed in the mounting substrate so as to surround the mounting area, and radial channels extending radially from the center towards the periphery of the mounting area. An adhesive is applied at least to either the center of the mounting surface of the semiconductor device or the center of the mounting area of the mounting substrate. The semiconductor device is placed on the mounting area and the adhesive flows outwardly along the radial channels, with the adhesive then being cured. The peripheral channel provides control of the amount of adhesive which flows to the outside of the semiconductor device and the mounting area. The adhesive overflow can be adjusted such that adhesive climbs up the sides of the semiconductor device but not reach the upper surface of the device.

Abstract: To prevent the contact of adjacent wires when a molding resin for forming the external shape of a semiconductor package is poured. The semiconductor device of the present invention is equipped with a semiconductor chip 13 that has a row of electrode pads 13a along the periphery of the principal plane, wires 14 that extend from each of the electrode pads 13a, a molding resin package material 15 that covers at least the above-mentioned semiconductor chip 13 and the wires 14 and that forms the external shape of the semiconductor device, and dam members that are arranged between the two closest of the above-mentioned wires 14a and 14b, which are arranged so that the corners of the above-mentioned semiconductor chip are inserted in between the wires, that is, the dummy wires 17.

Abstract: A semiconductor device includes a heat sink adjacent to a die. A dam is positioned at the peripheral edges of the heat sink. During a transfer molding process, the dam serves two purposes. First, the dam prevents damage to the mold. Second, the dam prevents encapsulant packaging compound material from flowing onto the heat sink. The dam may be a gasket. The dam may also be a burr created by, for example, stamping the bottom of the heat sink. The dam may include copper, polyamides, and leadlock tape. The dam may be permanently connected to the heat sink for removal following packaging. The dam may be removed mechanically, through the use of heat, or during an electrolytic deflash cycle.

Abstract: An universal lead frame type of Quad Flat Non-Lead package of semiconductor comprises a chip, a plurality of leads, a heat sink, and a molding compound. The leads are disposed at the periphery of the chip. The chip has its back surface bonded to the top surface of the heat sink, and the periphery of the top surface of the heat sink has a plurality of projections. The bonding portion at the periphery on the bottom surface of the heat sink is bonded to the top surface of the leads. The protruded portion at the center of the bottom surface of the heat sink is disposed in the opening region such that the bottom surface of the heat sink and the bottom surface of the leads are coplaner. The bonding pads of the chip are electrically connected to the top surface of the leads by a plurality of bonding wires. The molding compound encapsulates the chip, the heat sink, the top surface of the leads, and the bonding wires while exposes the protruded portion of the heat sink.

Abstract: A structure and method are provided to allow a die to be packaged more uniformly and in parallel with a package by utilizing a lead frame having at least one cavity within the lead frame, thereby allowing excess die-attach epoxy can flow into the cavity or cavities and reducing the amount of contact surface area between the die and lead frame.

Abstract: A semiconductor packaging chip-supporting substrate of the present invention comprises an insulating supporting substrate, wiring provided on the substrate, and an insulating film provided on the wiring. The wiring each have i) an inner connection that connects to a semiconductor chip electrode and ii) a semiconductor chip-mounting region. An opening is also provided in the insulating supporting substrate at its part where each of the wiring is formed on the insulating supporting substrate, which is the part where an outer connection conducting to the inner connection is provided. The insulating film is formed at the part on which the semiconductor chip is mounted, covering the semiconductor chip-mounting region of the wiring.

Abstract: In a semiconductor device, a semiconductor chip is mounted on a planar substrate approximately at the center and a hollow cavity for housing the semiconductor chip is formed by laminating an annular ring member, annular adhesive tapes, and a heat spreader plate on the substrate. A slit is formed in the adhesive tape or the ring member to provide an air vent.

Abstract: The leadframe of the present invention comprises a supporting bar having the first terminals and the second terminals, wherein the first terminals are coupled to the separating portion of the leadframe and the second terminals are used to support the chip. A plurality of inner leads connected to the supporting bar. A plurality of external leads connected to the inner leads; Adhesive material, formed on the leadframe and used to attach the chip to the inner leads, wherein the area of adhesive material is smaller than that of said chip. A plurality of bonding wires is used to couple the chip to the leadframe. Finally, the chip is encapsulated with the molding compound to protect the chip and the bonding wires.

Abstract: A semiconductor package includes a semiconductor die mounted on an upper surface of a substrate. A number of wire bonds electrically connect between a number of bonding pads on the upper surface of the substrate and a number of bonding pads on an upper surface of the semiconductor die. A fixing portion surrounds the semiconductor die and covers a mediate portion of each wire bond. Encapsulating material is molded over the semiconductor die and the wire bonds to form an encapsulant. In an alternative embodiment, the fixing portion is provided on the upper surface of the substrate adjacent to a mold gate of the substrate where the wire sweeping is most likely to occur while molding. The fixing portion does not cover the semiconductor die to avoid thermal strain acting on the semiconductor die due to the different coefficients of thermal expansion between the fixing portion and the encapsulant.

Abstract: The present invention relates to electro optical devices with a reduced filter thinning on the edge pixels and a method for reducing the thinning of filter layers on the pixels closest to the edge of an electro optical device such as a photosensitive chip, as would be used, for example, in a full-color digital copier or scanner. A semiconductor wafer includes a main surface defining a plurality of chip areas and tab regions separated by grooves, wherein the chip areas include inner photosites, outer photosites and bonding pads. A plurality of dams are deposited over the main surface in the tab regions, and a clear layer is deposited over the main surface exclusive of the bonding pads. Alternatively, a clear layer is deposited over the main surface exclusive of the bonding pads, and a plurality of tabs is then deposited in the tab regions on the main surface.

Abstract: The power semiconductor component has a semiconductor body which is electrically supplied through a contact clip. A solder ball connects the semiconductor body to the contact clip. The contact clip has a meandering electrical supply to a solder land, into which the solder ball is inserted.

Abstract: A semiconductor device packaged in a plastic package provided with a semiconductor device chip, a plurality of leads each of which is bonded with each of the bonding pads of the semiconductor device chip, and a plastic mold packaging the semiconductor device chip bonded with the leads, allowing the leads to project themselves from the bottom surface thereof and to extend outward along the bottom surface thereof, wherein each of the leads has a horizontal shape in which the surface of the edge thereof is a half circle, a half ellipse or a half polygon convex toward the inward direction.

Abstract: A semiconductor device according to the invention of the present application includes a semiconductor chip having a plurality of electrodes provided on the surface thereof, at least one inner lead fixed to the surface of the semiconductor chip with an insulating layer interposed therebetween, a shielding plate placed in the neighborhood of a first side of the semiconductor chip, and a sealing resin for sealing the semiconductor chip, the inner lead and the shielding plate. The sealing resin is injected from the direction of a second side of the semiconductor chip, which is opposite to the first side of the semiconductor chip Therefore, the flow of the resin is controlled upon sealing so that the resin is uniformly injected.

Abstract: A reinforcing ring surrounding a semiconductor element connected electrically to respective interconnecting portions through electrodes is provided as one body through suspending portions. A film circuit is produced by forming a ring in place of an outer lead for instance by applying a lead frame forming technique in which a laminate of three layers or more is used as a base, an inner lead is formed on one side and an outer lead is formed by a surface layer on another side. In this manner, in a film circuit composed of an insulating film and a plurality of interconnecting portions (leads) electrically connecting between electrodes and other electronic components of a semiconductor element on at least one principal plane of the insulating film, it is made possible to align a ring surrounding a semiconductor element with respect to the semiconductor element only by placing the film circuit on the semiconductor element, and in its turn to reduce assembly mandays of a semiconductor device.

Abstract: To provide a substantially flat surface, a semiconductor device includes a first insulating film formed on one main surface of a semiconductor substrate, and a first lead layer buried in the first insulating film. A first bonding pad is formed in contact with the first lead layer. A second insulating film is formed on the first insulating film and the first lead layer. A second lead layer is formed on the second insulating film, and a second bonding pad includes part of the second lead layer. The height of the surface of the second lead layer is substantially equal to the height of the surface of the first bonding pad respectively from the one main surface of the semiconductor substrate.

Abstract: A leadframe for connection to a semiconductor chip, in particular a metal leadframe, includes a plurality of lead prongs and at least two raised lead surfaces. When a semiconductor module that includes the leadframe and a semiconductor chip is sheathed with plastic, the raised lead surfaces assure a uniform flow of a plastic composition in a mold cavity and thus prevent air from becoming trapped in a plastic package. The lead surfaces are preferably created by folding over tabs in the leadframe. The invention also relates to preliminary stages of the leadframe and to semiconductor components that contain the leadframe of the invention.

Abstract: A protection device for integrated circuits which prevents inadvertent damage caused by over-voltage power surges. The protection device comprising an insulating carrier having a ground plane thereon and a plurality of conductive pads around a periphery thereof. The plurality of conductive pads are spaced from the ground plane with a precision gap therebetween. When the protection device is placed over the integrated circuit chip, the plurality of conductive pads are coupled to the bonding pads of the integrated circuit and at least one of the conductive pads is coupled to the ground plane.

Abstract: The invention concerns a device comprising a first substrate and a second substrate intended to form a micro-system such as a sensor, at least one of the substrates being able to include electronic circuit components. The invention is characterised in that a layer of polymer is interposed between the first and the second substrate, in that the polymer layer includes at least one cavity which extends from the first to the second substrate and in that solder attaching means are provided in the cavity, said solder means assuring a traction resistant mechanical connection between the two substrates.

Abstract: A printed circuit board (PCB) for use in chip-on-board (COB) packages reduces failures due to warping of the COB packages. The PCB includes a board body having a upper surface and a lower surface, a chip bonding area on the upper surface for attaching a semiconductor device, and a plurality of conductors in a circuit pattern on the upper surface outside the chip bonding area, for electrical connection to the semiconductor device using a plurality of bonding wires. An encapsulation region encloses the chip bonding area, the bonding wires, a portion of the plurality of conductors, and a portion of the upper surface. The board includes external contacts on the lower surface for electrical connections to an external electrical appliance, and via holes through the board body for electrically connecting the plurality of conductors in the circuit pattern to the external contacts.

Abstract: A semiconductor package provided with a reinforcing plate on the side of the lead joined face of which a chip housing concave portion is formed, a semiconductor chip housed and fixed in the chip housing concave portion of this reinforcing plate, a plurality of leads joined and held on the lead joined face of the reinforcing plate, the inner lead section of which is joined to the semiconductor chip via a bump and in the outer lead section of which a protruded electrode is formed, a solder resist film formed on the lead except the bump formed area and the electrode formed area of this lead and a polyimide film formed on the side of the inner lead section of the lead on the solder resist film and the manufacturing method are disclosed and hereby, the quality of the semiconductor package with ultra-multipin structure is stabilized.

Abstract: A lead frame and a semiconductor chip package includes supporters on a lead frame paddle and tiebars using the same for preventing undesired paddle bending which may occur due to the pressure of an epoxy molding compound during the molding process. The supports also allow improved heat dissipation during the molding process of the semiconductor chip package and mounting process of the package onto a printed circuit board.

Abstract: A tape carrier for TAB includes a base material having an insulating property and an elongated shape. The base material has peripheral edges defining an opening for disposing an integrated circuit component. A first pair of portions of the peripheral edges face each other, and a second pair of portions of the peripheral edges face each other. A plurality of connection leads extend from the first pair of portions into the opening. A plurality of dummy leads extend from the second pair of portions into the opening.

Abstract: A surface mount semiconductor package employs locking elements for locking a plastic housing to a metal pad on which a semiconductor device is mounted. The package includes terminals having elongated crushable beads on their side surfaces adjacent the portions of the terminals just outside the plastic housing. The beads are crushed inwardly by a molding tool when it closes to provide a seal which prevents the molding plastic from bleeding out and over the sides of the terminals which extend beyond the housing and which could interfere with solder connection to the terminals.

Abstract: The invention relates to a single piece leadframe that can be used in current semiconductor device production. The leadframe has a plurality of segments in a horizontal plane, a chip mount pad in a different horizontal plane, and another plurality of segments connecting said chip mount pad with said leadframe. The latter plurality of segments has a geometry designed so as to tolerate bending and stretching beyond the limit of simple elongation based upon the inherent material characteristics. The chip mount pad of said leadframe provides direct thermal contact to an external heat conductor or heat sink by being designed so as to extend through the encapsulating package. The exposed chip pad can also be used electrically as a ground connection.

Abstract: A semiconductor packaging chip-supporting substrate of the present invention comprises an insulating supporting substrate, wiring provided on the substrate, and an insulating film provided on the wiring. The wiring each have i) an inner connection that connects to a semiconductor chip electrode and ii) a semiconductor chip-mounting region. An opening is also provided in the insulating supporting a substrate at its part where each of the wiring is formed on the insulating supporting substrate, which is the part where an outer connection conducting to the inner connection is provided. The insulating film is formed at the part on which the semiconductor chip is mounted, covering the semiconductor chip-mounting region of the wiring.

Abstract: In order that popcorning and delamination resulting from moisture vapor in a semiconductor package may be prevented, a vent hole is formed in a die-bonding area of a plastic substrate so as to extend vertically through the substrate. An upper open end of the vent hole is covered with a solder resist film and a semiconductor chip is die-bonded on the solder resist film. In the die-bonding step, the solder resist film prevents an adhesive agent from flowing into the vent hole through the upper open end, so that gas permeability of the vent hole can be ensured. Furthermore, since the solder resist film has gas permeability, moisture vapor in the package is released outside through the vent hole and the solder resist film during a reflow heating.

Abstract: A semiconductor sensor is provided with a good temperature characteristic, the sensor being capable of preventing a pressure or acceleration detection characteristic from being affected by a change of the surrounding temperature. A semiconductor chip is provided approximately in the center of a die pad of a lead frame and detects a displacement amount corresponding to a pressure or an acceleration. The displacement amount is converted into an electric signal and output. A resin mold is formed so as to cover the semiconductor chip. A thermal-stress-relieving buffer ring is provided on the die pad so as to surround an external circumference of the semiconductor sensor chip thereby preventing stress caused by thermal expansion/contraction of the resin mold from being directly applied to the semiconductor chip from the side.

Abstract: A low-stress silicon-backed light valve package assembly that includes a matched coefficient of thermal expansion (CTE) substrate with a CTE no greater than 300% of the CTE of silicon, a silicon-backed light valve adhered to the matched CTE substrate by a soft adhesive layer, a flexible circuit adhered to the matched CTE substrate and electrically connected to the silicon-backed light valve, an encapsulant dam surrounding the silicon-backed light valve and a soft encapsulant layer filling the cavity defined by the encapsulant dam. Both the soft encapsulant layer and the soft adhesive layer have a Shore A hardness of less than 5. The combination of a soft encapsulant layer, soft adhesive layer and matched CTE substrate insure sufficiently low mechanical stress levels to avoid the presence of optical interference patterns in the light valve display.