With Dam Or Vent For Encapsulant Patents (Class 257/667)
  • Patent number: 5763942
    Abstract: There is provided a lead frame including an outer frame, a die pad on which a semiconductor device is to be mounted, a plurality of outer leads extending from the outer frame to the die pad, a dam bar connected at opposite ends thereof to the outer frame for connecting the outer leads to one another for prevention of resin overflow, and a support lead extending obliquely to the dam bar for connecting the die pad to the outer frame. The outer frame is formed beyond an end of the dam bar with an opening extending in a direction making an angle with a direction in which the dam bar longitudinally extends so that there is formed an elastically deformable portion between the opening and an end of the dam bar, the opening having a length covering at least a width of the dam bar.
    Type: Grant
    Filed: February 13, 1997
    Date of Patent: June 9, 1998
    Assignee: NEC Corporation
    Inventor: Yasuhiro Suzuki
  • Patent number: 5753969
    Abstract: A semiconductor chip having a plurality of electrodes on its surface is fixed onto a die pad. The leads are spaced away from the die pad and connected to the electrodes of the semiconductor chip by means of a TAB tape. The die pad is substantially equal in size to the insulation film of the TAB tape. The die pad has a plurality of resin circulating holes around the semiconductor chip. The resin circulating holes are arranged such that a fluid resin sufficiently flows into a narrow area between the TAB tape and die pad. On the die pad, portions each between adjacent resin circulating holes serves as heat conducting paths. The heat generated from the semiconductor chip is transmitted to the entire region of the die pad through the heat conducting paths and then radiated outside.
    Type: Grant
    Filed: August 14, 1996
    Date of Patent: May 19, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuhito Suzuya, Morihiko Ikemizu, Terunari Takano, Kenji Uehara, Akito Yoshida
  • Patent number: 5729050
    Abstract: A semiconductor package substrate and a ball grid array (BGA) semiconductor package using the same include a cavity formed in the substrate, anti-cracking bumpers on the inner substrate surface adjacent to the cavity and a plurality of holes and recesses in the substrate, whereby delamination and cracking which may occur during the credibility checkup can be prevented, thereby improving the package reliability.
    Type: Grant
    Filed: November 18, 1996
    Date of Patent: March 17, 1998
    Assignee: LG Semicon Co., Ltd.
    Inventor: Jin Sung Kim
  • Patent number: 5723899
    Abstract: A lead frame for semiconductor packages is disclosed. In the lead frame, some of the inner leads in the four sides are extended and provided with connection bars on their inside ends. Alternatively, diagonally arranged tie bars of the lead frame are extended and provided with a rectangular guide ring on their inside ends. The connection bar or guide ring functions as a dam for restricting possible overflow of adhesive, which adhesive is applied on the heat sink for bonding a semiconductor chip to the heat sink. The lead frame of the invention also prevents waste of expensive tape by letting the adhesive tape adhere only to the connection bars or to a given portion of the guide ring when mounting the lead frame to the heat sink and makes it possible higher integration of semiconductor chip by making connection bar and guide ring from the lead or the tie bar.
    Type: Grant
    Filed: August 29, 1995
    Date of Patent: March 3, 1998
    Assignees: Amkor Electronics, Inc., Anam Industrial Co., Ltd.
    Inventor: Won Sun Shin
  • Patent number: 5721450
    Abstract: An integrated circuit package (10) comprises a semiconductor die (14) having a top surface and a bottom surface, and a substrate (16) for receiving the semiconductor die. The substrate should have an aperture(s) (18) below the semiconductor die for providing moisture relief during temperature excursions. An adhesive (20) applied to the substrate allows for mounting the semiconductor die to the substrate. Then, the semiconductor die is wirebonded to the substrate. Finally, an encapsulant (12) for sealing the top surface of the semiconductor die is formed over the semiconductor die and portions of the substrate.
    Type: Grant
    Filed: June 12, 1995
    Date of Patent: February 24, 1998
    Assignee: Motorola, Inc.
    Inventor: Barry M. Miles
  • Patent number: 5714792
    Abstract: A semiconductor device (10) having a reduced die support area (24) includes a semiconductor die (11) having a plurality of bond pads (17) which are electrically coupled to a plurality of leads (16) by wire bonds (15). The die is supported solely by two cantilevered tie bars (20). Use of cantilevered tie bars decreases the total plastic-metal interface area in a plastic encapsulated device, thereby lessening the probability of internal delamination and package cracking. The cantilevered tie bars also permit a variety of die sizes to be used with the same leadframe design. Optionally, a power supply bar may be used to connect the two tie bars to provide an electrical bus for the device.
    Type: Grant
    Filed: September 30, 1994
    Date of Patent: February 3, 1998
    Assignee: Motorola, Inc.
    Inventor: Michael C. Przano
  • Patent number: 5708294
    Abstract: A lead frame has a frame section for carriage, a square die pad for mounting a semiconductor chip, and four suspension arms bridging the frame section and corners of the die pad. The die pad has a plurality of oblique slits therein extending parallel to one another and parallel to a diagonal line of the die pad passing first and second corners of the die pad. During encapsulation, resin is introduced from a gate of molding dies located at the first corner to a vent of the molding dies located at the second corner. The oblique slits enhances oblique resin-flow under the lower surface of the die pad during encapsulation of the semiconductor device, to thereby prevent a die pad shift, unfilling of the resin and resin void in the semiconductor device.
    Type: Grant
    Filed: February 26, 1996
    Date of Patent: January 13, 1998
    Assignee: NEC Corporation
    Inventor: Keiji Toriyama
  • Patent number: 5692296
    Abstract: The present invention provides a method for fabricating an integrated circuit package, as well the resulting integrated circuit package, which retains a heatsink in close communication with a mold cavity. This precludes any encapsulant from flowing between the heatsink and the inner surface of a mold cavity. As a consequence, the bottom of the heatsink is not encapsulated and is thus exposed. This is accomplished by including posts, attached to the leadframe assembly, which have the function of exerting a downward force on a leadframe assembly and, in turn, on the heatsink. Tie bars, which are non-functional parts of a leadframe assembly, can be utilized as posts by bending the posts into an upright position.
    Type: Grant
    Filed: July 29, 1996
    Date of Patent: December 2, 1997
    Assignee: LSI Logic Corporation
    Inventor: Patrick Variot
  • Patent number: 5689137
    Abstract: A method for transfer molding a standard electronic package and an apparatus resulting from such method. A seal is formed between a portion of the mold platens of the mold and a portion of a printed circuit board adjacent to electrical contacts along at least one side of the printed circuit board. After the apparatus is removed from the mold, a protective cap is placed over the electrical contacts.
    Type: Grant
    Filed: October 16, 1995
    Date of Patent: November 18, 1997
    Assignee: Hestia Technologies, Inc.
    Inventor: Patrick O. Weber
  • Patent number: 5684327
    Abstract: A lead frame for use in a resin-sealed type semiconductor device, comprising an outer frame, a plurality of leads supported by the outer frame, arranged side by side and each composed of an inner lead and an outer lead, a die pad arranged inside the outer frame and located so that the tips of the inner leads are close to the die pad and oppose the die pad, and a resin flow-control body. The resin flow-control body has been formed by extending a portion of the outer frame toward the die pad through a space formed in the outer frame. The body is designed to be placed in a cavity of a mold having a gate communicating with the cavity, with the space located between the gate and the cavity, in order to form a resin sealing body.
    Type: Grant
    Filed: September 13, 1995
    Date of Patent: November 4, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsutomu Nakazawa, Yumi Inoue
  • Patent number: 5652463
    Abstract: A printed wiring board with either a pin grid array, a ball grid array, a land grid array, etc. of electrical contacts is prepared with a heat sink in the usual manner. A passage is provided either in the printed wiring board or in the heat sink so that during the transfer molding process, fluid molding compound passes latitudinally under the heat sink into a cavity below the heat sink to encapsulate the package.
    Type: Grant
    Filed: May 26, 1995
    Date of Patent: July 29, 1997
    Assignee: Hestia Technologies, Inc.
    Inventors: Patrick O. Weber, Michael A. Brueggeman
  • Patent number: 5641987
    Abstract: An improved heat spreader having a specified structure suitable for commonly used in semiconductor packages regardless of pad sizes of the packages is disclosed. The heat spreader has a pad evenly provided with a plurality of first indentations. A plurality of outward broadening openings radially extend from the pad. A plurality of second indentations are provided on a leadframe facing surface of the heat spreader at the outside of the openings, so that the second indentations surround the openings. A plurality of small coupling sections radially extend on the edge of the heat spreader at every 90.degree. angle. The small coupling sections have their downward extending projections at their distal ends. A plurality of large coupling sections diagonally extend on the edge of the heat spreader. Each of the large coupling sections has a plurality of outward extending projections.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: June 24, 1997
    Assignees: Anam Industrial Co., Ltd., Amkor Electronics, Inc.
    Inventor: Myung Jun Lee
  • Patent number: 5623163
    Abstract: A leadframe for semiconductor derides having patterned die-mounting structures arranged along the longitudinal axis of the leadframe. Each of the structures contains a die pad for mounting a semiconductor device chip thereon, die pad supports for supporting the die pad, fingers for forming inner leads and outer leads, and tiebars for preventing leakage of a molding material during a molding process. At least one of the die pad supports has a first communication path through which a molding material flows from one side of the body to the other thereof. The molding material supplied into one side of the leadframe can flow to the other side thereof through not only the gaps between the die pad and the body but also the first communication path during a molding process, resulting in a small flow rate difference of the molding material. Failures such as visible voids and no fillings are not produced in the plastic-molding package.
    Type: Grant
    Filed: September 19, 1994
    Date of Patent: April 22, 1997
    Assignee: NEC Corporation
    Inventor: Atsuhiko Izumi
  • Patent number: 5596225
    Abstract: A leadframe for use in an integrated circuit package including at least one integrated circuit die attached to the leadframe and an encapsulant material surrounding the die and portions of the leadframe is herein disclosed. The leadframe includes a central portion having a plurality of perforations through the central portion adapted to allow the flow of the encapsulant material through the perforations during the molding process of the manufacture of the integrated circuit package thereby (i) preventing the flow of the encapsulant material from shifting the die attach pad during the manufacture of the package and (ii) providing anchoring for the encapsulant material to the leadframe to prevent delamination and cracking of the package.
    Type: Grant
    Filed: March 27, 1996
    Date of Patent: January 21, 1997
    Assignee: National Semiconductor Corporation
    Inventors: Ranjan J. Mathew, Hem P. Takiar
  • Patent number: 5594274
    Abstract: A distance between each two sides adjacent to a first portion X of the outer peripheral portion of an island portion 3 and the inner end of an inner lead portion 4 is set to d.sub.1 while the distance between each two sides adjacent to a second portion Y, which is diagonal to the first portion X, and the inner end of the inner lead portion 4 is set to d.sub.2 (<d.sub.1). The island portion 3 has a portion 2a for placing the semiconductor chip thereon and an overhang portion 3a attached to that portion. A semiconductor chip 2 is adhered on the island portion 3 of the lead frame 10, which is then attached in position within a mold. From a gate 21 a molten resin is injected into the cavity 23 in a diagonal direction of the square island portion, i.e. a direction from the first portion X toward the second portion Y.
    Type: Grant
    Filed: January 11, 1996
    Date of Patent: January 14, 1997
    Assignee: NEC Corporation
    Inventor: Kenji Suetaki
  • Patent number: 5585600
    Abstract: The present invention provides a method for forming an improved lead-on chip semiconductor module and an improved module of this type. In a lead-on chip semiconductor device, a semiconductor chip which has a major surface having input and output bonding pads thereon, is secured to a lead frame having a plurality of leads adjacent the bonding pads by means of bonding wires connecting a respective one of the leads to a pad on the chip. A coating of dielectric material having a Young's modulus in the range of about 10 psi to about 500 psi is disposed around the entire length of each of the wires and over the pads and over the portion of the respective leads to which the wires are connected to act as a stress buffer. This material preferably has a T.sub.g of at least as low as -40.degree. C. Also preferably this package is encapsulated with conventional encapsulant.
    Type: Grant
    Filed: September 2, 1993
    Date of Patent: December 17, 1996
    Assignee: International Business Machines Corporation
    Inventors: Francis E. Froebel, David L. Gardell, Gary H. Irish, Mohammed S. Shaikh
  • Patent number: 5583370
    Abstract: A semiconductor device (42) has a protective containment housing (44) around the edges (24) of the die (12) to protect the die. A plurality of leads (30) are TAB bonded to the die's active surface (18). The containment housing is attached around the die such that a portion of the inner sidewalls of the housing contacts the edges of the die to seal the edges. The top edge of the containment housing acts as a dam to prevent encapsulant (14') overflowing down the die edges and to the die's inactive surface (28). Various embodiments of the containment housing are possible.
    Type: Grant
    Filed: August 11, 1995
    Date of Patent: December 10, 1996
    Assignee: Motorola Inc.
    Inventors: Leo M. Higgins, III, John C. Gentile
  • Patent number: 5539251
    Abstract: A "leads over chip" lead frame design is disclosed which can be used with a conventional die having leads located at the periphery. The inventive design uses an elongated tie bar which extends from one side of the lead frame to the other, across the die. The die is attached to the bottom of the tie bar, then the bond pads are wire bonded to the lead fingers. The lead fingers of the inventive lead frame do not extend over the top of the die, but are positioned in close proximity to allow for short bond wires. The die and a portion of the lead fingers are encapsulated, and the tie bars are severed to separate them from the lead frame. The invention allows the advantages of a leads over die configuration with a conventional die having bond pads located at the periphery. Therefor, a single die can be manufactured which can be used either with the inventive lead frame for a plastic package, or with a ceramic package.
    Type: Grant
    Filed: February 17, 1995
    Date of Patent: July 23, 1996
    Assignee: Micron Technology, Inc.
    Inventors: Robert E. Iverson, Walter L. Moden
  • Patent number: 5530278
    Abstract: In dicing of semiconductor chips from a wafer and mounting of the chips in an apparatus, techniques ensure the integrity of bonding pads and wire bonds in the dicing of individual chips and the connection of wire bonds to the chips. The wire bonds in the undiced chips are each connected to a probe pad disposed in an inter-chip area on the wafer, and this probe pad is used to accept probe pins which may otherwise damage the bonding pads on the chips themselves. In the dicing step, the probe pads are obliterated by the cutting blade. A polyimide dam disposes adjacent the bonding pads restricts the migration of liquid encapsulant securing the wire bonds to the bonding pads.
    Type: Grant
    Filed: April 24, 1995
    Date of Patent: June 25, 1996
    Assignee: Xerox Corporation
    Inventors: Josef E. Jedicka, Brian T. Ormond
  • Patent number: 5517056
    Abstract: A leadframe (30) having a novel resin injecting area (44) is disclosed to facilitate and control the removal of a molded gate (18) prior to excising a semiconductor device(70) from a carrier ring (14). The carrier ring has a corner which is on a diagonal with a corner of the package body (12) to form the resin injecting area. The resin injecting area of the leadframe has a hole (48) and an extension bar (50) extending from the hole to connect to a tie bar (36), which supports a die pad (32), inside the package body. The hole in the leadframe is designed for retaining a molded gate. The extension bar is designed to make the removal of a portion of a molded gate easier and more controllable. The semiconductor device can be shipped in the carrier ring with a portion of the molded gate already removed.
    Type: Grant
    Filed: September 30, 1993
    Date of Patent: May 14, 1996
    Assignee: Motorola, Inc.
    Inventors: Charles G. Bigler, Alan H. Woosley, Michael B. McShane
  • Patent number: 5486722
    Abstract: A lead frame in which a bulgy portion is disposed to each of inner leads or outer leads at a position corresponding to a mold line, whereby a lead gap in the portion is defined as less than 0.15 mm.The lead frame has such a shape as causing less resin leakage upon applying resin molding to a packaging main body upon preparing an IC plastic package. This enables to improve the yield in preparing the IC plastic package and reduce the manufacturing cost.
    Type: Grant
    Filed: May 3, 1994
    Date of Patent: January 23, 1996
    Assignee: Sumitomo Metal Mining Company, Limited
    Inventors: Naohumi Sato, Yasuhiro Yanagisawa
  • Patent number: 5479051
    Abstract: A semiconductor device includes at least a first semiconductor chip and a second semiconductor chip each having a first surface and a second surface. The second surface of the first semiconductor chip confronts the first surface of the second semiconductor chip. Additionally, the semiconductor device includes a plurality of leads having inner portions and outer portions, where the inner portions of the leads are electrically coupled to selected portions on one of the first and second surfaces of each of the first and second semiconductor chips. An insulator is interposed between the second surface of the first semiconductor chip and the first surface of the second semiconductor chip at portions other than the selected portions. Further, a resin package encapsulates the first and second semiconductor chips so that the outer portions of the leads project outside the resin package.
    Type: Grant
    Filed: September 24, 1993
    Date of Patent: December 26, 1995
    Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics Limited
    Inventors: Masaki Waki, Tosiyuki Honda, Yukio Gomi
  • Patent number: 5473189
    Abstract: A lead frame for a semiconductor integrated circuit has a chip mounting section for carrying a semiconductor chip and a peripheral section where a plurality of outer leads are juxtaposed with each other. The semiconductor chip will be sealed by a sealing resin when mounted on said chip mounting section. The outer leads extend outwardly from the chip mounting section and are adapted to electrically connected with the semiconductor ship mounted. Each outer lead has a first offset portion which is spaced more from a first adjacent outer lead on one side thereof than from a second adjacent outer lead on the other side thereof and a second offset portion which is spaced more from the second adjacent outer lead than from the first adjacent outer lead. The first and second offset portions of each outer lead is arranged in a staggered pattern.
    Type: Grant
    Filed: October 4, 1994
    Date of Patent: December 5, 1995
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Hiroyuki Nakanishi
  • Patent number: 5459103
    Abstract: This invention relates to a process for strengthening the adhesive bond between a lead frame and a plastic mold compound (350). The process involves plating the lead frame with a copper strike and selectively exposing the copper strike to an oxidizing agent to form a layer of cupric oxide (CuO) (318). Such lead frames are fitted with chips (324) and then encapsulated in the plastic mold compound (350), whereby the adhesive bond forms directly between the layer of CuO (318) and the plastic mold compound (350). A lead frame produced by this process may include a plurality of leads (310) having lead ends (312) and lead fingers (314) and a die pad (320) having a layer of CuO (318). The die pad (320) is encased by a plastic mold compound (350) which forms an adhesive bond directly with the layer of CuO (318). This layer (318) may have a thickness in a range of about 5 to 50.mu. inches (12.7 to 127 .mu.cm). Lead ends (312 ) and lead fingers (314) may be spot-plated with silver or palladium.
    Type: Grant
    Filed: April 18, 1994
    Date of Patent: October 17, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Harold T. Kelleher, David W. West
  • Patent number: 5457341
    Abstract: A method of making an integrated circuit (IC) device comprises the steps of providing (300) at least one lead frame (10) comprising a plurality of leads (14), laminating (302) the lead frame (10) with a photoresist, exposing (304) a portion of the photoresist to impose a pattern on the photoresist (10), and developing (306) the photoresist on lead frame (10), such that the photoresist produces a pair of strips and forms non-electrically conductive bonds (30, 32) between leads (14). Further, an IC device comprises a plurality of leads (14) extending from a lead frame (10). The leads (14) comprise an inner lead portion (26), a middle lead portion (27) and an outer lead portion (28). A photoresist is overlaid onto the leads (14).
    Type: Grant
    Filed: October 11, 1994
    Date of Patent: October 10, 1995
    Assignee: Texas Instruments Incorporated
    Inventor: David W. West
  • Patent number: 5455200
    Abstract: A semiconductor device (10) has a lead-on-chip (LOC) configuration. Leads (24) of the device have central portions (36) which are electrically coupled to peripheral bond pads (14) by conductive wires (30). Inner portions (38) of the leads extend from the central portions toward centerline A--A for improved adhesion and to provide an internal clamping area (41) which stabilizes the leads during wire bonding. In one embodiment, tie bar (22) of leadframe (16) is used to distribute power across semiconductor chip (12). The leadframe may also include chip alignment features (50) and tape alignment features (52) to align chip (12) and insulating tape (18) to the leadframe, respectively.
    Type: Grant
    Filed: July 27, 1993
    Date of Patent: October 3, 1995
    Assignee: Motorola, Inc.
    Inventors: Charles G. Bigler, James J. Casto, Michael B. McShane, David D. Afshar
  • Patent number: 5440169
    Abstract: A resin-packaged semiconductor device having a semiconductor element mounted on a first surface of a mounting pad. The mounting pad has an edge molded in a frame-shaped portion of a molding material. A second surface of the mounting pad has a central portion that is not included in the edge of the mounting pad and that is not covered with the molding material, the central portion of the second surface being exposed at the outside of the device. The thickness of the molding material in the frame-shaped portion and on the second surface of the mounting pad can be readily reduced to reduce the thickness of the device. Since the molding material does not cover the entire second surface, molding characteristics as well as heat radiation characteristics are improved.
    Type: Grant
    Filed: January 5, 1994
    Date of Patent: August 8, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshihiro Tomita, Shunichi Abe
  • Patent number: 5424577
    Abstract: A lead frame for semiconductor devices which does not require tie bar cutting in the manufacture of semiconductor devices includes a base lead frame having no tie bars and a dummy lead frame having dummy leads filling gaps between outer lead portions of the leads when the dummy lead frame is mounted on the base lead frame. Instead of tie bars, the dummy leads reinforce the leads and also stop molten sealing resin from flowing into the gaps between the outer lead portions during resin molding.
    Type: Grant
    Filed: March 30, 1994
    Date of Patent: June 13, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasuhito Suzuki, Kazunari Michii
  • Patent number: 5422163
    Abstract: A flexible substrate to be used for assemblage of a semiconductor chip having connecting points to be electrically connected to an external side, comprises a base film unit made of a flexible synthetic resin and including a mounting portion for mounting thereon a semiconductor chip, groups of conductive leads formed on a surface of the base film unit, each lead group including a plurality of the leads formed so as to extend from respective positions in the mounting portion corresponding to the connecting points of the semiconductor chip as mounted in the mounting portion to selected positions on the base film unit, and a plurality of projections each formed at an area between adjacent two of the lead groups on the surface of the base film unit and having a height substantially equal to the height of the leads of the lead group.
    Type: Grant
    Filed: December 10, 1993
    Date of Patent: June 6, 1995
    Assignee: Nippon Steel Corporation
    Inventors: Tadashi Kamiyama, Yoshiaki Emoto
  • Patent number: 5414293
    Abstract: Encapsulation of semiconductor light emitting diodes, in particular laser diodes, characterized in that a gap is formed in an encapsulant, which is positioned in front of the light emitting facet of the diode, the gap preventing the encapsulant from adhering to the light emitting facet.
    Type: Grant
    Filed: April 19, 1993
    Date of Patent: May 9, 1995
    Assignee: International Business Machines Corporation
    Inventor: Ronald F. Broom
  • Patent number: 5371044
    Abstract: A molding method in which a control plate having a size which is equal to or larger than the width of the outlet port of a supply passage are disposed in a cavity adjacent to the resin supply passage of a mold and thereby, the resin molding can be effected substantially equally at upper and lower sides of the insert comprising a semiconductor device and a lead.
    Type: Grant
    Filed: April 30, 1992
    Date of Patent: December 6, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Isamu Yoshida, Junichi Saeki, Shigeharu Tsunoda, Kunihiko Nishi, Ichiro Anjoh, Kenichi Imura, Toshihiro Yasuhara, Junichi Arita, Kazuhiro Sugino
  • Patent number: 5343072
    Abstract: A leadframe includes a first longitudinal side band, a second longitudinal side band integrally connected to the first band by transverse sectioning bars spaced longitudinally of the leadframe, a plurality of first leads located closer to the first side band between the respective sectioning bars, and a plurality of second leads integrally connected to the second side band between the respective sectioning bars. The first leads are integrally connected to the respective sectioning bars only via twistably slenderized segments. Each first lead can be turned over toward a corresponding second lead by torsioning the twistable segments.
    Type: Grant
    Filed: November 16, 1992
    Date of Patent: August 30, 1994
    Assignee: Rohm Co., Ltd.
    Inventors: Hiroshi Imai, Tadashi Murakami, Tetsuya Mimura, Masao Yamamoto, Yuji Kosumi, Masashi Asai, Yasunori Aoki
  • Patent number: 5327104
    Abstract: A flat package piezoelectric oscillator, sealed with resin, and having leads or terminals includes an IC chip mounted on one side of an island portion of a lead frame, and a piezoelectric oscillator element mounted on an opposite side of the island portion. The resin package of the oscillator has at least one hole through one of opposite surfaces of the package. An injection hole for resin injection is provided along a diagonal line extending between diametrically opposed corners of the resin package, and a cylindrical case of the piezoelectric crystal oscillator element is located such that its longitudinal axis is aligned with the diagonal line to within a range from -45.degree. to +45.degree.. The connection portions of lead terminals for the piezoelectric oscillator element and the pads of the IC chip are located adjacent to the diagonal line. The fabrication of the piezoelectric crystal oscillator is completed by sealing the above described structure with resin.
    Type: Grant
    Filed: October 14, 1992
    Date of Patent: July 5, 1994
    Assignee: Seiko Epson Corporation
    Inventor: Masayuki Kikushima
  • Patent number: 5317189
    Abstract: An axial lead frame including two side rails arranged opposite to each other and plural pairs of lead terminals separated from each other and located opposite to each other, in which a longer lead terminal and a shorter lead terminal of a pair of the lead terminals are alternately arranged to extend in parallel with each other in the equally spaced relationship between both side rails. And, a buffer member is formed at the substantially central part between both the side rails so as to allow the longer lead terminals extending from both the side rails toward the buffer member to be jointed to each other along the buffer member. A die pad is die-bonded to the foremost end of each of the longer lead terminal, while a pad is placed at the foremost end of each of the shorter lead terminal. Dam bars are bridged between adjacent lead terminals in order to prevent molten resin from flowing out during molding operation.
    Type: Grant
    Filed: March 9, 1993
    Date of Patent: May 31, 1994
    Assignee: Rohm Co., Ltd.
    Inventors: Kazuyoshi Tsuji, Eiji Shimazaki
  • Patent number: 5311060
    Abstract: A first, lower heat sink disposed immediately below and closely adjacent a semiconductor chip (die) in a semiconductor chip assembly is disclosed. The lower heat sink is a flat metallic or ceramic shim. A second, upper heat sink disposed immediately above and closely adjacent the top surface of the semiconductor device is disclosed. The upper heat sink may have a portion in contact with a passivation layer over the top surface of the semiconductor die (device). The second heat sink preferably has a flat surface forming an exterior surface of the semiconductor device assembly. In one embodiment, the second heat sink has pedestals resting atop a plastic layer in a tape-like structure within the semiconductor chip assembly. In a second embodiment, the second heat sink includes an add-on portion that is external to the semiconductor chip assembly. The first heat sink is particularly well-suited to applications wherein the semiconductor chip assembly is mounted to a thermal mass.
    Type: Grant
    Filed: July 28, 1992
    Date of Patent: May 10, 1994
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, Mark Schneider, Edwin Fulcher
  • Patent number: 5304841
    Abstract: A lead frame for a rectangular flat package has dumb bars connecting the lead terminals and dam bar coupling portions at the corners of the frame in which the coupling portions are notched to permit the adjacent dam bars to have the same length as the other dam bars, permitting them to be cut away by the same punch. This arrangement permits an increase in the length of the nicked part of the corner of the resin body of the flat package, at which a gate for injection-molding of a resin is located, thereby avoiding chipping of the resin body when excess resin from the injection is removed.
    Type: Grant
    Filed: April 12, 1993
    Date of Patent: April 19, 1994
    Assignee: Rohm Co., Ltd.
    Inventor: Atsuhito Negoro
  • Patent number: 5302850
    Abstract: A semiconductor sealing mold for sealing a semiconductor element within a thermosetting resin is provided with resin inflow openings formed in oppositely and substantially symmetrically opposed relation to the active surface and back surface of a lead frame connected semiconductor element. As a result, the application of the molding process and method of encapsulation of the semiconductor element can be accomplished under conditions of uniformly applied pressure to opposite surfaces of the semiconductor element and extending outwardly in all radial directions from the center of the semiconductor element. Furthermore, since the bonding wires and lead frame leads are substantially aligned in the same radial directions from the center of the semiconductor element, damage does not occur to these wires or leads during the molding process.
    Type: Grant
    Filed: August 30, 1993
    Date of Patent: April 12, 1994
    Assignee: Seiko Epson Corporation
    Inventor: Akitoshi Hara
  • Patent number: 5296743
    Abstract: A method of making an integrated circuit package is disclosed herein along with the package itself, which package is encapsulated by plastic that is caused to flow in a given direction during the package's formation. The package itself includes an IC chip having an array of chip output/input terminals, and means for supporting the chip including an array of electrically conductive leads, all of which are provided for connection with the output/input terminals of the IC chip. In addition, the overall package includes bonding wires connecting the chip output/input terminals with respective ones of the leads such that each bonding wire extends in a direction that defines an acute angle of less than 45 degrees with the given flow direction of the plastic material used to encapsulate the IC chip, support means and bonding wires. In a preferred embodiment, at least a portion and most preferably substantially all of the bonding wires are substantially parallel with the given flow direction of the plastic material.
    Type: Grant
    Filed: May 7, 1993
    Date of Patent: March 22, 1994
    Assignee: National Semiconductor Corporation
    Inventors: Luu T. Nguyen, Hem P. Takiar
  • Patent number: 5294827
    Abstract: A thin semiconductor device (50) can be cost effectively manufactured using conventional wire bonding technology and stamped leadframes. A flagless leadframe (12) is utilized in one embodiment. A support tape (14) having a die support surface (20) is attached transversely to a plurality of leads (18) of the leadframe. A semiconductor die (16) is attached on its active surface to the die support surface such that the active surface is coplanar with the leadframe. Low loop wire bonds (24) electrically connect the die to the leadframe. A resin encapsulant package body (52) is molded around the active surface of the die, the wire bonds, and a portion of the leads. An inactive surface of the die is exposed for enhanced thermal dissipation in addition to enabling a thin package body. External lead configuration of the semiconductor device is not limited.
    Type: Grant
    Filed: December 14, 1992
    Date of Patent: March 15, 1994
    Assignee: Motorola, Inc.
    Inventor: Michael B. McShane
  • Patent number: 5293065
    Abstract: A lead frame (10) is connected to an integrated circuit (32) by adhesives. The lead frame (10) includes a mold gate (40) to provide for constant flow of resin (72) into the mold cavity (66) during encapsulation of the integrated circuit (32). The lead frame (10) also has an air vent (50) to direct air and any excess resin (74) from the mold cavity (66) to a dummy cavity (70).
    Type: Grant
    Filed: August 27, 1992
    Date of Patent: March 8, 1994
    Assignee: Texas Instruments, Incorporated
    Inventor: Min Y. Chan
  • Patent number: 5291060
    Abstract: A multi-layer lead frame is provided with a lead frame body made of a metal strip and having a plurality of inner leads including respective tips which define an opening. A power supply metal plane is adhered to the inner leads and a ground metal plane is adhered to the power supply metal plane by insulative adhesive layers. These metal planes are provided with first wire bonding areas and through holes in the vicinity thereof. A semiconductor device comprises such a multi-layer lead frame, a semiconductor chip mounted on a stage thereof, bonding-wires electrically connecting the chip to the areas, and a resin integrally molding the multi-layer lead frame, the chip, and the bonding-wires in such a manner that the through holes are filled with the resin.
    Type: Grant
    Filed: December 3, 1992
    Date of Patent: March 1, 1994
    Assignees: Shinko Electric Industries Co., Ltd., Intel Corp.
    Inventors: Mitsuharu Shimizu, Yoshiki Takeda, Hirofumi Fujii
  • Patent number: 5285104
    Abstract: A lead frame and a circuit board for mounting thereon a semiconductor element for encapsulating a semiconductor device by transfer molding comprising an electrically conductive lead portions connected to the frame portion and a bridge member connecting the lead portions together. Each lead portion is partially encapsulated by a mold resin and divided into inner and outer lead portions by the resin boundary. The electrically insulating and heat-resisting bridge member is disposed at a position corresponding to the outer surface of the mold resin and having a thickness at least equal to that of the lead portions. Therefore, the spaces between the lead portions are completely closed by the bridge member, so that no burr is formed between the leads and leads are mechanically supported while being electrically insulated from each other, whereby a fine pitch lead frame can easily realized. A semiconductor device in which the lead frame or the circuit board is used is also disclosed.
    Type: Grant
    Filed: September 29, 1992
    Date of Patent: February 8, 1994
    Assignee: Ibiden Co., Ltd.
    Inventors: Mitsuhiro Kondo, Osamu Watanabe
  • Patent number: 5283466
    Abstract: A lead frame for a semiconductor device provided with package suspension leads that have one end portion connected to an outer frame and that have the side of the other end portion extending into a resin encapsulation region, and island suspension leads that have one end portion connected to the side portion of the island that does not oppose the outer frame, and another end portion extending and connected to the outer frame in the direction of the side of the island so that a region of a depressed portion is obtained.
    Type: Grant
    Filed: September 27, 1991
    Date of Patent: February 1, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazunori Hayashi
  • Patent number: 5252783
    Abstract: A semiconductor package is provided having a die attach flag (12) with integral flanges (13) which prevent high pressure plastic encapsulant (18) from escaping or entering between the die attach flag (12) and a mold cavity plate (15) during encapsulation. The die attach flag (12) is held flush against the cavity plate (15) by the packing pressure of the encapsulant (18) during low pressure stages of the encapsulation process. Plastic flowing along the flange (13) solidifies more rapidly than plastic in the body of the semiconductor package, thereby damming plastic flow at the edges of the die attach flag (12) during high pressure stages of the encapsulation process.
    Type: Grant
    Filed: February 10, 1992
    Date of Patent: October 12, 1993
    Assignee: Motorola, Inc.
    Inventor: John Baird
  • Patent number: 5208467
    Abstract: A semiconductor device comprising a lead frame, a semiconductor chip on the lead frame, a wiring provided between the lead frame and the semiconductor chip, a silicon nitride film formed on the semiconductor chip, the wire, and the lead frame, and a mold formed from a plastic material to enclose the silicon nitride film therein and having a vent hole formed on the undersurface of the lead frame, so that the lead frame is partly exposed to the outside.
    Type: Grant
    Filed: January 14, 1991
    Date of Patent: May 4, 1993
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 5202577
    Abstract: A leadframe comprising a thin-walled portion that is formed in a dam bar portion or a portion that extends from the dam bar portion to a pair of inner leads which are adjacent thereto. By cutting the dam bar portion along the thin-walled portion, the stress that is imposed on a cutting punch is reduced. Thus, it is possible to extend the lifetime of the cutting punch and also to minimize the shear droop formed on the cut surface. The leadframe further has a thick-walled portion formed at the position where the thin-wall portion is formed. The thick-walled portion serves to support the thin-walled portion when the dam bar portion is cut off, thus preventing the dam bar portion from tilting. Accordingly, the dam bar cutting operation can be conducted stably without undesired movement of the dam bar portion, and the stress that is imposed on the leadframe can be controlled so as to be well balanced.
    Type: Grant
    Filed: February 6, 1991
    Date of Patent: April 13, 1993
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Kikuo Ichigi, Soichiro Shimamura, Masahiro Fuse
  • Patent number: 5175612
    Abstract: A first heat sink disposed immediately below and closely adjacent a semiconductor chip in a semiconductor chip assembly is disclosed. The heat sink is a flat metallic or ceramic shim. A second heat sink disposed immediately above and closely adjacent the semiconductor device is disclosed. The second heat sink preferably has a flat surface forming an exterior surface of the semiconductive device assembly . In one embodiment, the second heat sink has pedestals resting atop a plastic layer in a tape-like structure within the semiconductor chip assembly. In a second embodiment, the second heat sink includes an add-on portion that is external to the semiconductor chip assembly. The first heat sink is particularly well-suited to applications where the semiconductor chip assembly is mounted to a thermal mass. The second heat sink is particularly well-suited to applications where air cooling is available.
    Type: Grant
    Filed: April 1, 1992
    Date of Patent: December 29, 1992
    Assignee: LSI Logic Corporation
    Inventors: Jon Long, Mark Schneider, Sadanand Patil