Abstract: A lead frame for LOC is provided which can reduce a variation in coverage of an insulating adhesive, permitting the fixation of a semiconductor chip and wire bonding to be stably performed. In a lead frame for LOC 10 wherein an insulating adhesive for fixing a semiconductor chip is applied to inner leads 11 in their semiconductor chip mounting region, a coverage regulating lead 14 is provided outside the semiconductor chip mounting region and adjacent to inner leads 11a, 11b located at the end of the semiconductor chip mounting region, permitting the insulting adhesive to be homogeneously applied to each of the inner leads 11 without creating any variation in coverage of the adhesive.

Abstract: A semiconductor lead frame and a fabricating method thereof are provided. The semiconductor lead frame includes a metal substrate, and a multi-layered plating layer including a copper-nickel alloy layer formed on the metal substrate, and a palladium or palladium alloy layer formed on the copper-nickel alloy layer.

Abstract: A semiconductor apparatus that can limit the shifting of a semiconductor device when it is sealed with a sealing resin and can prevent bonding wires from being exposed at the surface of the sealing resin, and that can provide improved resistance to moisture and prevent deterioration of performance and reliability, potting resin structures are affixed to bonding wire mounting faces of a plurality of inner leads before they are sealed by a sealing resin, so that the tops of the potting resin structures are higher than the positions at which the bonding wires are mounted. With this arrangement, the shifting of the semiconductor device is halted by the potting resin structures, the bonding wires are not exposed at the surface of the sealing resin, and the potting resin structures and the sealing resin are closely attached, so that resistance to moisture is improved.

Abstract: A heat sink is constructed in accordance with this invention to increase the spacing surrounding radiating pins which extend outward from a base at the region of highest thermal stress, and to increase the mass of the radiating pins a distance from said region of highest thermal stress to enhance the effects of a thermal differential.

Abstract: A semiconductor device includes a substrate, a semiconductor chip having a lower surface mounted to the substrate, an upper surface and side surfaces, and a frame mounted to the substrate and surrounding the side surfaces of the semiconductor chip. A bonding material is provided between the upper surface of the semiconductor chip and an upper edge of the frame, the bonding material being provided along at least the entire upper surface edges of the semiconductor chip along the entire peripheral edge and the upper edge of the frame for sealing at least the area between the sides of the semiconductor chip and the frame.

Abstract: An IC package suitable for high density mounting and high speed is provided, by improving the humidity resistance and mounting stress resistance at a resin-sealed type BGA package and improving the reliability lessened a warp of the package. A concave part is provided in a multi-layer wiring substrate which has an exhaling route of water vapor expanded by heat in the inside of the package and a semiconductor chip is mounted at the concave part and is connected electrically to the substrate and the upper surface and sides of the package is sealed with resin. By this constitution, the infiltration of water is prevented and the stress at receiving thermal stress is lessened and the occurrence of stripping and crack of the inside of the package is prevented. Moreover, by utilizing the concave part effectively and connecting electrically, the wiring length is shortened and the high frequency characteristic is improved.

Abstract: A package for a semiconductor chip including a plurality of input/output pads includes an insulating layer and a plurality of conductive traces. The insulating layer has a first surface for bonding with the surface of the semiconductor chip so that the input/output pads are exposed adjacent the insulating layer. The conductive traces are provided on a second surface of the insulating layer opposite the first surface wherein each of the conductive traces corresponds to a respective one of the input/output pads. In particular, the conductive traces are adapted to receive a plurality of bonding wires each of which corresponds to a respective one of the input/output pads. Accordingly, each of the bonding wires can be bonded at a first end to the respective input/output pad and at a second end to the respective conductive trace.

Abstract: A semiconductor device in which a flat inner lead is connected to a semiconductor pellet so that a side edge of the inner lead is connected to the semiconductor pellet. The lead includes a constricted portion that is twisted so that the side edge faces a surface of the pellet to which the lead is connected. A lead frame is arranged so that the side edge can be twisted into position.

Abstract: Apparatus and method of increasing the distance of the gap between a lead frame and a semiconductor die surface in a package assembly. An adhesive layer and a gap increasing layer are disposed between the lead frame and the semiconductor die surface. The gap increasing layer has a thickness selected to reduce likelihood of package particles from being trapped between the lead frame and the die surface. The gap increasing layer includes silver plating, and has a thickness of at least about 300 to 500 microinches.

Abstract: A lead frame having a plurality of metallic conductors with each conductor having a coined or stamped region near its proximal end but spaced therefrom to provide pressure points to assure substantial even joining of the conductor to semiconductor chip via an insulative adhesive medium. The lead frame, when mounted on the active face of a semiconductor chip, has wires connecting terminals on the major active surface of the semiconductor chip to the bands on selected lead frame conductors. The lead frame on the semiconductor chip and the wires which connect the semiconductor chip terminals to the bands of selected lead frame conductors are then encapsulated with a suitable insulative material to form a semiconductor module or package.

Abstract: A semiconductor apparatus includes a semiconductor chip and a die pad on which the semiconductor chip is mounted. The die pad is provided thereon with an opening. The semiconductor chip and the die pad may be shaped to be similar figures of rectangle, and the opening may include a plurality of first slits which are arranged around the corners of the die pad, respectively.

Abstract: A semiconductor package having a light, thin, simple and compact structure including outer leads having a minimum length and a resin encapsulate having a minimum volume. The semiconductor package includes a package body, a semiconductor chip mounted on a central portion of the body, inner and outer leads bonded to a peripheral portion of an upper surface of the body by an insulating layer in such a manner that the leads are supported on the body, conductive wires or bumps for electrically connecting the inner leads to the semiconductor chip, a resin encapsulate for encapsulating the semiconductor chip, the conductive wires or bumps and the inner leads. Each outer lead has an end positioned at a level higher than an upper surface of the semiconductor chip so that a boundary portion defined between the associated outer and inner leads serves as a barrier for the resin encapsulate. The end of each outer lead is exposed outside the resin encapsulate and extending to a peripheral edge of the body.

Abstract: One embodiment of a semiconductor device includes a semiconductor chip having long sides. A system carrier is connected to the semiconductor chip and has an island. The island has an opening formed centrally therein over a large area. The opening is wider than the semiconductor chip on two of the long sides of the semiconductor chip. Another embodiment of a semiconductor device includes a semiconductor chip having corner regions. A system carrier is connected to the semiconductor chip and has an island with an opening formed therein. The semiconductor chip is joined to the island only in the corner regions.

Abstract: A semiconductor packaging device includes a printed circuit board substrate, a mold gate formed on a periphery of the printed circuit board substrate through which a package encapsulant is poured to enclose electric elements mounted on a side of the printed circuit board, and a layer of non-metallic material covered on the side of the printed circuit board substrate in the mold gate area. The package encapsulant, after hardened, is bonded with the layer of non-metallic material, and the bonded package encapsulant/the layer of non-metallic material is degatable from the mold gate.

Abstract: In a plastic packaged semiconductor device, a chip support formed on the same lead frame as leads is disposed so as to extend over the surface of a semiconductor element, the chip support is bonded and fixed to the surface of a polyimide wafer coat on the semiconductor element by means of an insulating tape, the leads are brought into contact with the polyimide wafer coat on the semiconductor element without being fixed, the leads and the electrodes of the semiconductor element are connected by means of gold wires, and these are packaged by a packaging material. Generation of crack in the sealing material thereby prevented, and the thickness of the plastic packaged semiconductor device is reduced.

Abstract: A lead frame is prepared which has a plurality of leads whose inner lead portions are coupled to a support member and a notch formed across the bottom surface of each inner lead portion near at its front portion on the support member side. After an LSI chip is adhered to the support member, pads on the chip are connected via bonding wires to corresponding inner leads of the plurality of leads. The chip and inner lead portions are buried in an insulating layer made of resin or the like as protective coating. Each inner lead portion is cut with a cutting device such as laser beam at the notch position to separate the inner lead portion from the support member. Thereafter, the separated assembly unit is accommodated in a package made of resin or the like, and the outer leads are cut and shaped. For an assembly method of a semiconductor device including a wire bonding process, bonding defects to be caused by deformed leads can be reduced.

Abstract: The present invention provides printed circuit boards for mounting to a semiconductor integrated circuit die. In one embodiment the printed circuit boards comprise a rigid dielectric substrate having a planar face, a plurality of circuit lines affixed to the face of the substrate, and a plurality of conductive bumps affixed to the face of the substrate. Each conductive bump has an upper bonding surface that is substantially planar and a lateral surface which is essentially perpendicular to the face of the substrate. The conductive bumps and the circuit lines are formed from a single metallic layer. The conductive bumps and circuit lines constitute a unitary, integral structure, i.e., each conductive bump and connecting circuit line lack a physical interface therebetween. The upper surfaces of the conductive bumps extend to essentially the same height above the surface of the substrate, i.e., the upper surfaces of the conductive bumps are substantially coplanar relative to each other.

Abstract: An improved leadframe structure and an improved IC package and process using such structure are disclosed. The improved leadframe structure eliminates the dambar commonly found on leadframes for use in plastic packages. A polymer structure is formed and employed primarily to act as a barrier to flashing during the epoxy encapsulation process and secondarily to provide support for the leads. The polymer structure remains a permanent part of the IC package following molding. An improved IC packaging process using the improved leadframe design eliminates common debar, dejunk and deflash operations, resulting in reduced capital costs and higher yields.

Abstract: A lead frame structure of a semiconductor package including a plurality of leads, a respective dam bar extended from at least one of the plurality leads toward an adjacent lead and having a certain distance provided between the respective dam bar and the adjacent lead, and an insulating adhesive member is filled between the leads and the dam bars. The lead frame structure prevents leads from bending or twisting.

Abstract: A method of forming high definition elements for electrical and electronic devices, substrates, and other components from or including viscous material. The method includes applying a de-wetting agent to a surface bordering the viscous material prior to applying the viscous material. The de-wetting agent causes the viscous material to "bead-up.

Abstract: A semiconductor device package is equipped with devices for preventing the formulation of air traps in its encapsulated package body. These devices include dummy block leads formed on the outermost inner lead of each row of inner leads, and extended portions formed on each tie bar. Each dummy block lead extends from the end of an outermost inner lead and is integrally formed therewith. The tie bar extended portions are separated into several parts defined by spaces between the parts, and the several parts are formed integral with each other and with the tie bar. The dummy block leads and the tie bar extended portions may be formed so as to be inclined relative to horizontal and with jagged edges at their side surfaces. The dummy block leads and tie bar extended portions serve to reduce the velocity of the potting resin which forms the encapsulate, as it enters the die cavity for encapsulation, but before the resin actually contacts the chip or the inner leads.

Abstract: A leadframe includes a leadframe finger support for supporting elongate leadframe fingers. These elongate leadframe fingers are subject to damage prior to or during the assembly process. Through the provision of the leadframe finger support, the leadframe fingers may be supported at an intermediate position along their length as necessary to prevent bending. The support may be severed from the dam bar in the course of singulation.

Abstract: Composition, method, and products for the environmental protection of integrated circuits comprising a robotically dispensible, wave solderable, low moisture absorbing urethane polymer reaction product of an aliphatic isocyanate, a flexibilizing low molecular weight rubbery polymer having isocyanate reactive hydroxyl terminals, and a diamine arranged to bodily encapsulate the integrated circuit within a dam of thixotropic version of the same polymer, the encapsulation being free of popcorning response to rapid heat rise after high humidity conditioning and otherwise superior as an IC encapsulant.

Abstract: A lead frame is made from a body including a Cu layer and stacked plate layers including an Ni layer, a Pd layer and an Au layer formed on the body. The lead frame includes a die pad, die-pad supports, inner leads, dam-bars, outer leads and an outer frame. No Au layer is formed in a gate runner portion. Since the Pd layer with poor adhesion to a sealing resin is exposed in the gate runner portion, the sealing resin remaining in the gate runner portion can be easily removed by punching pilot holes from the rear side after completing a resin sealing procedure. Thus, the lead frame can be definitely prevented from being deformed without providing any additional element.

Abstract: Disclosed are methods and apparatuses for manufacturing a semiconductor device package utilizing a lead frame which has one or more encapsulant material flow diverters. The lead frame having material flow diverters includes a multiplicity of leads and at least material flow diverter. The material flow diverter is arranged in such a manner as to control the amount of encapsulant material which is directed both above and below an attached die during the encapsulation process.

Abstract: A circuit including an active area, at least one bond pad and a corral formed on the circuit between the active area and the bond pad. A method including providing a circuit with an active area and at least one bond pad and forming a corral on the circuit between the active area and the bond pad. Embodiments of the present invention contain materials placed over the active area of a circuit preventing them from engaging areas outside the corral.

Abstract: A highly reliable semiconductor device with an increased life is provided as comprising a wiring substrate comprising a portion for mounting a semiconductor pellet, a semiconductor pellet mounted on the portion for mounting the semiconductor pellet, an electrode provided on the wiring substrate connected to an electrode of the semiconductor pellet, a layer comprising a sealing material which seals the semiconductor pellet and the electrode provided on the wiring substrate, wherein at least a through hole for discharging water vapor is formed in the portion for mounting the semiconductor pellet provided on the wiring substrate, and the protective film for preventing the adhesion of solder or plating is removed from not only the soldered or plated portion but also the periphery of the portion for mounting the semiconductor pellet.

Abstract: A semiconductor device comprises a multiple-terminal integrated circuit formed on a substrate. The integrated circuit is formed on the upper surface of the substrate and electrically connected to a plurality of external terminals arranged on an under surface of the substrate. Part of a sealing member is embedded in a plurality of through-holes. The through holes are provided in the substrate to be in the vicinity of the plurality of external terminals. The sealing member seals the upper surface of the substrate, with the integrated circuit formed thereon.

Abstract: For manufacturing a packaged semiconductor device, a lead frame with an electrically insulating strip member and a semiconductor chip is placed in a molding unit having upper and lower dies. The upper and lower dies have recessed areas for determining a size of a cavity of the molding unit different from each other, the size of the cavity being measured in a direction perpendicular to a clamping motion direction of the dies. The lead frame is positioned so that a surface of each lead with the insulating strip member applied thereto is contacted with one of the upper and lower dies having a larger recessed area and a molding line of the molding unit intersects the insulating strip member. The molding unit is closed to clamp the lead frame to depress and thrust into spaces between adjacent leads that part of the strip member which is outside the molding line and to form the cavity of the molding unit.

Abstract: A surface mount semiconductor package employs locking elements for locking a plastic housing to a metal pad on which a semiconductor device is mounted. The package includes terminals having elongated crushable beads on their side surfaces adjacent the portions of the terminals just outside the plastic housing. The beads are crushed inwardly by a molding tool when it closes to provide a seal which prevents the molding plastic from bleeding out and over the sides of the terminals which extend beyond the housing and which could interfere with solder connection to the terminals.

Abstract: According to the present invention, a semiconductor package is provided. In one version of the invention, the semiconductor package includes a laminated substrate having a semiconductor die mounted on its upper surface, electrical connections between bond pads on the semiconductor die and conductive traces on the substrate, as well as electrical connections between the conductive traces and electrical contacts on the lower surface of the substrate. The semiconductor package also includes a molded covering on the upper surface of the substrate which covers the semiconductor die and the electrical connections. The molded covering has a mold body portion and a mold gate runner which extends from the mold body portion to an edge of the substrate. The mold gate runner is provided with a surface that is substantially even with the edge of the substrate and rises perpendicularly from the upper surface of the substrate.

Abstract: A semiconductor device package includes a semiconductor chip and a plurality of inner leads, each having at least one slot formed along an upper surface of the inner lead. An adhesive layer is used to attach a bottom surface of the semiconductor chip to the upper surface of the inner lead. An encapsulant is allowed to flow in a package body mold, around the inner leads and through the slot. The slots prevent the production of turbulence along a side surface of the inner lead opposite to the flow direction, thereby avoiding problems associated with incomplete encapsulation such as the internal voids.

Abstract: A semiconductor integrated circuit device includes a semiconductor integrated circuit chip, a IC package enclosing the semiconductor integrated circuit chip, lead terminals, and dummy terminals. The lead terminals are partly embedded in the IC package side by side along its opposed sides, and the dummy terminals are partly embedded in the IC package at both ends of a line of the lead terminals. These terminals are electrically connected with the circuit formed in the chip. One end of each terminal protrudes from either of the opposed sides of the IC package and has a connection to be connected with terminal electrodes of a packaging substrate. The dummy terminals are made wider and/or longer than the lead terminals so as to make their connections larger than those of the lead terminals, thereby enhancing their reliability in point of machine-resistance and heat-resistance.

Abstract: Disclosed herein are a plastic molded type semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a semiconductor element having electrodes provided on a surface thereof, a dambar formed along the outer periphery of the surface of the semiconductor element, a plurality of leads respectively electrically connected to the electrodes and provided inside the dambar but electrically independent of the dambar, and a mold resin body within a region surrounded by the dambar and formed so as to expose parts of the leads.

Abstract: A heat spreader to be molded into an encapsulated IC package in contact with a die attach pad carrying an IC die is adapted to be placed in a substantially rectangular mold cavity and to retain its position in the cavity while encapsulation material is injected. The heat spreader has a body portion with appendages extending toward each of the four walls, and the ends of the appendages furthest from the body are formed downward such as by bending to provide a support for the spreader from the bottom surface of the mold cavity substantially at the lines where the sidewalls meet the bottom surface of the mold cavity. In a preferred embodiment there are two appendages toward each sidewall, and the heat spreader before and during the molding process is supported from the bottom surface of the mold cavity by dimples through the body, forming additional supports.

Abstract: An inexpensive pre-molded package for electronic semiconductor circuit with increased thermal extraction capability, improved electrical performance, improved dielectric constant of sealing medium, optically transmissive sealing lid, and partially reduced electromagnetic radiation. In one embodiment, the pre-molded package includes electronic semiconductor circuit, a plurality of electrically conductive leads, a heat spreader, a plurality of electrically conductive bond wires, and a seal lid. Preferably, a surface of the heat spreader remains exposed to the exterior of the pre-molded package. In another embodiment, the pre-molded package includes a semiconductor circuit, a plurality of electrically conductive leads, a heat spreader, a plurality of electrically conductive bond wires, and an optically transmissive seal lid.

Abstract: A lead frame having a die pad of such a shape that prevents scattering of solder to lead when a chip is mounted on the lead frame, and a semiconductor device using such a lead frame are provided. The lead frame includes a die pad having a region surrounded by a first side, a second side opposing to the first side, a third side different from the first and second sides, and a fourth side opposing to the third side, and a lead formed of a conductor and electrically connected to a semiconductor element. The die pad includes a notch extending along the first and the second sides and positioned opposing to a main surface of the semiconductor element, and a through hole extending along the third and fourth sides and positioned opposing to the main surface of the semiconductor element. The semiconductor device employs the die pad.

Abstract: A microelectronic assembly (10) includes an integrated circuit component (14) attached to a polymeric substrate (12) by a plurality of unencapsulated solder bump interconnections (16). A collar (18) is affixed to the polymeric substrate (12) about the integrated circuit component (14) and is formed of an inorganic material having a coefficient of thermal expansion less than that of the substrate (12). The collar (18) constrains thermal expansion of the polymeric substrate (12) in the die attach region (22), thereby lessening any deleterious effects caused by a mismatch in the thermal expansion of the polymeric substrate (12) and the integrated circuit component (14).

Abstract: A method for manufacturing an electronic component by seal-molding with resin a die pad mounted by an electronic element thereon and loads of input-and-output terminals which are supported by a lead frame having an outer frame and removing such sealed electronic component with mold materials from the outer frame of the lead frame which includes suspending pins for supporting the leads and a first mold holder disconnected from the leads, the method including the steps of resin molding a first mold member on the leads and the first mold holder to join the leads and the first mold member with the first mold member, cutting the suspending pins between the first mold member and the outer frame, resin-molding a second mold member on the first mold member to cover the cut ends of the suspending pins, and cutting the first mold holder between the second mold member and the outer frame to remove thus molded electronic component from the lead frame.

Abstract: A multi-layer bottom lead package of the present invention has semiconductor chips having: (a) bonding pads; (b) an insulating circuit film including (i) an insulating base film with through holes, (ii) first metal lines formed on upper and lower faces of the base film, (iii) protruding, conductive inner pads which are respectively formed on the first metal lines, being respectively connected to said bonding pads of each semiconductor chip, (iv) protruding, conductive outer pads which are formed on the first metal line, and (v) second metal lines formed along wall surface of the through holes to connect to the inner pads of each semiconductor chip; (c) a lead frame including an inner lead and outer lead for electrically connecting the outer pads of the insulating circuit film to an external device; and (d) a package body of encapsulating a predetermined area containing the semiconductor chips, the insulating circuit film and the inner leads of the lead frame, including a plurality of dimples formed at electri

Abstract: An LOC semiconductor package includes: a semiconductor chip; a plurality of two-sided tapes being attached on predetermined portions of the semiconductor chip inthe form of layers; a lead frame having a step coverage corresponding to the form of the two-sided tape; wires electrically connecting inner leads of the lead frame to pads of the semiconductor chip; and a coating fluid for covering the semiconductor chip, the lead frame and the wires. Its fabricating method includes the steps of: forming an LOC lead frame having dam bars for a chip size package; attaching a plurality of two-sided tapes on the dam bars of the lead frame in the form of layers; attaching a semiconductor chip onto an uppermost layer of said plurality of two-sided tapes; wire-bonding a pad of the semiconductor chip to respective inner leads of the lead frame by using a conductive means; and potting to inject a coating fluid into the lead frame.

Abstract: An integrated circuit device package of this invention includes a flexible substrate having an upper patterned insulative layer, and a lower patterned conductive layer including a plurality of package leads. An integrated circuit die is fixed within a void of the upper surface of the flexible substrate. Electrical connections between the integrated circuit die and the package leads are provided. A rigid upper protective layer is present. The rigid upper protective layer encloses the integrated circuit die, and at least partially covers the top surface of the upper insulative layer. The semiconductor device package further comprises a rigid or semi-rigid metal lower protective layer opposite the upper protective layer including a ground plane proximal to the electrical leads and a power plane distal to the leads. Methods of production are also given.

Abstract: The present invention is characterized by providing leads not contributing to actual connection outside the corner leads to prevent the deformation of the corner leads and improve the yield of tape carriers. A device hole is made in a near-central place of an insulating resin film. Around the device hole, outer-lead holes are made. On the insulating resin film, a plurality of wiring patterns are provided and forced to project into the device hole. The plurality of wiring patterns are formed into a plurality of inner leads, of which the outermost ones are determined to be corner leads. On each corner of the device hole, an aligning mark is provided. Dummy leads are provided closer to the aligning marks. The dummy leads are made shorter than the inner leads and corner leads.

Abstract: Encapsulated thermally enhanced (TE) and electrically and thermally enhanced (ETE) integrated circuit assemblies that include bulky thermally conductive heat sinks are disclosed. The integrated circuit assemblies are configured to prevent the formation of pinholes and IC package warpage without adding bulk or additional structures. The assemblies are repositioned, through an offset in the bonding fingers of the leadframe, so that the rates of mold flow in the two halves of the mold cavity are substantially balanced. The repositioning of the assemblies also substantially balances the amount of mold material in the mold halves, which prevents warpage in a finished IC package.

Abstract: A reusable metal frame for manufacturing of encapsulated semiconductor devices includes a metal sheet having a plurality of openings disposed in compliance with topology of semiconductor devices carried by a supporting structure. During the molding operation, the frame is superposed over the supporting structure with each semiconductor device to be encapsulated, positioned centrally within one of the openings. The encapsulating material (resin, plastic, or the like) is supplied to each semiconductor device and stays within each opening, held in place by continuous uninterrupted contour of each opening. After the encapsulating material has been cooled, the metal frame is readily removed, and may be used in other molding operations.

Abstract: A semiconductor device has a semiconductor chip mounted on the mounting portion of a lead frame and sealed with resin. The chip is affixed to the lead frame by melting. A groove is formed in the lead frame in a cruciform, radial, lattice or similar pattern capable of reducing thermal stress during intermittent performance test and cycling test while insuring heat radiation.

Abstract: A semiconductor device including a plurality of grooves (21) formed on a top surface of a heat sink (51). A sealing resin (2) fills a portion between a lead frame (5) provided facing the top surface and the heat sink (51). The grooves (21) are formed on both sides of a center region (22) extending so as to divide the top surface in two. A power semiconductor element (11) is disposed above the center region (22) and a controlling semiconductor element (16) controlling the power semiconductor element (11) is disposed above the region where the grooves (21) are formed. The above construction suppresses thermal resistance interposed in a path through which heat loss in the power semiconductor element (11) is radiated to the heat sink (51) and improves heat radiating efficiency while maintaining close contact between the sealing resin (2) and the heat sink (51).

Abstract: A lead frame includes a base member having a device hole for accommodating a semiconductor chip therein, a plurality of inner lead portions extended outward from respective sides of the device hole, outer lead portions electrically connected to the inner lead portions, respectively, an adhesion area to which the inner lead portions formed on the base member are adhered, and a plurality of dummy leads disposed on a portion of the adhesion area where a density of the inner lead portions is low.

Abstract: A method of packaging an integrated circuit. An integrated circuit is connected to a substrate. A reservoir body is applied to the substrate, and the reservoir body and substrate define at least one reservoir and at least one flow gate. The reservoir body, substrate, and integrated circuit define a flow ring which extends at least partially around the circumference of the integrated circuit. A compound is dispensed into the reservoirs, and is flowed through the flow gates and into the flow ring, underfilling the integrated circuit.

Abstract: A highly reliable semiconductor device with an increased life is provided as comprising a wiring substrate comprising a portion for mounting a semiconductor pellet, a semiconductor pellet mounted on the portion for mounting the semiconductor pellet, an electrode provided on the wiring substrate connected to an electrode of the semiconductor pellet, a layer comprising a sealing material which seals the semiconductor pellet and the electrode provided on the wiring substrate, wherein at least a through hole for discharging water vapor is formed in the portion for mounting the semiconductor pellet provided on the wiring substrate, and the protective film for preventing the adhesion of solder or plating is removed from not only the soldered or plated portion but also the periphery of the portion for mounting the semiconductor pellet.